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| printed in japan document no. u14492ej4v1ud00 (4th edition) date published april 2004 n cp(k) v850e/ia1 32-bit single-chip microcontrollers hardware user?s manual pd703116 pd703116(a) pd703116(a1) pd70f3116 pd70f3116(a) pd70f3116(a1) 1999, 2002
2 user?s manual u14492ej4v1ud [memo] 3 user?s manual u14492ej4v1ud 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices 4 user?s manual u14492ej4v1ud these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of january, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 5 user?s manual u14492ej4v1ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: 6 user?s manual u14492ej4v1ud introduction readers this manual is intended for users who wish to understand the functions of the v850e/ia1 and design application systems using it. the target products are as follows. standard products: pd703116, 70f3116 special products: pd703116(a), 703116(a1), 70f3116(a), 70f3116(a1) purpose this manual introduces the hardware func tions of the v850e/ia1 shown below for user?s understanding. organization this manual is divided into two parts: hardware (this manual) and architecture (v850e1 architecture user?s manual). hardware architecture ? pin functions ? data type ? cpu function ? register set ? internal peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupt and exception ? electrical specifications ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. cautions 1. the application examples in this manual a pply to ?standard? quality grade products for genera l electronic systems. when using an example in this manual fo r an application that requires a ?special? quality grade product, thoroughly evaluate the component and circuit to be actually used to see if they satisfy the special quality grade. 2. when using this manual as a manual for a special grade product, read the part numbers as follows. pd703116 703116(a), 703116(a1) pd70f3116 70f3116(a), 70f3116(a1) ? to find the details of a regi ster where the name is known refer to appendix c register index . ? to understand the details of an instruction function refer to the v850e1 architecture user?s manual . ? to know details of the electric al specifications of the v850e/ia1 refer to chapter 18 electrical specifications . 7 user?s manual u14492ej4v1ud ? to understand the overall f unctions of the v850e/ia1 read this manual according to the contents. how to read register formats the name of a bit whose number is in angle brackets (<>) is defined as a reserved word in the device file. when the register format of each register describes 0 or 1, other values are prohibited to be specified. the mark shows major revised points. conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher address on the top and lower address on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 data type: word ... 32 bits halfword ... 16 bits byte ... 8 bits related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850e/ia1 document name document no. v850e1 architecture user?s manual u14559e v850e/ia1 hardware user?s manual this manual v850e/ia1, v850e/ia2 ac motor inverter control using vector operation application note u14868e v850 series flash memory self-p rogramming user?s manual u15673e 8 user?s manual u14492ej4v1ud documents related to developm ent tools (user?s manuals) document name document no. ie-v850e-mc, ie-v850e-mc-a (i n-circuit emulator) u14487e ie-703116-mc-em1 (in-circuit em ulator option board) u14700e operation u16053e c language u16054e ca850 ver. 2.50 c compiler package assembly language u16042e pm plus ver. 5.10 u16569e id850 ver. 2.50 integrated debugger operation u16217e sm850 ver. 2.50 system simulator operation u16218e sm850 ver. 2.00 or later system si mulator external part user open interface specification u14873e basics u13430e installation u13410e rx850 ver. 3.13 or later real-time os technical u13431e basics u13773e installation u13774e rx850 pro ver. 3.15 real-time os technical u13772e rd850 ver. 3.01 task debugger u13737e rd850 pro ver. 3.01 task debugger u13916e az850 ver. 3.20 system performance analyzer u14410e pg-fp4 flash memory programmer u15260e 9 user?s manual u14492ej4v1ud contents chapter 1 introduction ...................................................................................................... ...........18 1.1 outline........................................................................................................................ ................ 18 1.2 features ....................................................................................................................... .............. 21 1.3 applications................................................................................................................... ............ 22 1.4 ordering information ........................................................................................................... ..... 23 1.5 pin configuration (top view)........................................ ........................................................... 24 1.6 configuration of function block................................... .......................................................... 26 1.6.1 internal bl ock di agram ......................................................................................................... .........26 1.6.2 internal units................................................................................................................. ................27 1.7 differences between products ...................................... .......................................................... 29 chapter 2 pin functions .................................................................................................... ............30 2.1 list of pin functions .......................................................................................................... ...... 30 2.2 pin status..................................................................................................................... .............. 36 2.3 description of pin functions ......................................... .......................................................... 37 2.4 types of pin i/o circuit and connection of unused pins..................................................... 45 2.5 pin i/o circuits ............................................................................................................... ........... 47 chapter 3 cpu function..................................................................................................... ............48 3.1 features ....................................................................................................................... .............. 48 3.2 cpu register set ............................................................................................................... ....... 49 3.2.1 program regi ster set........................................................................................................... ..........50 3.2.2 system regi ster set............................................................................................................ ...........51 3.3 operation modes................................................................................................................ ....... 53 3.3.1 operation modes................................................................................................................ ..........53 3.3.2 operation mode specific ation ................................................................................................... ....54 3.4 address space .................................................................................................................. ........ 55 3.4.1 cpu addre ss space .............................................................................................................. .......55 3.4.2 image .......................................................................................................................... .................56 3.4.3 wrap-around of cpu address s pace............................................................................................57 3.4.4 memory map ..................................................................................................................... ...........58 3.4.5 area........................................................................................................................... ...................59 3.4.6 external memo ry expans ion ...................................................................................................... ...63 3.4.7 recommended use of address s pace ..........................................................................................64 3.4.8 on-chip periphera l i/o registers ............................................................................................... ....66 3.4.9 programmable peripheral i/o regist ers ........................................................................................77 3.4.10 specific re gisters ............................................................................................................. .............94 3.4.11 system wait control register (vswc) ...........................................................................................9 4 3.4.12 cautio ns ....................................................................................................................... ................94 chapter 4 bus control function............................................................................................ .95 4.1 features ....................................................................................................................... .............. 95 4.2 bus control pins............................................................................................................... ........ 95 4.2.1 pin status during internal rom, internal ram, and on-chip per ipheral i/o access .......................95 4.3 memory block function .......................................................................................................... .96 10 user?s manual u14492ej4v1ud 4.3.1 chip select co ntrol f unction ................................................................................................... ...... 97 4.4 bus cycle type control function .................................... ..................................................... 100 4.5 bus access ..................................................................................................................... ......... 101 4.5.1 number of ac cess cl ocks........................................................................................................ ... 101 4.5.2 bus sizing functi on............................................................................................................ ......... 102 4.5.3 word data proc essing fo rmat.................................................................................................... . 102 4.5.4 bus wid th ...................................................................................................................... ............. 103 4.6 wait function.................................................................................................................. ......... 109 4.6.1 programmable wa it func tion ..................................................................................................... . 109 4.6.2 external wait function ......................................................................................................... ....... 111 4.6.3 relationship between programmable wait a nd external wait ..................................................... 111 4.7 idle state insertion function............................................. ..................................................... 112 4.8 bus hold function .............................................................................................................. .... 113 4.8.1 function ou tline ............................................................................................................... .......... 113 4.8.2 bus hold pr ocedure ............................................................................................................. ...... 113 4.8.3 operation in powe r save mode.................................................................................................. 1 14 4.8.4 bus hold timing ................................................................................................................ .......... 114 4.9 bus priority order ............................................................................................................. ...... 115 4.10 boundary operation conditions....................................... ..................................................... 115 4.10.1 program space .................................................................................................................. ........ 115 4.10.2 data s pace ..................................................................................................................... ........... 115 chapter 5 memory access control function .................................................................116 5.1 sram, external rom, external i/o interface........................................................................ 116 5.1.1 featur es ....................................................................................................................... ............. 116 5.1.2 sram, external rom, external i/o access ............................................................................... 117 chapter 6 dma functions (dma controller) ....................................................................122 6.1 features ....................................................................................................................... ............ 122 6.2 configuration.................................................................................................................. ......... 123 6.3 control registers .............................................................................................................. ...... 124 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3 ) ............................................................. 124 6.3.2 dma destination address register s 0 to 3 (dda 0 to dda 3) ...................................................... 126 6.3.3 dma transfer count registers 0 to 3 (dbc0 to dbc3 )................................................................ 128 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc 3) ................................................... 129 6.3.5 dma channel control register s 0 to 3 (dchc 0 to dchc3 )........................................................ 131 6.3.6 dma disable status register (ddis)........................................................................................... 13 3 6.3.7 dma restart regi ster (drst) .................................................................................................... . 133 6.3.8 dma trigger factor registers 0 to 3 (dtfr0 to dtfr 3) ............................................................. 134 6.4 dma bus states................................................................................................................. ...... 136 6.4.1 types of bus states ............................................................................................................ ....... 136 6.4.2 dmac bus cycle st ate trans ition................................................................................................ 137 6.5 transfer mode.................................................................................................................. ........ 138 6.5.1 single trans fer m ode ........................................................................................................... ...... 138 6.5.2 single-step tran sfer mode ...................................................................................................... ... 140 6.5.3 block trans fer m ode............................................................................................................ ....... 140 6.6 transfer types................................................................................................................. ........ 141 6.6.1 two-cycle tr ansfer ............................................................................................................. ........ 141 11 user?s manual u14492ej4v1ud 6.7 transfer target................................................................................................................ ........ 142 6.7.1 transfer type and transfer target .............................................................................................. ..142 6.7.2 external bus cycles during dma transfer (two-cycl e transfe r) ....................................................143 6.8 dma channel priorities ......................................................................................................... . 143 6.9 next address setting function ..................................... ........................................................ 143 6.10 dma transfer start factors ................................................................................................... 14 5 6.11 forcible interruption.......................................................................................................... ..... 146 6.12 dma transfer end............................................................................................................... .... 146 6.13 forcible termination ........................................................................................................... ... 146 6.13.1 restriction related to dma tr ansfer forcible terminatio n .............................................................146 6.14 times related to dma transfer............................................................................................. 148 6.15 precautions.................................................................................................................... .......... 148 6.15.1 interrupt factors ............................................................................................................. ............149 chapter 7 interrupt/exception processing function..................................................150 7.1 features ....................................................................................................................... ............ 150 7.2 non-maskable interrupt......................................................................................................... . 153 7.2.1 operation ...................................................................................................................... .............154 7.2.2 restore........................................................................................................................ ...............156 7.2.3 non-maskable interrupt status fl ag (np) ....................................................................................157 7.2.4 edge detecti on func tion........................................................................................................ ......157 7.3 maskable interrupts ............................................................................................................ .... 158 7.3.1 operation ...................................................................................................................... .............158 7.3.2 restore........................................................................................................................ ...............160 7.3.3 priorities of ma skable inte rrupts .............................................................................................. ...161 7.3.4 interrupt control r egister ( xxicn)............................................................................................. ....165 7.3.5 interrupt mask registers 0 to 3 (imr0 to imr3 ) ..........................................................................168 7.3.6 in-service priority register (ispr) ............................................................................................ ...169 7.3.7 maskable interrupt st atus flag (id)............................................................................................ ..170 7.3.8 interrupt trigger mode sele ction............................................................................................... ...170 7.4 software exception............................................................................................................. .... 179 7.4.1 operation ...................................................................................................................... .............179 7.4.2 restore........................................................................................................................ ...............180 7.4.3 exception stat us flag (ep) ..................................................................................................... .....181 7.5 exception trap ................................................................................................................. ....... 182 7.5.1 illegal opcode definit ion...................................................................................................... ........182 7.5.2 debug trap ..................................................................................................................... ............184 7.6 multiple interrupt servicing contro l ..................................................................................... 186 7.7 interrupt response time........................................................................................................ 187 7.8 periods in which interrupts are not acknowledged .. ........................................................ 189 chapter 8 clock generation function ...............................................................................190 8.1 features ................................................................................................................... ................ 190 8.2 configuration .............................................................................................................. ............ 190 8.3 input clock selection ...................................................................................................... ....... 191 8.3.1 direc t mode .............................................................................................................. ..................191 8.3.2 p ll mode................................................................................................................. ..................191 8.3.3 peripheral comm and register (phcmd).....................................................................................1 92 12 user?s manual u14492ej4v1ud 8.3.4 clock control register (ckc) ............................................................................................. ......... 193 8.3.5 peripheral stat us register (phs) ......................................................................................... ....... 195 8.4 pll lockup................................................................................................................. ............. 196 8.5 power save control ......................................................................................................... ....... 197 8.5.1 ov ervi ew ................................................................................................................. .................. 197 8.5.2 control registers ........................................................................................................ ................ 200 8.5.3 halt mode ................................................................................................................ ............... 203 8.5.4 idle mode................................................................................................................ ................. 205 8.5.5 software stop mode....................................................................................................... ......... 207 8.6 securing oscillation stabilization time........................ ........................................................ 209 8.6.1 oscillation stabilization ti me security s pecificat ion.................................................................... . 209 8.6.2 time base counter (tbc) .................................................................................................. ........ 210 chapter 9 timer/counter function (real-time pulse unit)........................................211 9.1 timer 0.................................................................................................................... .................. 211 9.1.1 features (timer 0) ....................................................................................................... ............... 211 9.1.2 function over view (tim er 0) .............................................................................................. ......... 212 9.1.3 basic c onfigurat ion ...................................................................................................... .............. 213 9.1.4 control registers ........................................................................................................ ................ 219 9.1.5 oper ation................................................................................................................ ................... 243 9.1.6 operat ion timing ......................................................................................................... ............... 274 9.2 timer 1.................................................................................................................... .................. 283 9.2.1 features (timer 1) ....................................................................................................... ............... 283 9.2.2 function over view (tim er 1) .............................................................................................. ......... 283 9.2.3 basic c onfigurat ion ...................................................................................................... .............. 285 9.2.4 control registers ........................................................................................................ ................ 292 9.2.5 oper ation................................................................................................................ ................... 303 9.2.6 supplementary descripti on of internal operatio n........................................................................ 31 5 9.3 timer 2.................................................................................................................... .................. 319 9.3.1 features (timer 2) ....................................................................................................... ............... 319 9.3.2 function over view (tim er 2) .............................................................................................. ......... 319 9.3.3 basic c onfigurat ion ...................................................................................................... .............. 321 9.3.4 control registers ........................................................................................................ ................ 328 9.3.5 oper ation................................................................................................................ ................... 345 9.3.6 pwm output operati on when timer 2 operates in compar e mode .............................................. 363 9.4 timer 3.................................................................................................................... .................. 366 9.4.1 features (timer 3) ....................................................................................................... ............... 366 9.4.2 function over view (tim er 3) .............................................................................................. ......... 366 9.4.3 basic c onfigurat ion ...................................................................................................... .............. 367 9.4.4 control registers ........................................................................................................ ................ 372 9.4.5 oper ation................................................................................................................ ................... 378 9.4.6 applicat ion exam ples ..................................................................................................... ............ 385 9.4.7 prec autions.............................................................................................................. .................. 391 9.5 timer 4.................................................................................................................... .................. 392 9.5.1 features (timer 4) ....................................................................................................... ............... 392 9.5.2 function over view (tim er 4) .............................................................................................. ......... 392 9.5.3 basic c onfigurat ion ...................................................................................................... .............. 393 9.5.4 contro l register ......................................................................................................... ................. 397 13 user?s manual u14492ej4v1ud 9.5.5 oper ation ................................................................................................................ ...................398 9.5.6 applicat ion exam ple ...................................................................................................... .............400 9.5.7 prec auti ons .............................................................................................................. ..................400 9.6 timer connection function ....................................... ........................................................... . 401 9.6.1 ov ervi ew ................................................................................................................. ...................401 9.6.2 contro l register......................................................................................................... ..................402 chapter 10 serial interface function ................................................................................403 10.1 features .................................................................................................................. ................. 403 10.2 asynchronous serial interface 0 (uart0) ........................................................................... 404 10.2.1 f eatur es ................................................................................................................ .....................404 10.2.2 config uration ........................................................................................................... ...................405 10.2.3 control registers ....................................................................................................... ..................407 10.2.4 interrupt requests ...................................................................................................... .................414 10.2.5 oper ation ............................................................................................................... ....................415 10.2.6 dedicated baud ra te generator 0 (b rg0).................................................................................. .427 10.2.7 prec auti ons ............................................................................................................. ...................434 10.3 asynchronous serial interfaces 1, 2 (uart1, u art2) ....................................................... 435 10.3.1 f eatur es ................................................................................................................ .....................435 10.3.2 config uration ........................................................................................................... ...................436 10.3.3 control registers ....................................................................................................... ..................438 10.3.4 interrupt requests ...................................................................................................... .................447 10.3.5 oper ation ............................................................................................................... ....................448 10.3.6 synchr onous mode ........................................................................................................ ............457 10.3.7 dedicated baud rate gener ators 1, 2 (brg 1, brg2 ) .................................................................462 10.4 clocked serial interfaces 0, 1 (csi0, csi1)............ ............................................................... 470 10.4.1 f eatur es ................................................................................................................ .....................470 10.4.2 config uration ........................................................................................................... ...................470 10.4.3 control registers ....................................................................................................... ..................472 10.4.4 oper ation ............................................................................................................... ....................486 10.4.5 out put pi ns ............................................................................................................. ....................501 10.4.6 dedicated baud ra te generator 3 (b rg3).................................................................................. .502 chapter 11 fcan controller ................................................................................................. ...506 11.1 function overview......................................................................................................... ......... 506 11.2 configuration ............................................................................................................. ............. 507 11.3 configuration of messages and bu ffers............................................................................... 509 11.4 time stamp function ....................................................................................................... ...... 510 11.5 message processing ........................................................................................................ ...... 513 11.5.1 message transmi ssion.................................................................................................... ............513 11.5.2 message recept ion ....................................................................................................... ..............515 11.6 mask function ............................................................................................................. ............ 516 11.7 protocol.................................................................................................................. .................. 518 11.7.1 protocol mode func tion.................................................................................................. .............518 11.7.2 message formats......................................................................................................... ...............519 11.8 functions ................................................................................................................. ................ 528 11.8.1 determination of bus pr iority ........................................................................................... ...........528 11.8.2 bit stuffi ng ............................................................................................................ ......................528 14 user?s manual u14492ej4v1ud 11.8.3 mult i-mast er............................................................................................................ ................... 528 11.8.4 mult i-cast .............................................................................................................. ..................... 528 11.8.5 can sleep mode/ca n stop mode f unction ................................................................................ 529 11.8.6 error cont rol func tion .................................................................................................. ............... 529 11.8.7 baud rate co ntrol f unction.............................................................................................. ............ 532 11.9 cautions on bit set/clear function............................... ........................................................ 5 35 11.10 control registers ........................................................................................................ ............ 537 11.11 operations ............................................................................................................... ................ 589 11.11.1 initializat ion processing .............................................................................................. ............... 589 11.11.2 transmi t setti ng ....................................................................................................... .................. 602 11.11.3 receiv e setting ........................................................................................................ .................. 603 11.11.4 can sl eep mo de ......................................................................................................... .............. 605 11.11.5 can stop mo de .......................................................................................................... ............... 606 11.12 rules for correct setting of baud rate ...................... .......................................................... 608 11.13 ensuring data consistency ................................................................................................ ... 612 11.13.1 sequentia l data read ................................................................................................... .............. 612 11.13.2 burst read mo de ........................................................................................................ ................ 613 11.14 interrupt conditions..................................................................................................... ........... 614 11.14.1 interrupts that are gener ated for fcan contro ller...................................................................... 614 11.14.2 interrupts that are generated for global ca n interf ace .............................................................. 614 11.15 how to shut down fcan controller ..................................................................................... 615 11.16 cautions on use .......................................................................................................... ............ 616 chapter 12 nbd function ( pd70f3116) ...................................................................................618 12.1 overview .................................................................................................................. ................ 618 12.2 nbd function register map................................................................................................. .. 619 12.3 nbd function protocol..................................................................................................... ...... 620 12.4 nbd function .............................................................................................................. ............ 623 12.4.1 ram monitoring, a ccessing nbd space.................................................................................... 6 23 12.4.2 event detec tion f unction ................................................................................................ ............ 625 12.4.3 chip id regist ers (tid0 to tid2) ........................................................................................ ........ 626 12.5 control registers ......................................................................................................... ........... 627 12.6 restrictions on nbd ....................................................................................................... ........ 630 12.6.1 general restrict ions .................................................................................................... ............... 630 12.6.2 restrictions related to re ad or write of ram by nbd................................................................. 630 12.6.3 restrictions related to nbd event trigger functi on ..................................................................... 6 30 12.6.4 how to detect termination of dm a initialization via nbd tool..................................................... 630 12.7 initialization required for dma (2 channels) ......... .............................................................. 631 chapter 13 a/d converter ................................................................................................... .......635 13.1 features .................................................................................................................. ................. 635 13.2 configuration............................................................................................................. .............. 635 13.3 control registers ......................................................................................................... ........... 639 13.4 interrupt requests ........................................................................................................ .......... 648 13.5 a/d converter operation ................................................................................................... ..... 649 13.5.1 a/d converter basic oper ation ........................................................................................... ........ 649 13.5.2 operation mode s and trigger modes ....................................................................................... .. 650 13.6 operation in a/d trigger mode ............................................................................................. . 653 15 user?s manual u14492ej4v1ud 13.6.1 operation in select mode ................................................................................................ ...........653 13.6.2 operation in scan mode .................................................................................................. ...........654 13.7 operation in a/d trigger polling mode................................................................................. 655 13.7.1 operation in select mode ................................................................................................ ...........655 13.7.2 operation in scan mode .................................................................................................. ...........656 13.8 operation in timer trigger mode .............................. ............................................................ 6 57 13.8.1 operation in select mode ................................................................................................ ...........657 13.8.2 operation in scan mode .................................................................................................. ...........658 13.9 operation in external trigger mode........................ .............................................................. 65 9 13.9.1 operation in select mode ................................................................................................ ...........659 13.9.2 operation in scan mode .................................................................................................. ...........660 13.10 precautions on operation ................................................................................................. ..... 661 13.10.1 stopping a/d conv ersion oper ation ...................................................................................... ......661 13.10.2 trigger input during a/d conversi on operat ion .......................................................................... .661 13.10.3 external or ti mer trigger interval ..................................................................................... ............661 13.10.4 operation in standby modes ............................................................................................. .........661 13.10.5 compare match interrupt in timer tr igger mode .......................................................................... 662 13.10.6 timing that makes the a/d conversion resu lt undef ined ............................................................662 13.11 how to read a/d converter ch aracteristics table ............................................................. 663 chapter 14 port functions .................................................................................................. ......667 14.1 features .................................................................................................................. ................. 667 14.2 basic configuration of ports ................................... ........................................................... ... 667 14.3 pin functions of each port ...................................... .......................................................... .... 682 14.3.1 port 0.................................................................................................................. ........................682 14.3.2 port 1.................................................................................................................. ........................683 14.3.3 port 2.................................................................................................................. ........................686 14.3.4 port 3.................................................................................................................. ........................689 14.3.5 port 4.................................................................................................................. ........................691 14.3.6 po rt dh ................................................................................................................. .....................693 14.3.7 po rt dl ................................................................................................................. ......................695 14.3.8 po rt cs................................................................................................................. ......................697 14.3.9 po rt ct................................................................................................................. ......................699 14.3.10 po rt cm ................................................................................................................ ......................701 14.4 operation of port function ................................................................................................ .... 703 14.4.1 writing to i/o port ..................................................................................................... ..................703 14.4.2 reading from i/o port................................................................................................... ..............703 14.4.3 output status of alter nate function in control mode ....................................................................7 03 14.5 noise eliminator.......................................................................................................... ............ 704 14.5.1 interr upt pi ns .......................................................................................................... ....................704 14.5.2 timer 10, timer 11, timer 3 in put pins .................................................................................. .......705 14.5.3 timer 2 input pins...................................................................................................... .................709 chapter 15 reset function .................................................................................................. ......712 15.1 features .................................................................................................................. ................. 712 15.2 pin functions ............................................................................................................. ............. 712 15.3 initialization ............................................................................................................ ................. 714 16 user?s manual u14492ej4v1ud chapter 16 flash memory ( pd70f3116) .................................................................................720 16.1 features ....................................................................................................................... ............ 720 16.2 writing by flash programmer................................................................................................ 720 16.3 programming environment.................................................................................................... 722 16.4 communication mode............................................................................................................. 722 16.5 pin connection ................................................................................................................. ....... 724 16.5.1 v pp pin ........................................................................................................................... ............ 724 16.5.2 serial in terface pin.................................................................................................... ................. 724 16.5.3 reset pin............................................................................................................... .................. 726 16.5.4 nm i pin ................................................................................................................. ..................... 726 16.5.5 mode0 to mode2 pins ..................................................................................................... ....... 726 16.5.6 port pi ns ............................................................................................................... ..................... 726 16.5.7 other signal pins....................................................................................................... ................. 726 16.5.8 powe r supply ............................................................................................................ ................. 727 16.6 programming method ............................................................................................................. 727 16.6.1 flash memo ry control .................................................................................................... ............ 727 16.6.2 flash memory programmi ng m ode........................................................................................... . 728 16.6.3 selection of communicati on mode......................................................................................... .... 728 16.6.4 communicati on commands .................................................................................................. ..... 729 16.7 flash memory programming by self-programming .... ........................................................ 730 16.7.1 outline of self -programming .................................................................................................... .. 730 16.7.2 self-programmi ng func tion ...................................................................................................... .. 731 16.7.3 outline of self-progr amming inte rface........................................................................................ 73 1 16.7.4 hardware en vironment ........................................................................................................... ... 732 16.7.5 software env ironment........................................................................................................... ..... 734 16.7.6 self-programming function number ........................................................................................... 735 16.7.7 calling pa rameters ............................................................................................................. ....... 736 16.7.8 contents of ra m paramet ers .................................................................................................... 7 37 16.7.9 errors during se lf-programming ................................................................................................. 738 16.7.10 flash info rmation .............................................................................................................. ......... 738 16.7.11 area num ber.................................................................................................................... .......... 739 16.7.12 flash programming mode cont rol register (flpmc ).................................................................. 740 16.7.13 calling device inte rnal proc essing ............................................................................................. 742 16.7.14 erasing flash memory flow ...................................................................................................... .. 745 16.7.15 continuous wr iting flow........................................................................................................ ...... 746 16.7.16 internal ve rify flow........................................................................................................... ........... 747 16.7.17 acquiring flash in formation flow ............................................................................................... .. 748 16.7.18 self-programmi ng libr ary ....................................................................................................... .... 749 16.8 how to distinguish flash memory and mask rom versions .......... ................................... 751 chapter 17 turning on/off power .........................................................................................75 2 chapter 18 electrical specifications ..................................................................................754 18.1 normal operation mode ......................................................................................................... 7 54 18.2 flash memory programming mode ( pd70f3116 only)...................................................... 780 chapter 19 package drawing................................................................................................. ...782 17 user?s manual u14492ej4v1ud chapter 20 recommended soldering conditions............................................................783 appendix a notes ............................................................................................................ .................784 a.1 restriction on conflict between sl d instruction and interrupt requ est ........................... 784 a.1.1 descr iption .............................................................................................................. ...................784 a.1.2 counte rmeasure........................................................................................................... ..............784 appendix b notes on target system design....................................................................785 appendix c register index .................................................................................................. ........786 appendix d instruction set list........................................................................................... ...797 d.1 functions .................................................................................................................. ............... 797 d.2 instruction set (alphabetical or der) ..................................................................................... 80 0 appendix e revision history ................................................................................................ ......806 e.1 major revisions in this edition ............................................................................................ 806 e.2 revision history up to previous edition ................ .............................................................. 809 18 user?s manual u14492ej4v1ud chapter 1 introduction the v850e/ia1 is a product in the v850 series of nec el ectronics corporation single-chip microcontrollers. this chapter provides an over view of the v850e/ia1. 1.1 outline the v850e/ia1 is a 32-bit single-chip microcontroller that r ealizes high-precision inverter control of a motor due to high-speed operation. it uses the v850e1 cpu of the v850 series and has on-chip rom, ram, bus interface, dma controller, a variety of timers including a 3-phase sine wave pwm timer for a motor, various serial interfaces including fcan, and peripheral facilities such as a/d converters. (1) implementation of v850e1 cpu the v850e1 cpu supports a risc instruction set in whic h instruction execution speeds are increased greatly through the use of basic instructi ons that execute one instruction per clock and optimized pipelines. moreover, it supports multiply instru ctions using a 32-bit hardware multip lier, saturated product-sum operation instructions, and bit manipulation inst ructions as optimum instructions for digital servo control applications. object code efficiency is increased in the c compiler by using 2-byte length basic instructions and instructions corresponding to high-level languages, which makes a program compact. furthermore, since interrupt response time including proces sing by the on-chip interrupt controller also is fast, this cpu is suited to the realm of advanced real-time control. (2) external bus interface function as the external bus interface, there is a multiplex bus configuration that is an address bus (24 bits) and data bus (select 8 bits or 16 bits) suitable for com pact system design. sram and rom memories can be connected. in the dma controller, a transfer is started using software and transfers between external memories can be made concurrent with internal cpu operations or data tr ansfers. real-time control such as motor control or communication control also can be realized simultaneously due to high speed, high-performance cpu instruction execution. (3) on-chip flash memory ( pd70f3116) the on-chip flash memory version ( pd70f3116), which has a quickly accessible flash memory on-chip, can shorten system development time since it is possible to rewrite a program with t he v850e/ia1 mounted in an application system. moreover, it can greatly improve maintainability after a system ships. (4) complete middleware, deve lopment environment products the v850e/ia1 can execute jpeg, jbig, mh/mr/mmr and other middleware fast. moreover, since middleware for realizing speech recognition, speech synthesis, and other processing also is provided, multimedia systems can be realized easily by combining with this middleware. a development environment that integrates an optimizing c compiler, debug ger, in-circuit emulator, simulator, and system performance analyzer also is provided. chapter 1 introduction 19 user?s manual u14492ej4v1ud table 1-1 lists the differences between the v850e/ia 1 and v850e/ia2. table 1-2 lists the differences between the v850e/ia1 and v850e/ia2 register setting values. table 1-1. differences between v850e/ia1 and v850e/ia2 item v850e/ia1 v850e/ia2 maximum operating frequency 50 mhz note 40 mhz mask rom pd703116: 256 kb pd703114: 128 kb internal rom flash memory pd70f3116: 256 kb pd70f3114: 128 kb internal ram 10 kb 6 kb timer 00, 01 provided buffer register, compare register, and compare match interrupt added timer 10, 11 provided timer 10: provided, timer 11: not provided timer 20, 21 provided provided timer 3 provided to3 output buffer off function added by intp4 input timer timer 4 provided provided uart0 provided provided uart1 provided provided (pins also used with csi1) uart2 provided not provided csi0 provided provided csi1 provided provided (pins also used with uart1) serial interface fcan provided not provided debug support function nbd provided not provided analog input total of two circuits: 16 ch a/d converter 0: 8 ch a/d converter 1: 8 ch total of two circuits: 14 ch a/d converter 0: 6 ch a/d converter 1: 8 ch a/d converter av dd , av ref pins independent pins alternate-function pins supply voltage v dd3 = 3.3 v 0.3 v v dd5 = 5.0 v 0.5 v v dd = rv dd = 5.0 v 0.5 v internal regulator package 144-pin plastic lqfp 100-pin plastic lqfp 100-pin plastic qfp note the maximum operating frequency of the in-circuit emulator is 40 mhz. a frequency of 50 mhz can be supported by upgrading the in-circuit emulator, so contact an nec el ectronics sales representative or distributor. remark for details, refer to the user?s manual of each product. chapter 1 introduction 20 user?s manual u14492ej4v1ud table 1-2. differences between v850e /ia1 and v850e/ia2 register setting values register name v850e/ia1 note v850e/ia2 system wait control register (vswc) 12h 02h timer 1/timer 2 clock selection register (prm02) 00h or 01h 01h (initial value 00h) notes 1. setting the tesne1 and tesne0 bits of timer 2 count clock/control edge select register 0 (cse0) to 11b (both rising/falling edges) is prohibited when the prm2 bit of the timer 1/timer 2 clock selection register (prm02) is 1b (f clk = f xx /2) 2. set the vswc register to 15h when the prm2 bit of the timer 1/timer 2 clock selection register (prm02) = 0b (f clk = f xx /4). remark for details, refer to the user?s manual of each product. chapter 1 introduction 21 user?s manual u14492ej4v1ud 1.2 features number of instructions 83 minimum instruction execution time 20 ns (@ internal 50 mhz operation) general-purpose registers 32 bits 32 registers instruction set v850e1 cpu signed multiplication (32 bits 32 bits 64 bits): 1 or 2 clocks saturated operation instructions (wit h overflow/underflow detection function) 32-bit shift instruction: 1 clock bit manipulation instructions long/short format load/store instructions signed load instructions memory space 256 mb linear address space (shared by program and data) chip select output function: 8 spaces memory block division function: 2, 4, or 8 mb/block programmable wait function idle state insertion function external bus interface 16-bit data bus (address/data multiplex) 16-/8-bit bus sizing function bus hold function external wait function on-chip memory product name internal rom internal ram pd703116 256 kb (mask rom) 10 kb pd70f3116 256 kb (flash memory) 10 kb interrupts/exceptions external interrupts: 20 (including nmi) internal interrupts: 45 sources exceptions: 1 cause 8 levels of priority definable memory access control sram controller chapter 1 introduction 22 user?s manual u14492ej4v1ud dma controller 4-channel configuration transfer unit: 8 bits/16 bits maximum transfer count: 65,536 (2 16 ) transfer type: 2-cycle transfer transfer modes: single transfer, single-step transfer, block transfer transfer subjects: memory ? memory, memory ? i/o, i/o ? i/o transfer requests: on-c hip peripheral i/o, software next address setting function i/o lines input ports: 8 i/o ports: 75 real-time pulse unit 16-bit timer for 3-phase sine wave pwm inverter control: 2 channels 16-bit up/down counter/timer for 2-phase encoder input: 2 channels general-purpose 16-bit timer/counter: 2 channels general-purpose 16-bit timer/event counter: 1 channel 16-bit interval timer: 1 channel serial interface (sio) asynchronous serial interface (uart): 3 channels clocked serial interface (csi): 2 channels fcan (full controller area network): 1 channel nbd (non break debug) function: 1 channel ( pd70f3116 only) ram monitoring event detection a/d converter 10-bit resolution a/d converter: 8 channels 2 units clock generator multiplication function ( 1, 2.5, 5, 10) using pll clock synthesizer divide-by-2 function using external clock input power-saving function halt, idle, and software stop modes power supply voltage internal unit: 3.3 v, a/d converter: 5 v, external pin: 5 v package 144-pin plastic lqfp (fine pitch) (20 20) cmos technology full static circuits 1.3 applications ? pd703116, 70f3116: consumer equipm ent (inverter air conditioner) industrial equipment (motor co ntrol, general-purpose inverter) ? pd703116(a), 703116(a1), 70f3116(a), 70f3116(a1): auto mobile applications (electrical power steering, electric car control) chapter 1 introduction 23 user?s manual u14492ej4v1ud 1.4 ordering information part no. package quality grade pd703116gj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) standard pd70f3116gj-uen 144-pin plasti c lqfp (fine pitch) (20 20) standard pd703116gj(a)-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) special pd703116gj(a1)-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) special pd70f3116gj(a)-uen 144-pin plas tic lqfp (fine pitch) (20 20) special pd70f3116gj(a1)-uen 144-pin plastic lqfp (fine pitch) (20 20) special remark xxx indicates the rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications. differences between pd703116, 703116(a), 703116(a1), 70f3116, 70f3116(a), and 70f3116(a1) part no. item pd703116 pd703116(a) pd703116(a1) pd70f3116 pd70f3116(a) pd70f3116(a1) quality grade standard grade specia l grade standard grade special grade maximum operating frequency (mhz) 50 note 32 50 note 32 operating ambient temperature (t a ) ? 40 to +85 c ? 40 to +110 c ? 40 to +85 c ? 40 to +110 c note the maximum operating frequency of the in-circuit emulator is 40 mhz. a frequency of 50 mhz can be supported by upgrading the in-circuit emulator, so contact an nec electronics sales representative or distributor. chapter 1 introduction 24 user?s manual u14492ej4v1ud 1.5 pin configuration (top view) ? 144-pin plastic lqfp (fine pitch) (20 20) pd703116gj- -uen, 703116gj(a)- -uen, 703116gj(a1)- -uen pd70f3116gj-uen, 70f3116gj( a)-uen, 70f3116gj(a1)-uen ani07 av dd av ss av ref1 ani10 ani11 ani12 ani13 ani14 ani15 ani16 ani17 trig _ dbg ad3 _ dbg ad2 _ dbg ad1 _ dbg ad0 _ dbg sync clk _ dbg reset cv dd cv ss x1 x2 cksel mode0 mode1 mode2 si0/p40 so0/p41 sck0/p42 si1/p43 so1/p44 sck1/p45 crxd/p46 ctxd/p47 tiud11/to11/p13 tclr10/intp101/p12 tcud10/intp100/p11 tiud10/to10/p10 pcm4 hldrq/pcm3 hldak/pcm2 clkout/pcm1 wait/pcm0 pct7 astb/pct6 pct5 rd/pct4 pct3 pct2 uwr/pct1 lwr/pct0 v dd5 v ss5 cs7/pcs7 cs6/pcs6 cs5/pcs5 cs4/pcs4 cs3/pcs3 cs2/pcs2 cs1/pcs1 cs0/pcs0 a23/pdh7 a22/pdh6 a21/pdh5 a20/pdh4 a19/pdh3 a18/pdh2 a17/pdh1 a16/pdh0 rxd0/p30 txd0/p31 rxd1/p32 txd1/p33 asck1/p34 rxd2/p35 txd2/p36 asck2/p37 ti2/intp20/p20 to21/intp21/p21 to22/intp22/p22 to23/intp23/p23 to24/intp24/p24 tclr2/intp25/p25 ti3/intp30/tclr3/p26 to3/intp31/p27 v dd3 v ss3 v ss5 v dd5 ad0/pdl0 ad1/pdl1 ad2/pdl2 ad3/pdl3 ad4/pdl4 ad5/pdl5 ad6/pdl6 ad7/pdl7 ad8/pdl8 ad9/pdl9 ad10/pdl10 ad11/pdl11 ad12/pdl12 ad13/pdl13 ad14/pdl14 ad15/pdl15 ani06 ani05 ani04 ani03 ani02 ani01 ani00 av ref0 av ss av dd to015 to014 to013 to012 to011 to010 v dd3 v ss3 v ss5 v dd5 to005 to004 to003 to002 to001 to000 intp6/p07 intp5/p06 intp4/p05 adtrg1/intp3/p04 adtrg0/intp2/p03 eso1/intp1/p02 eso0/intp0/p01 nmi/p00 note 3 tclr11/intp111/p15 tcud11/intp110/p14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 note 1 note 2 notes 1. on-chip in pd70f3116 only. as follows in pd703116. trig_dbg: ic1, ad0_dbg to ad3_ dbg: ic2, sync: ic3, clk_dbg: ic4 2. pd703116: ic5 pd70f3116: v pp 3. the nmi/p00 pin always functions as the nmi pin. the nmi pin level can be read by reading the p0.p00 bit. cautions 1. when using the pd70f3116 in normal mode, connect the v pp pin to v ss5 . 2. when using the pd703116, the processing when the ic1 to ic5 pins are unused is as follows. ic1 to ic4 pins: leave open. ic5 pin: independently connect to v ss5 via a resistor. chapter 1 introduction 25 user?s manual u14492ej4v1ud pin identification a16 to a23: ad0 to ad15: ad0_dbg to ad3_dbg: adtrg0, adtrg1: ani00 to ani07, ani10 to ani17: asck1, asck2: astb: av dd : av ref0 , av ref1 : av ss : cksel: clk_dbg: clkout: crxd: cs0 to cs7: ctxd: cv dd : cv ss : eso0, eso1: hldak: hldrq: ic1 to ic5: intp0 to intp6, intp100, intp101, intp110, intp111, intp20 to intp25, intp30, intp31: lwr: mode0 to mode2: nmi: p00 to p07: p10 to p15: address bus address/data bus debug address/data bus a/d trigger input analog input asynchronous serial clock address strobe analog power supply analog reference voltage analog ground clock generator operating mode select debug clock clock output receive data for controller area network chip select transmit data for controller area network clock generator power supply clock generator ground emergency shut off hold acknowledge hold request internally connected external interrupt input lower write strobe mode non-maskable interrupt request port 0 port 1 p20 to p27: p30 to p37: p40 to p47: pcm0 to pcm4: pcs0 to pcs7: pct0 to pct7: pdh0 to pdh7: pdl0 to pdl15: rd: reset: rxd0 to rxd2: sck0, sck1: si0, si1: so0, so1: sync: tclr10, tclr11, tclr2, tclr3: tcud10, tcud11: ti2, ti3: tiud10, tiud11: to000 to to005, to010 to to015, to10, to11, to21 to to24, to3: trig_dbg: txd0 to txd2: uwr: v dd3 , v dd5 : v pp : v ss3 , v ss5 : wait: x1, x2: port 2 port 3 port 4 port cm port cs port ct port dh port dl read strobe reset receive data serial clock serial input serial output debug synchronization timer clear timer control pulse input timer input timer count pulse input timer output debug trigger transmit data upper write strobe power supply programming power supply ground wait crystal chapter 1 introduction 26 user?s manual u14492ej4v1ud 1.6 configuration of function block 1.6.1 internal block diagram uart0 brg0 uart1 brg1 uart2 brg2 csi0 csi1 fcan nbd note 3 rpu tm0: 2 ch tm1: 2 ch tm2: 2 ch tm3: 1 ch tm4: 1 ch intc sio nmi intp0 to intp6 intp20 to intp25 intp30, intp31 intp100, intp101 intp110, intp111 eso0, eso1 to000 to to005, to010 to to015 tiud10/to10, tcud10, tclr10 tiud11/to11, tcud11, tclr11 ti2, tclr2, to21 to to24 ti3/tclr3, to3 txd0 rxd0 txd1 rxd1 asck1 txd2 rxd2 asck2 so0 si0 sck0 so1 si1 sck1 ctxd crxd clk_dbg sync ad0_dbg to ad3_dbg trig_dbg note 1 sramc romc dmac pc 32-bit barrel shifter multiplier 32 32 64 cpu rom ram bcu alu memc hldrq hldak cs0 to cs7 cksel clkout x1 x2 cv dd cv ss pdl0 to pdl15 pdh0 to pdh7 pcs0 to pcs7 pct0 to pct7 pcm0 to pcm4 p40 to p47 p30 to p37 p20 to p27 p10 to p15 p00 to p07 adtrg0 ani00 to ani07 av ss av ref0 av dd adtrg1 ani10 to ani17 av ss av ref1 av dd mode0 to mode2 reset v dd5 v ss5 v dd3 v ss3 v pp note 4 uwr lwr wait a16 to a23 ad0 to ad15 system register general- purpose registers 32bits 32 ports adc0 adc1 cg system controller brg3 10 kb rd astb note 2 instruction queue notes 1. pd703116: 256 kb (mask rom) pd70f3116: 256 kb (flash memory) 2. on-chip in pd70f3116 only. as follows pd703116. trig_dbg: ic1, ad0_dbg to ad3_ dbg: ic2, sync: ic3, clk_dbg: ic4 3. pd70f3116 only. 4. pd70f3116 only. in the pd703116, the v pp pin is assigned as the ic5 pin. chapter 1 introduction 27 user?s manual u14492ej4v1ud 1.6.2 internal units (1) cpu the cpu uses 5-stage pipeline control to execute address calculation, ar ithmetic and logica l operation, data transfer, and most other instruction processing in one clock. a multiplier (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits), barrel shifter (32-bit), and other dedicated hardware are on-chip to accele rate complex instruction processing. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on a physical addr ess obtained from the cpu. if there is no bus cycle start request from the cp u when fetching an instruction from an external memory area, the bcu generates a prefetch addres s and prefetches the instruction code. t he prefetched instruction code is fetched into the internal instruction queue of the cpu. (3) memory controller (memc) the memc controls sram, rom, and various i/o for external memory expansion. (4) dma controller (dmac) the dma transfers data between memory and i/o in place of the cpu. the address mode is two-cycle transfer. the three bus modes are single transfer, single-step transfer, and block transfer. (5) rom there is on-chip flash memory (256 kb) in the pd70f3116, and mask rom (256 kb) in the pd703116. on an instruction fetch, the rom can be accessed by the cpu in one clock. when single-chip mode 0 or flash memory programmi ng mode is set, rom is mapped starting from address 00000000h. when single-chip mode 1 is set, it is mapped starting from address 00100000h. rom cannot be accessed if romless mode 0 or 1 is set. (6) ram ram is mapped starting from address ffffc000h. it can be accessed by the cpu in one clo ck on an instruction fetch or data access. (7) interrupt controller (intc) the intc services hardware interrupt requests from on-chip peripheral i/o and external sources (nmi, intp0 to intp6, intp20 to intp25, intp30, intp31, intp100, intp101, intp110, intp111). for these interrupt requests, eight levels of interrupt priority can be de fined and multiprocessing controls against the interrupt sources can be performed. (8) clock generator (cg) the cg provides a frequency t hat is 1, 2.5, 5, or 10 times (using the on-chip pll) or 1/2 times (not using the on-chip pll) the input clock (f x ) as the internal system clock (f xx ). as the input clock, connect an external resonator to pins x1 and x2 (only when using the on-chip pll synthesizer) or input an external clock from the x1 pin. chapter 1 introduction 28 user?s manual u14492ej4v1ud (9) real-time pulse unit (rpu) the rpu has a 2-channel 16-bit timer (tm0) for 3-phase sine wave pwm inverter control, a 2-channel 16-bit up/down counter (tm1) that can be used for 2-phase encoder input or as a general-purpose timer, a 2- channel 16-bit general-purpose timer unit (tm2), a 1- channel 16-bit timer/event counter (tm3), and a 1- channel 16-bit interval timer (tm4) on-chip. the rpu can measure the pulse interval or frequency and can output a programmable pulse. (10) serial interface (sio) a 3-channel asynchronous serial interface (uart), 2-ch annel clocked serial interface (csi), and 1-channel fcan are provided as serial interfaces. the uart performs data transfer using pins txdn and rxdn (n = 0 to 2). the csi performs data transfer using pi ns som, sim, and sckm (m = 0, 1). fcan performs data transfer using pins ctxd and crxd. (11) nbd function there is a 1-channel nbd on-chip as a debugging interface ( pd70f3116 only). (12) a/d converter (adc) two units of a high-speed, high-resolution 10-bit a/d converter having eight analog input pins are implemented. the adc converts using a successive approximation method. (13) ports as shown in the table below, ports function as general-purpose ports and as control pins. port i/o control functions port 0 8-bit input nmi input real-time pulse unit output stop signal input external interrupt input a/d converter external trigger input port 1 6-bit i/o real-time pulse unit i/o external interrupt input port 2 8-bit i/o real-time pulse unit i/o external interrupt input port 3 8-bit i/o serial interface i/o (uart0 to uart2) port 4 8-bit i/o serial interface i/o (csi0, csi1, fcan) port dh 8-bit i/o external address bus (a16 to a23) port dl 16-bit i/o external address/data bus (ad0 to ad15) port cs 8-bit i/o external bus interface control signal output port ct 8-bit i/o external bus interface control signal output port cm 5-bit i/o wait insertion signal input internal system clock output external bus interface control signal i/o chapter 1 introduction 29 user?s manual u14492ej4v1ud 1.7 differences between products item pd703116 pd703116(a) pd703116(a1) pd70f3116 pd70f3116(a) pd70f3116(a1) mask rom flash memory internal rom 256 kb internal ram 10 kb nbd (non break debug) function not provided (ic1 to ic4) provided (trig_dbg, ad0_dbg to ad3_dbg, sync, clk_dbg) flash memory programming pin not provided (ic5) provided (v pp ) flash memory programming mode not provided provided (mode0 = h/l, mode1 = h, mode2 = l, v pp = 7.8 v) quality grade standard grade specia l grade standard grade special grade electrical specifications the maximum operating frequency, operating ambient te mperature, and current consumption differ (refer to the data sheet of each product). other the noise immunity and noise r adiation differ because the circuit scale and mask layout are different. 30 user?s manual u14492ej4v1ud chapter 2 pin functions the names and functions of the v850e /ia1 pins are shown below. these pins can be divided by function into port pins and non-port pins. 2.1 list of pin functions (1) port pins (1/3) pin name i/o function alternate function p00 nmi p01 eso0/intp0 p02 eso1/intp1 p03 adtrg0/intp2 p04 adtrg1/intp3 p05 intp4 p06 intp5 p07 i port 0 8-bit input-only port p00 is also used for indicating the nm i pin status. the nmi pin level can be read by reading the p0.p00 bit. p 00 functions as an nmi input when a valid edge is input. intp6 p10 tiud10/to10 p11 tcud10/intp100 p12 tclr10/intp101 p13 tiud11/to11 p14 tcud11/intp110 p15 i/o port 1 6-bit i/o port input/output can be specified in 1-bit units. tclr11/intp111 p20 ti2/intp20 p21 to21/intp21 p22 to22/intp22 p23 to23/intp23 p24 to24/intp24 p25 tclr2/intp25 p26 ti3/tclr3/intp30 p27 i/o port 2 8-bit i/o port input/output can be specified in 1-bit units. to3/intp31 p30 rxd0 p31 txd0 p32 rxd1 p33 txd1 p34 asck1 p35 rxd2 p36 txd2 p37 i/o port 3 8-bit i/o port input/output can be specified in 1-bit units. asck2 chapter 2 pin functions 31 user?s manual u14492ej4v1ud (2/3) pin name i/o function alternate function p40 si0 p41 so0 p42 sck0 p43 si1 p44 so1 p45 sck1 p46 crxd p47 i/o port 4 8-bit i/o port input/output can be specified in 1-bit units. ctxd pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldrq pcm4 i/o port cm 5-bit i/o port input/output can be specified in 1-bit units. ? pct0 lwr pct1 uwr pct2 ? pct3 ? pct4 rd pct5 ? pct6 astb pct7 i/o port ct 8-bit i/o port input/output can be specified in 1-bit units. ? pcs0 cs0 pcs1 cs1 pcs2 cs2 pcs3 cs3 pcs4 cs4 pcs5 cs5 pcs6 cs6 pcs7 i/o port cs 8-bit i/o port input/output can be specified in 1-bit units. cs7 pdh0 a16 pdh1 a17 pdh2 a18 pdh3 a19 pdh4 a20 pdh5 a21 pdh6 a22 pdh7 i/o port dh 8-bit i/o port input/output can be specified in 1-bit units. a23 chapter 2 pin functions 32 user?s manual u14492ej4v1ud (3/3) pin name i/o function alternate function pdl0 ad0 pdl1 ad1 pdl2 ad2 pdl3 ad3 pdl4 ad4 pdl5 ad5 pdl6 ad6 pdl7 ad7 pdl8 ad8 pdl9 ad9 pdl10 ad10 pdl11 ad11 pdl12 ad12 pdl13 ad13 pdl14 ad14 pdl15 i/o port dl 16-bit i/o port input/output can be specified in 1-bit units. ad15 chapter 2 pin functions 33 user?s manual u14492ej4v1ud (2) non-port pins (1/3) pin name i/o function alternate function to000 ? to001 ? to002 ? to003 ? to004 ? to005 o timer 00 pulse signal output ? to010 ? to011 ? to012 ? to013 ? to014 ? to015 o timer 01 pulse signal output ? to10 p10/tiud10 to11 o timer 10 or 11 pulse signal output p13/tiud11 to21 p21/intp21 to22 p22/intp22 to23 p23/intp23 to24 o timer 2 pulse signal output p24/intp24 to3 o timer 3 pulse signal output p27/intp31 eso0 p01/intp0 eso1 i timer 00 or 01 output stop signal input p02/intp1 tiud10 p10/to10 tiud11 i external count clock input to up/down counter (timer 10 or 11) p13/to11 tcud10 p11/intp100 tcud11 i count operation switching signal to up/down counter (timer 10 or 11) p14/intp110 tclr10 p12/intp101 tclr11 i clear signal input to up/down counter (timer 10 or 11) p15/intp111 ti2 p20/intp20 ti3 i timer 2 or 3 external count clock input p26/intp30/tclr3 tclr2 p25/intp25 tclr3 i timer 2 or 3 clear signal input p26/intp31/ti3 intp0 p01/eso0 intp1 p02/eso1 intp2 p03/adtrg0 intp3 p04/adtrg1 intp4 p05 intp5 p06 intp6 i external maskable interrupt request input p07 chapter 2 pin functions 34 user?s manual u14492ej4v1ud (2/3) pin name i/o function alternate function intp100 p11/tcud10 intp101 i external maskable interrupt request input and timer 10 external capture trigger input p12/tclr10 intp110 p14/tcud11 intp111 i external maskable interrupt request input and timer 11 external capture trigger input p15/tclr11 intp20 p20/ti2 intp21 p21/to21 intp22 p22/to22 intp23 p23/to23 intp24 p24/to24 intp25 i external maskable interrupt request input and timer 2 external capture trigger input p25/tclr2 intp30 p26/ti3/tclr3 intp31 i external maskable interrupt request input and timer 3 external capture trigger input p27/to3 so0 p41 so1 o serial transmit data output (3-wire) of csi0 and csi1 p44 si0 p40 si1 i serial receive data input (3-wire) of csi0 and csi1 p43 sck0 p42 sck1 i/o serial clock i/o (3-w ire) of csi0 and csi1 p45 txd0 p31 txd1 p33 txd2 o serial transmit data output of uart0 to uart2 p36 rxd0 p30 rxd1 p32 rxd2 i serial receive data input of uart0 to uart2 p35 asck1 p34 asck2 i/o serial clock i/o of uart1 and uart2 p37 ctxd o fcan serial transmit data output p47 crxd i fcan serial receive data input p46 ani00 to ani07 ? ani10 to ani17 i analog input to a/d converter ? adtrg0 p03/intp2 adtrg1 i external trigger input to a/d converter p04/intp3 nmi i non-maskable interrupt request input p00 mode0 ? mode1 ? mode2 i specifies v850e/ia1 operation mode ? v pp note 1 ? power application for flash memory write ? ic1 to ic5 note 2 ? internal connection pins ? notes 1. pd70f3116 only 2. pd703116 only chapter 2 pin functions 35 user?s manual u14492ej4v1ud (3/3) pin name i/o function alternate function wait i control signal input to insert wait in bus cycle pcm0 hldak o bus hold acknowledge output pcm2 hldrq i bus hold request input pcm3 lwr o external data lower byte write strobe signal output pct0 uwr o external data upper byte write strobe signal output pct1 rd o external data bus read strobe signal output pct4 astb o external data bus address strobe signal output pct6 cs0 pcs0 cs1 pcs1 cs2 pcs2 cs3 pcs3 cs4 pcs4 cs5 pcs5 cs6 pcs6 cs7 o chip select signal output pcs7 ad0 to ad15 i/o 16-bit address/data bus for external memory pdl0 to pdl15 a16 to a23 o upper 8-bit address bus fo r external memory pdh0 to pdh7 reset i system reset input ? x1 i ? x2 ? crystal resonator connection pin for system clock generation input to x1 pin when providing clocks from outside. ? clkout o system clock output pcm1 cksel i input specifying clock generator operation mode ? av ref0 i reference voltage input for a/d converter 0 ? av ref1 i reference voltage input for a/d converter 1 ? av dd ? positive power supply for a/d converter ? av ss ? ground potential for a/d converter ? cv dd ? positive power supply for dedicated clock generator ? cv ss ? ground potential for dedicated clock generator ? v dd5 ? positive power supply for peripheral interface ? v ss5 ? ground potential for peripheral interface ? v dd3 ? 3.3 v positive power supply pin for internal cpu ? v ss3 ? ground potential for internal cpu ? clk_dbg note i debugging interface clock input (3.3 v interface) ? sync note i debugging interface command synchronization input (3.3 v interface) ? ad0_dbg note ? ad1_dbg note ? ad2_dbg note ? ad3_dbg note i/o command interface input for debugging (3.3 v interface) ? trig_dbg note o address match trigger signal out put for debugging (3.3 v interface) ? note pd70f3116 only chapter 2 pin functions 36 user?s manual u14492ej4v1ud 2.2 pin status the following table shows the status of each pin after a reset, in power-saving mode (software stop mode, idle, halt), on a dma transfer, and on a bus hold. operating status pin reset (single-chip mode 0) reset (single-chip mode 1, romless mode 0 or 1) idle mode/ software stop mode halt mode/ during dma transfer bus hold a16 to a23 (pdh0 to pdh7) hi-z hi-z hi-z operating hi-z ad0 to ad15 (pdl0 to pdl15) hi-z hi-z hi-z operating hi-z cs0 to cs7 (pcs0 to pcs7) hi -z hi-z h operating hi-z lwr, uwr (pct0, pct1) hi-z hi-z h operating hi-z rd (pct4) hi-z hi-z h operating hi-z astb (pct6) hi-z hi-z h operating hi-z wait (pcm0) hi-z hi-z ? operating ? clkout (pcm1) hi-z operat ing l operating operating hldak (pcm2) hi-z hi-z h operating l hldrq (pcm3) hi-z hi-z ? operating operating caution when controlling the external bus using an as ic or the like in standby mode, provide a separate controller. remark hi-z: high impedance h: high-level output l: low-level output ? : no input sampling chapter 2 pin functions 37 user?s manual u14492ej4v1ud 2.3 description of pin functions (1) p00 to p07 (port 0) ? input port 0 is an 8-bit input-only port in which all pins are fixed for input. besides functioning as an input port, in control mode, p00 to p07 operate as nmi input, real-time pulse unit (rpu) output stop signal input, external interrupt request input, and a/d converter (adc) external trigger input. normally, if function pins also serve as ports, one mode or the other is selected using a port mode control register. however, there is no such register for p00 to p07. therefore, the input port cannot be switched with the nmi input pin, rpu output stop signal input pin, external interrupt request input pin, and a/d converter (adc) external trigger input pin. read the status of each pin by reading the port. (a) port mode p00 to p07 are input-only. (b) control mode p00 to p07 also serve as nmi, eso0, eso1, adtr g0, adtrg1, and intp0 to intp6 pins, but they cannot be switched. (i) nmi (non-maskable inte rrupt request) ? input this is non-maskable interrupt request input. (ii) eso0, eso1 (emergency shut off) ? input these pins input timer 00 and timer 01 output stop signals. (iii) intp0 to intp6 (external interrupt input) ? input these are external interrupt request input pins. (iv) adtrg0, adtrg1 (a/d trigger input) ? input these are a/d converter external trigger input pins. (2) p10 to p15 (port 1) ? i/o port 1 is a 6-bit i/o port in which input or output can be set in 1-bit units. besides functioning as an i/o port, in control mode, p 10 to p15 operate as rpu i/o and external interrupt request input. an operation mode of port or contro l mode can be selected for each bi t and specified by the port 1 mode control register (pmc1). (a) port mode p10 to p15 can be set to input or output in 1- bit units using the port 1 mode register (pm1). (b) control mode p10 to p15 can be set to port or control mode in 1-bit units using pmc1. (i) to10, to11 (timer output) ? output these pins output timer 10 and timer 11 pulse signals. (ii) tiud10, tiud11 (timer count pulse input) ? input these are external count clock input pins to the up/down counter (timer 10, timer 11). chapter 2 pin functions 38 user?s manual u14492ej4v1ud (iii) tcud10, tcud11 (timer control pulse input) ? input these pins input count operation switching signal s to the up/down counter (timer 10, timer 11). (iv) tclr10, tclr11 (timer clear) ? input these are clear signal input pins to the up/down counter (timer 10, timer 11). (v) intp100, intp101 (external interrupt input) ? input these are external interrupt request input pins and timer 10 external capture trigger input pins. (vi) intp110, intp111 (external interrupt input) ? input these are external interrupt request input pins and timer 11 external capture trigger input pins. (3) p20 to p27 (port 2) ? i/o port 2 is an 8-bit i/o port in which input or output can be set in 1-bit units. besides functioning as an i/o port, in control mode, p 20 to p27 operate as rpu i/o and external interrupt request input. an operation mode of port or contro l mode can be selected for each bi t and specified by the port 2 mode control register (pmc2). (a) port mode p20 to p27 can be set to input or output in 1- bit units using the port 2 mode register (pm2). (b) control mode p20 to p27 can be set to port or control mode in 1-bit units using pmc2. (i) to21 to to24 (timer output) ? output these pins output a timer 2 pulse signal. (ii) to3 (timer output) ? output this pin outputs a timer 3 pulse signal. (iii) ti2, ti3 (timer input) ? input these are timer 2 and timer 3 external count clock input pins. (iv) tclr2, tclr3 (timer clear) ? input these are timer 2 and timer 3 clear signal input pins. (v) intp20 to intp25 (external interrupt input) ? input these are external interrupt request input pins and timer 2 external capture trigger input pins. (vi) intp30, intp31 (external interrupt input) ? input these are external interrupt request input pins and timer 3 external capture trigger input pins. chapter 2 pin functions 39 user?s manual u14492ej4v1ud (4) p30 to p37 (port 3) ? i/o port 3 is an 8-bit i/o that can be set to input or output in 1-bit units. besides functioning as an i/o port, in control mode, p30 to p37 operate as serial interface (uart0 to uart2) i/o. an operation mode of port or contro l mode can be selected for each bi t and specified by the port 3 mode control register (pmc3). (a) port mode p30 to p37 can be set to input or output in 1- bit units using the port 3 mode register (pm3). (b) control mode p30 to p37 can be set to port or control mode in 1-bit units using pmc3. (i) txd0 to txd2 (tra nsmit data) ? output these pins output serial trans mit data of uart0 to uart2. (ii) rxd0 to rxd2 (receive data) ? input these pins input serial receive data of uart0 to uart2. (iii) asck1, asck2 (asynchronous serial clock) ? i/o these are uart1 and uart2 serial clock i/o pins. (5) p40 to p47 (port 4) ? i/o port 4 is an 8-bit i/o port in which input or output can be set in 1-bit units. besides functioning as an i/o port, in control mode, p40 to p47 operate as serial interface (csi0, csi1, fcan) i/o. an operation mode of port or contro l mode can be selected for each bi t and specified by the port 4 mode control register (pmc4). (a) port mode p40 to p47 can be set to input or output in 1- bit units using the port 4 mode register (pm4). (b) control mode p40 to p47 can be set to port or control mode in 1-bit units using pmc4. (i) so0, so1 (serial output) ? output these pins output csi0 and cs i1 serial transmit data. (ii) si0, si1 (serial input) ? input these pins input csi0 and csi1 serial receive data. (iii) sck0, sck1 (serial clock) ? i/o these are csi0 and csi1 serial clock i/o pins. (iv) ctxd (transmit data for c ontroller area network) ? output this pin outputs fcan serial transmit data. chapter 2 pin functions 40 user?s manual u14492ej4v1ud (v) crxd (receive data for co ntroller area network) ? input this pin inputs fcan serial receive data. (6) pcm0 to pcm4 (port cm) ? i/o port cm is a 5-bit i/o port in which input or output can be set in 1-bit units. besides functioning as a port, in control mode, pcm0 to pcm4 operate as wait insertion signal input, internal system clock output, and bus hold control signal output. an operation mode of port or control mode can be se lected for each bit and specified by the port cm mode control register (pmccm). (a) port mode pcm0 to pcm4 can be set to input or output in 1- bit units using the port cm mode register (pmcm). (b) control mode pcm0 to pcm4 can be set to port or control mode in 1-bit units using pmccm. (i) wait (wait) ? input this control signal input pin, which inserts a data wait in a bus cycle, can input asynchronously with respect to a clkout signal. sampling is done at the falling edge of a clkout signal in a bus cycle in a t2 or tw state. if the setup or hold time is not secured in the sampling timing, wait insertion may not be performed. (ii) clkout (clock output) ? output this is an internal system clock output pin. in single-chip mode 1 and romless mode 0 or 1, output is not performed by the clkout pin because it is in port mode during the reset period. to perform clkout output, set this pin to control mode usi ng the port cm mode control register (pmccm). (iii) hldak (hold acknowledge) ? output this is an acknowledge signal output pin that s hows that the v850e/ia1 received a bus hold request and that the external address/data bus and various strobe pins entered in a high-impedance state. while this signal is active, the external add ress/data bus and various strobe pins become high- impedance and transfer the bus mastership to the external bus master. (iv) hldrq (hold request) ? input this is the input pin by which an external devic e requests that the v850e/ia1 release the external address/data bus and various strobe pins. the signal via this pin can be input asynchronously with respect to the clkout signal. when this pin becomes active, the v850e/ia1 makes the external address/data bus and various strobe pins high-impe dance after the executing bus cycle terminates (or immediately if there is none) and releases the bus by making the hldak signal active. to reliably set bus hold status, keep the hldrq signal active until a hldak signal is output. chapter 2 pin functions 41 user?s manual u14492ej4v1ud (7) pct0 to pct7 (port ct) ? i/o port ct is an 8-bit i/o port in which inpu t or output can be set in 1-bit units. besides functioning as a port, in control mode, it oper ates as control signal output for when memory is expanded externally. an operation mode of port or control mode can be se lected for each bit and specified by the port ct mode control register (pmcct). (a) port mode pct0 to pct7 can be set to input or output in 1-bit units using the port ct mode register (pmct). (b) control mode pct0 to pct7 can be set to port or control mode in 1-bit units using pmcct. (i) lwr (lower byte write strobe) ? output this is a strobe signal that s hows that the exec uting bus cycle is a write cycle for sram, external rom, or an external peripheral i/o area. in the data bus, the lower byte is in effect. if the bus cycle is a lower memory write, it becomes active at the falling edge of a t1 state clkout signal and becomes i nactive at the falling edge of a t2 state clkout signal. (ii) uwr (upper byte write strobe) ? output this is a strobe signal that s hows that the exec uting bus cycle is a write cycle for sram, external rom, or an external peripheral i/o area. in the data bus, the upper byte is in effect. if the bus cycle is an upper memory write, it becomes active at the falling edge of a t1 state clkout signal and becomes i nactive at the falling edge of a t2 state clkout signal. (iii) rd (read strobe) ? output this is a strobe signal that s hows that the exec uting bus cycle is a read cycle for sram, external rom, or external peripheral i/o. it is inactive in an idle state (ti). (iv) astb (address strobe) ? output this is the external address bus latch strobe signal output pin. output becomes low level in synchronous with the falling edge of the clock in a t1 state bus cycle, and high level in synchronous with the falli ng edge of the clock in a t3 state. (8) pcs0 to pcs7 (port cs) ? i/o port cs is an 8-bit i/o port in which inpu t or output can be set in 1-bit units. besides functioning as a port, in control mode, these oper ate as chip select signal output for when memory is expanded externally. an operation mode of port or control can be selected for each bit and specified by the port cs mode control register (pmccs). (a) port mode pcs0 to pcs7 can be set to input or output in 1- bit units using the port cs mode register (pmcs). chapter 2 pin functions 42 user?s manual u14492ej4v1ud (b) control mode pcs0 to pcs7 can be set to port or control mode in 1-bit units using pmccs. (i) cs0 to cs7 (chip select) ? output this is the chip select signal for external sram, external rom, or external peripheral i/o. the signal csn is assigned to memory block n (n = 0 to 7). this is active for the period du ring which a bus cycle that accesse s the correspondi ng memory block is activated. it is inactive in an idle state (ti). (9) pdh0 to pdh7 (port dh) ? i/o port dh is an 8-bit i/o port in which inpu t or output can be set in 1-bit units. besides functioning as a port, in control mode (ext ernal expansion mode), these operate as the address bus (a16 to a23) for when memory is expanded externally. an operation mode of port or control mode can be se lected for each bit and specified by the port dh mode control register (pmcdh). (a) port mode pdh0 to pdh7 can be set to input or output in 1-bit units using the port dh mode register (pmdh). (b) control mode pdh0 to pdh7 can be used as a16 to a23 by using pmcdh. (i) a16 to a23 (address) ? output this pin outputs the upper 8-bit address of the 24- bit address in the address bus on an external access. (10) pdl0 to pdl7 (port dl) ? i/o port dl is a 16-bit i/o port in which in put or output can be set in 1-bit units. besides functioning as a port, in control mode (exter nal expansion mode), these operate as the address/data bus (ad0 to ad15) for when memory is expanded externally. an operation mode of port or control mode can be sele cted for each bit and specified by the port dl mode control register (pmcdl). (a) port mode pdl0 to pdl15 can be set to input or output in 1-bi t units using the port dl mode register (pmdl). (b) control mode pdl0 to pdl15 can be used as ad0 to ad15 by using pmcdl. (i) ad0 to ad15 (address/data bus) ? i/o this is a multiplexed bus for an address or data on an external access. when used for an address (t1 state) they are 24-bit addre ss output pins a0 to a15, and when used for data (t2, tw, t3) they are 16-bit data i/o bus pins. (11) to000 to to005 (timer output) ? output these pins output the pulse signal of timer 00. chapter 2 pin functions 43 user?s manual u14492ej4v1ud (12) to010 to to015 (timer output) ? output these pins output the pulse signal of timer 01. (13) ani00 to ani07, ani10 to ani17 (analog input) ? input these are analog input pins to the a/d converter. (14) cksel (clock generator op erating mode select) ? input this is the input pin that specifies the operation mode of the clock generator. fix it so that the input level does not change during operation. (15) mode0 to mode2 (mode) ? input these are the input pins that specif y the operation mode. operation mo des are broadly divided into normal operation modes and flash memory programming mode. the normal operation modes are single-chip modes 0 and 1 and romless modes 0 and 1 (see 3.3 operation modes for details). the operation mode is determined by sampling the status of eac h of pins mode0 to mode2 on a reset. fix these so that the input level does not change during operation. (a) pd703116 mode2 mode1 mode0 operation mode l l l romless mode 0 l l h romless mode 1 l h l single-chip mode 0 l h h normal operation mode single-chip mode 1 other than above setting prohibited (b) pd70f3116 v pp mode2 mode1 mode0 operation mode 0 v l l l romless mode 0 0 v l l h romless mode 1 0 v l h l single-chip mode 0 0 v l h h normal operation mode single-chip mode 1 7.8 v l h flash memory programming mode other than above setting prohibited remark l: low-level input h: high-level input : don?t care (16) reset (reset) ? input reset input is asynchronous input. when a signal having a certain low level width is input in asynchronous with the operation clock, a system reset that takes precedence over all operations occurs. besides a normal initialize or start, this signal is also used to release a standby mode (halt, idle, software stop). chapter 2 pin functions 44 user?s manual u14492ej4v1ud (17) x1, x2 (crystal) these pins connect a resonato r for system clock generation. they also can input external clocks. for external cl ock input, connect to the x1 pin and leave the x2 pin open. (18) cv dd (power supply for clock generator) this is the positive power supply pin for the clock generator. (19) cv ss (ground for clock generator) this is the ground pin for the clock generator. (20) v dd5 (power supply) this is the positive power supply pin for the peripheral interface. (21) v ss5 (ground) this is the ground pin for the peripheral interface. (22) v dd3 (power supply) this is the positive power supply pin for the internal cpu. (23) v ss3 (ground) this is the ground pin for the internal cpu. (24) clk_dbg (debug clock) ? input this is the clock input pin for the debug interface (3.3 v interface). (25) sync (debug synchronization) ? input this is the command synchronization input pin for debugging (3.3 v interface). (26) ad0_dbg to ad3_dbg (d ebug address/data bus) ? i/o these are command interface pins for debugging (3.3 v interface). (27) trig_dbg (debug trigger) ? output this is the address match trigger signal ou tput pin for debugging (3.3 v interface). (28) av dd (analog power supply) this is the analog positive power su pply pin for the a/d converter. (29) av ss (analog ground) this is the ground pin for the a/d converter. (30) av ref0 , av ref1 (analog reference voltage) ? input these are the reference voltage supp ly pins for the a/d converter. chapter 2 pin functions 45 user?s manual u14492ej4v1ud 2.4 types of pin i/o circuit and connection of unused pins connection of a 1 to 10 k ? resistor is recommended when connecting to v dd5 , v ss5 , cv dd , cv ss , or av ss via a resistor. (1/2) pin i/o circuit type recommended connection p00/nmi p01/eso0/intp0 p02/eso1/intp1 p03/adtrg0/intp2 p04/adtrg1/intp3 p05/intp4 to p07/intp6 2 connect directly to v ss5 . p10/tiud10/to10 p11/tcud10/intp100 p12/tclr10/intp101 p13/tiud11/to11 p14/tcud11/intp110 p15/tclr11/intp111 p20/ti2/intp20 p21/to21/intp21 to p24/to24/intp24 p25/tclr2/intp25 p26/ti3/tclr3/intp30 p27/to3/intp31 p30/rxd0 5-ac p31/txd0 5 p32/rxd1 5-ac p33/txd1 5 p34/asck1 p35/rxd2 5-ac p36/txd2 5 p37/asck2 p40/si0 5-ac p41/so0 5 p42/sck0 p43/si1 5-ac p44/so1 5 p45/sck1 p46/crxd 5-ac p47/ctxd pcm0/wait pcm1/clkout pcm2/hldak 5 input status: independently connect to v dd5 or v ss5 via a resistor. output status: leave open. chapter 2 pin functions 46 user?s manual u14492ej4v1ud (2/2) pin i/o circuit type recommended connection pcm3/hldrq pcm4 pct0/lwr pct1/uwr pct2 pct3 pct4/rd pct5 pct6/astb pct7 pcs0/cs0 pcs1/cs1 pcs2/cs2 pcs3/cs3 pcs4/cs4 pcs5/cs5 pcs6/cs6 pcs7/cs7 pdh0/a16 to pdh7/a23 pdl0/ad0 to pdl15/ad15 5 input status: independently connect to v dd5 or v ss5 via a resistor. output status: leave open. ad0_dbg to ad3_dbg note 1 5-ac independently connect to cv dd or cv ss via a resistor. trig_dbg note 1 3 leave open (low-level output). clk_dbg note 1 independently connect to cv ss via a resistor. sync note 1 2 independently connect to cv dd via a resistor. ic1 to ic4 note 2 ? leave open. ani00 to ani07, ani10 to ani17 7 connect to av ss . to000 to to005, to010 to to015 4 leave open. mode0 to mode2 ? v pp note 1 connect to v ss5 . ic5 note 2 independently connect to v ss5 via a resistor. reset ? cksel 2 ? x2 ? leave open. av ss ? connect to v ss5 . av ref0 , av ref1 ? connect to v ss5 . av dd ? connect to v dd5 . notes 1. pd70f3116 only 2. pd703116 only chapter 2 pin functions 47 user?s manual u14492ej4v1ud 2.5 pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics in type 3 p-ch out v dd n-ch type 4 push-pull output with possible high-impedance output (p-ch, n-ch both off) data output disable p-ch out v dd n-ch type 5 data output disable p-ch in/out v dd n-ch input enable type 5-ac type 7 in comparator + _ v ref (threshold voltage) p-ch n-ch p-ch n-ch v dd in/out data output disable input enable 48 user?s manual u14492ej4v1ud chapter 3 cpu function the cpu of the v850e/ia1 is based on ri sc architecture and executes almost all instructions in one clock cycle, using 5-stage pipeline control. 3.1 features minimum instruction execution time: 20 ns (@ internal 50 mhz operation) memory space program space: 64 mb linear data space: 4 gb linear thirty-two 32-bit general-purpose registers internal 32-bit architecture five-stage pipeline control multiplication/division instructions saturated operation instructions one-clock 32-bit shift instruction long/short format load/store instructions four types of bit manipulation instructions set1 clr1 not1 tst1 chapter 3 cpu function 49 user?s manual u14492ej4v1ud 3.2 cpu register set the registers of the v850e/ia1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. all the registers are 32-bit width. for details, refer to v850e1 architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (status saving register during nmi) (status saving register during nmi) eipc eipsw (status saving register during interrupt) (status saving register during interrupt) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (status saving register during exception/debug trap) (status saving register during exception/debug trap) ctpc ctpsw (status saving register during callt execution) (status saving register during callt execution) chapter 3 cpu function 50 user?s manual u14492ej4v1ud 3.2.1 program register set the program register set includes general -purpose registers and a program counter. (1) general-purpose registers thirty-two general-purpose registers, r0 to r31, are av ailable. any of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instruct ions, and care must be exercised when using these registers. r0 is a register that always holds 0, and is used for operations using 0 and offset 0 addressing. r30 is used, by means of the sld and sst instructions, as a base pointer for when memory is accessed. also, r1, r3 to r5, and r31 are implicitly used by the as sembler and c compiler. ther efore, before using these registers, their contents mu st be saved so that they are not lost. the contents must be restored to these registers after they have been used. r2 is sometimes used by a real-time os. r2 can be used as a register for variables when it is not being used by the real-time os. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register work ing register for generating address r2 address/data variable register (wh en not being used by the real-time os) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area (where program code is located) r6 to r29 address/dat a variable registers r30 element pointer base pointer for generating address when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution remark for detailed descriptions about r1, r3 to r5, and r31, which are used by the assembler and c compiler, refer to ca850 (c compiler package) asse mbly language user?s manual . (2) program counter (pc) this register holds the instruction address during program execution. the lower 26 bi ts of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occurs from bit 25 to 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address during execution 0 initial value 00000000h chapter 3 cpu function 51 user?s manual u14492ej4v1ud 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. to read/write these system r egisters, specify a system register number indicated below using the system register load/store instruction (lds r or stsr instruction). table 3-2. system register numbers operand specification no. system register name ldsr instruction stsr instruction 0 status saving register during interrupt (eipc) note 1 { { 1 status saving register during interrupt (eipsw) note 1 { { 2 status saving register during nmi (fepc) { { 3 status saving register during nmi (fepsw) { { 4 interrupt source register (ecr) { 5 program status word (psw) { { 6 to 15 reserved number for future function expansion (operations that access these register numbers cannot be guaranteed). 16 status saving register du ring callt execution (ctpc) { { 17 status saving register du ring callt execution (ctpsw) { { 18 status saving register du ring exception/debug trap (dbpc) { note 2 { 19 status saving register during exception/debug trap (dbpsw) { note 2 { 20 callt base pointer (ctbp) { { 21 to 31 reserved number for future function expansion (operations that access these register numbers cannot be guaranteed). notes 1. because this register has only one set, to allow multip le interrupts, it is necessary to save this register by program. 2. these registers can be accessed only after db trap instruction execution and before dbreti instruction execution. caution even if bit 0 of eipc, fepc, or ctpc is set to 1 with the ldsr instruction, bit 0 will be ignored when the program is returned by the reti instruction after in terrupt servicing (because bit 0 of the pc is fixed to 0). when setting the value of eipc, fepc, or ctpc, use an even value (bit 0 = 0). remark { : access allowed : access prohibited (1) interrupt source register (ecr) 31 0 ecr fecc eicc initial value 00000000h 16 15 bit position bit name function 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception/maskable interrupt chapter 3 cpu function 52 user?s manual u14492ej4v1ud (2) program status word (psw) 31 0 psw rfu initial value 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag function 31 to 8 rfu reserved field (fixed to 0). 7 np indicates that non-maskable interrupt (nmi ) servicing is in prog ress. this flag is set when an nmi is acknowledged, and disables multiple interrupts. 0: nmi servicing not under execution. 1: nmi servicing under execution. 6 ep indicates that exception processing is in progress. this flag is set when an exception is generated. moreover, interrupt requests can be acknowledged when this bit is set. 0: exception processing not under execution. 1: exception processing under execution. 5 id displays whether a maskable interr upt request can be acknowledged or not. 0: interrupt enabled. (ei) 1: interrupt disabled. (di) 4 sat note displays that the operation result of a saturated operation processing instruction is saturated due to overflow. due to the cumulative flag, if the operation result is saturated by the saturation operation instruction, this bit is set (1), but is not cleared (0) even if the operation results of subsequent instructions are not saturated. to clear (0) this bit, load the data in psw. note that in a general arithmetic operation, this bit is neither set (1) nor cleared (0). 0: not saturated. 1: saturated. 3 cy this flag is set if carry or borrow occurs as result of an operation (if carry or borrow does not occur, it is reset). 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note this flag is set if an overflow occurs du ring operation (if overflow does not occur, it is reset). 0: overflow does not occur. 1: overflow occurs. 1 s note this flag is set if the result of an operati on is negative (it is reset if the result is positive). 0: the operation result was positive or 0. 1: the operation result was negative. 0 z this flag is set if the result of an operati on is zero (if the result is not zero, it is reset). 0: the operation result was not 0. 1: the operation result was 0. note the result of a saturation-processed operation is dete rmined by the contents of the ov and s flags in the saturation operation. simply setting the ov flag (1 ) will set the sat flag (1) in a saturation operation. flag status status of operation result sat ov s saturation-processed operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (not exceeding the maximum) 0 negative (not exceeding the maximum) retain the value before operation 0 1 operation result itself chapter 3 cpu function 53 user?s manual u14492ej4v1ud 3.3 operation modes 3.3.1 operation modes the v850e/ia1 has the following operation modes. mode s pecification is carried out by the mode0 to mode2 pins. (1) normal operation mode (a) single-chip modes 0, 1 access to the internal rom is enabled. in single-chip mode 0, after the system reset is clear ed, each pin relate d to the bus inte rface enters the port mode, program execution branches to the reset entry address of the internal rom, and instruction processing starts. by setting the pmcdh, pmcdl , pmccs, pmcct, and pmccm registers to control mode by instruction, an external device can be connected to the external memory area. in single-chip mode 1, after the system reset is clear ed, each pin relate d to the bus inte rface enters the control mode, program execution branches to the ex ternal device?s (memory) reset entry address, and instruction processing starts. the intern al rom area is mapped from address 100000h. (b) romless modes 0, 1 after the system reset is cleared, each pin related to the bus interface enters the control mode, program execution branches to the external device?s (memo ry) reset entry address, and instruction processing starts. fetching of instructions and data access for internal rom becomes impossible. in romless mode 0, the data bus is a 16-bit data bus and in romless mode 1, the data bus is an 8-bit data bus. (2) flash memory programming mode ( pd70f3116 only) if this mode is specified, it becomes possible for the fl ash programmer to run a program to the internal flash memory. the initial values of the regist ers differ depending on the mode. operation mode pmcdh pmcdl pmccs pmcct pmccm bsc romless mode 0 ffh ffffh ffh 53h 0fh 5555h romless mode 1 ffh ffffh ffh 53h 0fh 0000h single-chip mode 0 00h 0000h 00h 00h 00h 5555h normal operation mode single-chip mode 1 ffh ffffh ffh 53h 0fh 5555h chapter 3 cpu function 54 user?s manual u14492ej4v1ud 3.3.2 operation mode specification the operation mode is specifi ed according to the status of pins mode0 to mode2. in an application system fix the specification of these pins and do not change them during operation. oper ation is not guaranteed if these pins are changed during operation. (a) pd703116 mode2 mode1 mode0 oper ation mode remark l l l romless mode 0 16-bit data bus l l h romless mode 1 8-bit data bus l h l single-chip mode 0 internal rom area is allocated from address 000000h. l h h normal operation mode single-chip mode 1 internal rom area is allocated from address 100000h. other than above setting prohibited (b) pd70f3116 v pp mode2 mode1 mode0 o peration mode remark 0 v l l l romless mode 0 16-bit data bus 0 v l l h romless mode 1 8-bit data bus 0 v l h l single-chip mode 0 internal rom area is allocated from address 000000h. 0 v l h h normal operation mode single-chip mode 1 internal rom area is allocated from address 100000h. 7.8 v l h h/l flash memory programming mode ? other than above setting prohibited remark l: low-level input h: high-level input chapter 3 cpu function 55 user?s manual u14492ej4v1ud 3.4 address space 3.4.1 cpu address space the cpu of the v850e/ia1 is of 32-bit architecture and sup ports up to 4 gb of linear address space (data space) during operand addressing (data access). also, in instru ction address addressing, a maximum of 64 mb of linear address space (program space) is supported. figure 3-1 shows the cpu address space. figure 3-1. cpu address space ffffffffh 04000000h 03ffffffh 00000000h data area (4 gb linear) program area (64 mb linear) cpu address space chapter 3 cpu function 56 user?s manual u14492ej4v1ud 3.4.2 image 16 images, each containing a 256 mb physical address spac e, are seen in the 4 gb cpu address space. in actuality, the same 256 mb physical a ddress space is accessed regardless of t he values of bits 31 to 28 of the cpu address. figure 3-2 shows the ima ge of the virtual addressing space. physical address x0000000h can be seen as cpu address 00000000h, and in addition, can be seen as address 10000000h, address 20000000h, ? , address e0000000h, or address f0000000h. figure 3-2. image on address space ffffffffh f0000000h efffffffh 00000000h internal rom image image image internal ram on-chip peripheral i/o external memory physical address space fffffffh 0000000h image image e0000000h dfffffffh 20000000h 1fffffffh 10000000h 0fffffffh cpu address space chapter 3 cpu function 57 user?s manual u14492ej4v1ud 3.4.3 wrap-around of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calculation, the higher 6 bits ignore the carry or borrow. therefore, the lower-limit address of the program sp ace, address 00000000h, and the upper-limit address 03ffffffh become contiguous addresses. wrap-around refers to a sit uation like this w hereby the lower- limit address and upper-limit address become contiguous. caution the 4 kb area of 03fff000h to 03ffffffh can be seen as an image of 0ffff000h to 0fffffffh. no instruction can be fetched from this area beca use this area is defined as on-chip peripheral i/o area. therefore, do not execute any branch a ddress calculation in which the result will reside in any part of this area. 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction ( ) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit address of the program sp ace, address 00000000h, and the upper-limit address ffffffffh are contiguous addresses, and the data space is wrapped around at th e boundary of these addresses. fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction ( ) direction chapter 3 cpu function 58 user?s manual u14492ej4v1ud 3.4.4 memory map the v850e/ia1 reserves areas as shown below. each mode is specified by the mode0 to mode2 pins. figure 3-3. memory map xfffffffh on-chip peripheral i/o area internal ram area on-chip peripheral i/o area internal ram area on-chip peripheral i/o area internal ram area access prohibited note external memory area internal rom area external memory area internal rom area external memory area single-chip mode 0 single-chip mode 1 romless mode 0, 1 256 mb 1 mb 1 mb 4 kb xffff000h xfffefffh xfffe800h xfffe7ffh x0200000h x01fffffh x0100000h x00fffffh x0000000h xfffc000h xfffbfffh 10 kb note by setting the pmcdh, pmcdl, pmccs, pmcct, and pm ccm registers to control mode, this area can be used as external memory area. chapter 3 cpu function 59 user?s manual u14492ej4v1ud 3.4.5 area (1) internal rom/intern al flash memory area (a) memory map up to 1 mb of internal rom/internal flash memory area is reserved. 256 kb are provided in the following addresses as physical internal rom (mask rom/flash memory). ? in single-chip mode 0: addresses 000000h to 03ffffh (addresses 040000h to 0fffffh are undefined) ? in single-chip mode 1: addr esses 0100000h to 013ffffh (addresses 0140000h to 01fffffh are undefined) figure 3-4. internal rom /internal flash memory area undefined undefined internal rom/ internal flash memory area internal rom/ internal flash memory area single-chip mode 0 single-chip mode 1 0fffffh 040000h 000000h 03ffffh 1fffffh 140000h 100000h 13ffffh (b) interrupt/exception table the v850e/ia1 increases the interrupt response s peed by assigning handler addresses corresponding to interrupts/exceptions. the collection of these handler addresses is called an interrupt/exception table, which is located in the internal rom area. when an interrupt/exception re quest is acknowledged, execution jumps to the handler address, and the program writt en at that memory is executed. table 3-3 shows the sources of interrupts/exceptions, and the corresponding addresses. remark when in romless modes 0, 1, or in single-chip mode 1, in order to resume correct operation after reset, provide a handler address to the rese t routine in address 0 of the external memory. chapter 3 cpu function 60 user?s manual u14492ej4v1ud table 3-3. interrupt/exception table start address of interrupt/exception table interrupt/exception source start address of interrupt/exception table interrupt/exception source 00000000h reset 00000200h intp21/intcc21 00000010h nmi0 00000210h intp22/intcc22 00000040h trap0n (n = 0 to f) 00000220h intp23/intcc23 00000050h trap1n (n = 0 to f) 00000230h intp24/intcc24 00000060h ilgop/dbg0 00000240h intp25/intcc25 00000080h intp0 00000250h inttm3 00000090h intp1 00000260h intp30/intcc30 000000a0h intp2 00000270h intp31/intcc31 000000b0h intp3 00000280h intcm4 000000c0h intp4 00000290h intdma0 000000d0h intp5 000002a0h intdma1 000000e0h intp6 000002b0h intdma2 000000f0h intdet0 000002c0h intdma3 00000100h intdet1 000002d0h intcrec 00000110h inttm00 000002e0h intctrx 00000120h intcm003 000002f0h intcerr 00000130h inttm01 00000300h intcmac 00000140h intcm013 00000310h intcsi0 00000150h intp100/intcc100 00000320h intcsi1 00000160h intp101/intcc101 00000330h intsr0 00000170h intcm100 00000340h intst0 00000180h intcm101 00000350h intser0 00000190h intp110/intcc110 00000360h intsr1 000001a0h intp111/intcc111 00000370h intst1 000001b0h intcm110 00000380h intsr2 000001c0h intcm111 00000390h intst2 000001d0h inttm20 000003a0h intad0 000001e0h inttm21 000003b0h intad1 000001f0h intp20/intcc20 chapter 3 cpu function 61 user?s manual u14492ej4v1ud (c) internal rom area relocation function if set in single-chip mode 1, the internal rom area is located beginning from address 100000h, so booting from external memory becomes possible. therefore, in order to resume correct operation afte r reset, provide a handler address to the reset routine in address 0 of the external memory. figure 3-5. internal rom area in single-chip mode 1 internal rom area external memory area 200000h 1fffffh 100000h 0fffffh 000000h block 0 note note see 4.3 memory block function . (2) internal ram area 12 kb of memory, addresses fffc000h to fffefffh, is reserved for the internal ram area. the 12 kb area of 3ffc000h to 3ffefffh can be seen as an image of fffc000h to fffefffh. in the v850e/ia1, 10 kb of memory , addresses fffc000h to fffe7ffh, is provided as ph ysical internal ram. access to the area of addresses fffe 800h to fffefffh is prohibited. internal ram area (10 kb) fffefffh fffe800h fffe7ffh fffc000h access prohibited chapter 3 cpu function 62 user?s manual u14492ej4v1ud (3) on-chip peripheral i/o area 4 kb of memory, addresses ffff000h to fffffffh, is provided as an on-chip peripheral i/o area. an image of addresses ffff000h to fffffffh can be seen in the ar ea between addresse s 3fff000h and 3ffffffh note . note access to the area of addresse s 3fff000h to 3ffffffh is prohibited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. fffffffh ffff000h on-chip peripheral i/o area (4 kb) on-chip peripheral i/o registers associ ated with the operation mode specif ication and the state monitoring for the on-chip peripherals i/o are all memory-mapped to t he on-chip peripheral i/o area. program fetches cannot be executed from this area. cautions 1. the least significant bit of an address is not decoded. therefore, if byte access is executed in the register at an odd address (2n + 1), the register at the even address (2n) will be accessed because of th e hardware specification. 2. in the v850e/ia1, no registers exist that ar e capable of word access, but if a register is word accessed, halfword access is performed t wice in the order of lower address, then higher address of the word area, ignorin g the lower 2 bits of the address. 3. for registers in which byte access is possible, if halfword access is executed, the higher 8 bits become undefined during the read operation, and the lower 8 bits of data are written to the register during the write operation. 4. addresses that are not defined as registers are reserved for fu ture expansion. if these addresses are accessed, the operation is undefined and not guaranteed. 5. addresses 3fff000h to 3ffffffh cannot be specified as the source/destination address of dma transfer. be sure to u se addresses ffff000h to fffffffh for the source/destination address of dma transfer. in the on-chip peripheral i/o area, a 16 kb area of addresses from x0000h to x3fffh is provided as a programmable peripheral i/o area. within this area, the area between x2 000h and x2fffh is used exclusively for the fcan controller (see 3.4.9 programmable peripheral i/o registers ). caution when emulating the fcan controller using the in-circuit emulator (ie-v850e-mc or ie- 703116-mc-em1), perform the following settings in the configuration screen that appears when the debugger is started. ? set the start address of the programmable pe ripheral i/o area that is set using the bpc register to the programable i/o area field. ? map the programmable peri pheral i/o area as ?target? or ?emulation ram? in the memory mapping field. chapter 3 cpu function 63 user?s manual u14492ej4v1ud (4) external memory area 256 mb are available for external memory area. the lower 64 mb can be used as program/data area and the higher 192 mb as data area. ? when in single-chip mode 0: x0100000h to xfffbfffh ? when in single-chip mode 1: x0000000h to x00fffffh , x0200000h to xfffbfffh ? when in romless modes 0 and 1: x0000000h to xfffbfffh access to the external memory area uses the chip-sel ect signal assigned to each memory block (which is carried out in the cs unit set by chip area sele ction control registers 0 and 1 (csc0, csc1)). note that, the internal rom, inte rnal ram, on-chip peripheral i/o, and programmable per ipheral i/o areas cannot be accessed as external memory areas. 3.4.6 external memory expansion by setting the port n mode control register (pmcn) to control mode, an external device can be connected to the external memory space using each pin of ports dh, dl, cs, ct, and cm. each register is set by selecting control mode for each pin of these ports usi ng pmcn (n = dh, dl, cs, ct, cm). note that the status after reset differs as shown below in accordance with the operating mode specification set by pins mode0 to mode2 (refer to 3.3 operation modes for details of the operation modes). (a) in the case of romless mode 0 because each pin of ports dh, dl, cs, ct, and cm enters control mode following a reset, external memory can be used without making changes to the port n mode control register (pmcn) (the external data bus width is 16 bits). (b) in the case of romless mode 1 because each pin of ports dh, dl, cs, ct, and cm enters control mode following a reset, external memory can be used without making changes to the port n mode control register (pmcn) (the external data bus width is 8 bits). (c) in the case of single-chip mode 0 since the internal rom area is accessed after a re set, each pin of ports dh, dl, cs, ct, and cm enters the port mode, and external devices cannot be used. to use external memory, set the por t n mode control register (pmcn). (d) in the case of single-chip mode 1 the internal rom area is allocated from address 1000 00h. as a result, because each pin of ports dh, dl, cs, ct, and cm enters control mode following a reset, external memory can be used without making changes to the port n mode control register (pmc n) (the external data bus width is 16 bits). remark n = dh, dl, cs, ct, cm chapter 3 cpu function 64 user?s manual u14492ej4v1ud 3.4.7 recommended use of address space the architecture of the v850e/ia1 r equires that a register that serves as a pointer be secured for address generation when accessing operand data in the data space. operand data access from instruction can be directly executed at the address in this pointer register 32 kb. however, because there is a limit to which general-purpose registers are used as a pointer register, by minimizing the deterioration of address calculation performance when changing the pointer value, the number of usable general-pur pose registers for handling variables is maximized, and the program size can be saved. to enhance the efficiency of using the pointer in connecti on with the memory map of the v850e/ia1, the following points are recommended: (1) program space of the 32 bits of the program counter (pc), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. therefore, a contiguous 64 mb space starti ng from address 00000000h corresponds to the memory map of the program space. (2) data space for the efficient use of resources that make use of the wrap-around feature of the da ta space, the continuous 16 mb address spaces 00000000h to 00ffffffh and ff000000h to ffffffffh of the 4 gb cpu are used as the data space. with the v850e/ia1, a 256 mb physical address space is seen as 16 images in the 4 gb cpu address space. the highest bit (bit 25) of this 26-bit address is assigned as address sign- extended to 32 bits. example application of wrap-around 00007fffh (r =) 00000000h ffffe7ffh ffff8000h internal rom area on-chip peripheral i/o area external memory area fffff000h ffffefffh ffffbfffh ffffe800h ffffc000h internal ram area 32 kb 4 kb 10 kb 16 kb 0003ffffh when r = r0 (zero register) is specified with the ld /st disp16 [r] instruction, an addressing range of 00000000h 32 kb can be referenced with the sign-extended disp16. by mapping the external memory in the 16 kb area in the figure, all resources including internal hardware can be accessed with one pointer. the zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers for the pointer. chapter 3 cpu function 65 user?s manual u14492ej4v1ud figure 3-6. recommended memory map ffffffffh fffffa78h fffffa77h fffff000h ffffefffh ffffe800h ffffe7ffh ffffc000h ffffbfffh 03ffe800h 03ffe7ffh 03fff000h 03ffefffh 03ffc000h 03ffbfffh 00100000h 000fffffh 00040000h 0003ffffh 00000000h 03ffffffh 04000000h xfffffffh xffff000h xfffefffh xfffc000h xfffbfffh xfffe800h xfffe7ffh x0100000h x00fffffh x0040000h x003ffffh x0000000h xffffa78h xffffa77h data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram external memory internal rom external memory external memory internal ram on-chip peripheral i/o note program space 64 mb internal rom internal rom note access to this area is prohibited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. remarks 1. the arrows indicate the recommended area. 2. this is a recommended memory map when the v850e/ia1 is set to single-chip mode 0, and used in external expansion mode. chapter 3 cpu function 66 user?s manual u14492ej4v1ud 3.4.8 on-chip peripheral i/o registers (1/11) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value fffff004h port dl pdl r/w undefined fffff004h port dll pdll r/w undefined fffff005h port dlh pdlh r/w undefined fffff006h port dh pdh r/w undefined fffff008h port cs pcs r/w undefined fffff00ah port ct pct r/w undefined fffff00ch port cm pcm r/w undefined fffff024h port dl mode register pmdl r/w ffffh fffff024h port dl mode register l pmdll r/w ffh fffff025h port dl mode register h pmdlh r/w ffh fffff026h port dh mode register pmdh r/w ffh fffff028h port cs mode register pmcs r/w ffh fffff02ah port ct mode register pmct r/w ffh fffff02ch port cm mode register pmcm r/w ffh fffff044h port dl mode control register pmcdl r/w 0000h/ffffh fffff044h port dl mode control register l pmcdll r/w 00h/ffh fffff045h port dl mode control register h pmcdlh r/w 00h/ffh fffff046h port dh mode control register pmcdh r/w 00h/ffh fffff048h port cs mode control register pmccs r/w 00h/ffh fffff04ah port ct mode control register pmcct r/w 00h/53h fffff04ch port cm mode control register pmccm r/w 00h/0fh fffff060h chip area selection control register 0 csc0 r/w 2c11h fffff062h chip area selection control register 1 csc1 r/w 2c11h fffff064h peripheral area selection control register bpc r/w 0000h fffff066h bus size configuration register bsc r/w 0000h/5555h fffff06eh system wait control register vswc r/w 77h fffff080h dma source address register 0l dsa0l r/w undefined fffff082h dma source address register 0h dsa0h r/w undefined fffff084h dma destination address register 0l dda0l r/w undefined fffff086h dma destination address register 0h dda0h r/w undefined fffff088h dma source address register 1l dsa1l r/w undefined fffff08ah dma source address register 1h dsa1h r/w undefined fffff08ch dma destination address register 1l dda1l r/w undefined fffff08eh dma destination address register 1h dda1h r/w undefined fffff090h dma source address register 2l dsa2l r/w undefined fffff092h dma source address register 2h dsa2h r/w undefined chapter 3 cpu function 67 user?s manual u14492ej4v1ud (2/11) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value fffff094h dma destination address register 2l dda2l r/w undefined fffff096h dma destination address register 2h dda2h r/w undefined fffff098h dma source address register 3l dsa3l r/w undefined fffff09ah dma source address register 3h dsa3h r/w undefined fffff09ch dma destination address register 3l dda3l r/w undefined fffff09eh dma destination address register 3h dda3h r/w undefined fffff0c0h dma transfer count register 0 dbc0 r/w undefined fffff0c2h dma transfer count register 1 dbc1 r/w undefined fffff0c4h dma transfer count register 2 dbc2 r/w undefined fffff0c6h dma transfer count register 3 dbc3 r/w undefined fffff0d0h dma addressing control register 0 dadc0 r/w 0000h fffff0d2h dma addressing control register 1 dadc1 r/w 0000h fffff0d4h dma addressing control register 2 dadc2 r/w 0000h fffff0d6h dma addressing control register 3 dadc3 r/w 0000h fffff0e0h dma channel control register 0 dchc0 r/w 00h fffff0e2h dma channel control register 1 dchc1 r/w 00h fffff0e4h dma channel control register 2 dchc2 r/w 00h fffff0e6h dma channel control register 3 dchc3 r/w 00h fffff0f0h dma disable status register ddis r 00h fffff0f2h dma restart register drst r/w 00h fffff100h interrupt mask register 0 imr0 r/w ffffh fffff100h interrupt mask register 0l imr0l r/w ffh fffff101h interrupt mask register 0h imr0h r/w ffh fffff102h interrupt mask register 1 imr1 r/w ffffh fffff102h interrupt mask register 1l imr1l r/w ffh fffff103h interrupt mask register 1h imr1h r/w ffh fffff104h interrupt mask register 2 imr2 r/w ffffh fffff104h interrupt mask register 2l imr2l r/w ffh fffff105h interrupt mask register 2h imr2h r/w ffh fffff106h interrupt mask register 3 imr3 r/w ffffh fffff106h interrupt mask register 3l imr3l r/w ffh fffff107h interrupt mask register 3h imr3h r/w ffh fffff110h interrupt control register p0ic0 r/w 47h fffff112h interrupt control register p0ic1 r/w 47h fffff114h interrupt control register p0ic2 r/w 47h fffff116h interrupt control register p0ic3 r/w 47h fffff118h interrupt control register p0ic4 r/w 47h chapter 3 cpu function 68 user?s manual u14492ej4v1ud (3/11) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value fffff11ah interrupt control register p0ic5 r/w 47h fffff11ch interrupt control register p0ic6 r/w 47h fffff11eh interrupt control register detic0 r/w 47h fffff120h interrupt control register detic1 r/w 47h fffff122h interrupt control register tm0ic0 r/w 47h fffff124h interrupt control register cm03ic0 r/w 47h fffff126h interrupt control register tm0ic1 r/w 47h fffff128h interrupt control register cm03ic1 r/w 47h fffff12ah interrupt control register cc10ic0 r/w 47h fffff12ch interrupt control register cc10ic1 r/w 47h fffff12eh interrupt control register cm10ic0 r/w 47h fffff130h interrupt control register cm10ic1 r/w 47h fffff132h interrupt control register cc11ic0 r/w 47h fffff134h interrupt control register cc11ic1 r/w 47h fffff136h interrupt control register cm11ic0 r/w 47h fffff138h interrupt control register cm11ic1 r/w 47h fffff13ah interrupt control register tm2ic0 r/w 47h fffff13ch interrupt control register tm2ic1 r/w 47h fffff13eh interrupt control register cc2ic0 r/w 47h fffff140h interrupt control register cc2ic1 r/w 47h fffff142h interrupt control register cc2ic2 r/w 47h fffff144h interrupt control register cc2ic3 r/w 47h fffff146h interrupt control register cc2ic4 r/w 47h fffff148h interrupt control register cc2ic5 r/w 47h fffff14ah interrupt control register tm3ic0 r/w 47h fffff14ch interrupt control register cc3ic0 r/w 47h fffff14eh interrupt control register cc3ic1 r/w 47h fffff150h interrupt control register cm4ic0 r/w 47h fffff152h interrupt control register dmaic0 r/w 47h fffff154h interrupt control register dmaic1 r/w 47h fffff156h interrupt control register dmaic2 r/w 47h fffff158h interrupt control register dmaic3 r/w 47h fffff15ah interrupt control register canic0 r/w 47h fffff15ch interrupt control register canic1 r/w 47h fffff15eh interrupt control register canic2 r/w 47h fffff160h interrupt control register canic3 r/w 47h fffff162h interrupt control register csiic0 r/w 47h chapter 3 cpu function 69 user?s manual u14492ej4v1ud (4/11) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value fffff164h interrupt control register csiic1 r/w 47h fffff166h interrupt control register sric0 r/w 47h fffff168h interrupt control register stic0 r/w 47h fffff16ah interrupt control register seic0 r/w 47h fffff16ch interrupt control register sric1 r/w 47h fffff16eh interrupt control register stic1 r/w 47h fffff170h interrupt control register sric2 r/w 47h fffff172h interrupt control register stic2 r/w 47h fffff174h interrupt control register adic0 r/w 47h fffff176h interrupt control register adic1 r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc r/w 00h fffff200h a/d scan mode register 00 adscm00 r/w 0000h fffff200h a/d scan mode register 00l adscm00l r/w 00h fffff201h a/d scan mode register 00h adscm00h r/w 00h fffff202h a/d scan mode register 01 adscm01 r/w 0000h fffff202h a/d scan mode register 01l adscm01l r 00h fffff203h a/d scan mode register 01h adscm01h r/w 00h fffff204h a/d voltage detection mode register 0 adetm0 r/w 0000h fffff204h a/d voltage detection mode register 0l adetm0l r/w 00h fffff205h a/d voltage detection mode register 0h adetm0h r/w 00h fffff210h a/d conversion result register 00 adcr00 r 0000h fffff212h a/d conversion result register 01 adcr01 r 0000h fffff214h a/d conversion result register 02 adcr02 r 0000h fffff216h a/d conversion result register 03 adcr03 r 0000h fffff218h a/d conversion result register 04 adcr04 r 0000h fffff21ah a/d conversion result register 05 adcr05 r 0000h fffff21ch a/d conversion result register 06 adcr06 r 0000h fffff21eh a/d conversion result register 07 adcr07 r 0000h fffff240h a/d scan mode register 10 adscm10 r/w 0000h fffff240h a/d scan mode register 10l adscm10l r/w 00h fffff241h a/d scan mode register 10h adscm10h r/w 00h fffff242h a/d scan mode register 11 adscm11 r/w 0000h fffff242h a/d scan mode register 11l adscm11l r 00h fffff243h a/d scan mode register 11h adscm11h r/w 00h chapter 3 cpu function 70 user?s manual u14492ej4v1ud (5/11) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value fffff244h a/d voltage detection mode register 1 adetm1 r/w 0000h fffff244h a/d voltage detection mode register 1l adetm1l r/w 00h fffff245h a/d voltage detection mode register 1h adetm1h r/w 00h fffff250h a/d conversion result register 10 adcr10 r 0000h fffff252h a/d conversion result register 11 adcr11 r 0000h fffff254h a/d conversion result register 12 adcr12 r 0000h fffff256h a/d conversion result register 13 adcr13 r 0000h fffff258h a/d conversion result register 14 adcr14 r 0000h fffff25ah a/d conversion result register 15 adcr15 r 0000h fffff25ch a/d conversion result register 16 adcr16 r 0000h fffff25eh a/d conversion result register 17 adcr17 r 0000h fffff280h a/d internal trigger selection register itrg0 r/w 00h fffff400h port 0 p0 r undefined fffff402h port 1 p1 r/w undefined fffff404h port 2 p2 r/w undefined fffff406h port 3 p3 r/w undefined fffff408h port 4 p4 r/w undefined fffff422h port 1 mode register pm1 r/w ffh fffff424h port 2 mode register pm2 r/w ffh fffff426h port 3 mode register pm3 r/w ffh fffff428h port 4 mode register pm4 r/w ffh fffff442h port 1 mode control register pmc1 r/w 00h fffff444h port 2 mode control register pmc2 r/w 00h fffff446h port 3 mode control register pmc3 r/w 00h fffff448h port 4 mode control register pmc4 r/w 00h fffff462h port 1 function control register pfc1 r/w 00h fffff464h port 2 function control register pfc2 r/w 00h fffff480h bus cycle type configuration register 0 bct0 r/w cccch fffff482h bus cycle type configuration register 1 bct1 r/w cccch fffff484h data wait control register 0 dwc0 r/w 3333h fffff486h data wait control register 1 dwc1 r/w 3333h fffff488h address wait control register awc r/w 0000h fffff48ah bus cycle control register bcc r/w aaaah fffff540h timer 4 tm4 r 0000h fffff542h compare register 4 cm4 r/w 0000h fffff544h timer control register 4 tmc4 r/w 00h fffff570h dead-time timer reload register 0 dtrr0 r/w 0fffh chapter 3 cpu function 71 user?s manual u14492ej4v1ud (6/11) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value fffff572h buffer register cm00 bfcm00 r/w ffffh fffff574h buffer register cm01 bfcm01 r/w ffffh fffff576h buffer register cm02 bfcm02 r/w ffffh fffff578h buffer register cm03 bfcm03 r/w ffffh fffff57ah timer control register 00 tmc00 r/w 0508h fffff57ah timer control register 00l tmc00l r/w 08h fffff57bh timer control register 00h tmc00h r/w 05h fffff57ch timer unit control register 00 tuc00 r/w 01h fffff57dh timer output mode register 0 tomr0 r/w 00h fffff57eh pwm software timing output register 0 psto0 r/w 00h fffff57fh pwm output enable register 0 poer0 r/w 00h fffff580h tomr write enable register 0 spec0 r/w 0000h fffff5b0h dead-time timer reload register 1 dtrr1 r/w 0fffh fffff5b2h buffer register cm10 bfcm10 r/w ffffh fffff5b4h buffer register cm11 bfcm11 r/w ffffh fffff5b6h buffer register cm12 bfcm12 r/w ffffh fffff5b8h buffer register cm13 bfcm13 r/w ffffh fffff5bah timer control register 01 tmc01 r/w 0508h fffff5bah timer control register 01l tmc01l r/w 08h fffff5bbh timer control register 01h tmc01h r/w 05h fffff5bch timer unit control register 01 tuc01 r/w 01h fffff5bdh timer output mode register 1 tomr1 r/w 00h fffff5beh pwm software timing output register 1 psto1 r/w 00h fffff5bfh pwm output enable register 1 poer1 r/w 00h fffff5c0h tomr write enable register 1 spec1 r/w 0000h fffff5d0h timer 0 clock sele ction register prm01 r/w 00h fffff5d8h timer 1/timer 2 clock selection register prm02 r/w 00h fffff5e0h timer 10 tm10 r/w 0000h fffff5e2h compare register 100 cm100 r/w 0000h fffff5e4h compare register 101 cm101 r/w 0000h fffff5e6h capture/compare register 100 cc100 r/w 0000h fffff5e8h capture/compare register 101 cc101 r/w 0000h fffff5eah capture/compare control register 0 ccr0 r/w 00h fffff5ebh timer unit mode register 0 tum0 r/w 00h fffff5ech timer control register 10 tmc10 r/w 00h fffff5edh signal edge selection register 10 sesa10 r/w 00h fffff5eeh prescaler mode register 10 prm10 r/w 07h chapter 3 cpu function 72 user?s manual u14492ej4v1ud (7/11) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value fffff5efh status register 0 status0 r 00h fffff5f6h cc101 capture input selection register csl10 r/w 00h fffff5f8h timer 10 noise elimination time selection register nrc10 r/w 00h fffff600h timer 11 tm11 r/w 0000h fffff602h compare register 110 cm110 r/w 0000h fffff604h compare register 111 cm111 r/w 0000h fffff606h capture/compare register 110 cc110 r/w 0000h fffff608h capture/compare register 111 cc111 r/w 0000h fffff60ah capture/compare control register 1 ccr1 r/w 00h fffff60bh timer unit mode register 1 tum1 r/w 00h fffff60ch timer control register 11 tmc11 r/w 00h fffff60dh signal edge selection register 11 sesa11 r/w 00h fffff60eh prescaler mode register 11 prm11 r/w 07h fffff60fh status register 1 status1 r 00h fffff616h cc111 capture input selection register csl11 r/w 00h fffff618h timer 11 noise elimination time selection register nrc11 r/w 00h fffff620h timer connection sele ction register 0 tmic0 r/w 00h fffff630h timer 2 input filter mode register 0 fem0 r/w 00h fffff631h timer 2 input filter mode register 1 fem1 r/w 00h fffff632h timer 2 input filter mode register 2 fem2 r/w 00h fffff633h timer 2 input filter mode register 3 fem3 r/w 00h fffff634h timer 2 input filter mode register 4 fem4 r/w 00h fffff635h timer 2 input filter mode register 5 fem5 r/w 00h fffff640h timer 2 clock stop register 0 stopte0 r/w 0000h fffff640h timer 2 clock stop register 0l stopte0l r 00h fffff641h timer 2 cloc k stop register 0h stopte0h r/w 00h fffff642h timer 2 count clock/control edge selection register 0 cse0 r/w 0000h fffff642h timer 2 count clock/control edge selection register 0l cse0l r/w 00h fffff643h timer 2 count clock/control edge selection register 0h cse0h r/w 00h fffff644h timer 2 sub-channel input event edge selection register 0 sese0 r/w 0000h fffff644h timer 2 sub-channel input event edge selection register 0l sese0l r/w 00h fffff645h timer 2 sub-channel input event edge selection register 0h sese0h r/w 00h chapter 3 cpu function 73 user?s manual u14492ej4v1ud (8/11) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value fffff646h timer 2 time base control register 0 tcre0 r/w 0000h fffff646h timer 2 time base control register 0l tcre0l r/w 00h fffff647h timer 2 time base control register 0h tcre0h r/w 00h fffff648h timer 2 output control register 0 octle0 r/w 0000h fffff648h timer 2 output control register 0l octle0l r/w 00h fffff649h timer 2 output control register 0h octle0h r/w 00h fffff64ah timer 2 sub-channel 0, 5 capture/compare control register cmse050 r/w 0000h fffff64ch timer 2 sub-channel 1, 2 capture/compare control register cmse120 r/w 0000h fffff64eh timer 2 sub-channel 3, 4 capture/compare control register cmse340 r/w 0000h fffff650h timer 2 sub-channel 1 sub capture/compare register cvse10 r/w 0000h fffff652h timer 2 sub-channel 1 main capture/compare register cvpe10 r 0000h fffff654h timer 2 sub-channel 2 sub capture/compare register cvse20 r/w 0000h fffff656h timer 2 sub-channel 2 main capture/compare register cvpe20 r 0000h fffff658h timer 2 sub-channel 3 sub capture/compare register cvse30 r/w 0000h fffff65ah timer 2 sub-channel 3 main capture/compare register cvpe30 r 0000h fffff65ch timer 2 sub-channel 4 sub capture/compare register cvse40 r/w 0000h fffff65eh timer 2 sub-channel 4 main capture/compare register cvpe40 r 0000h fffff660h timer 2 sub-channel 0 capture/compare register cvse00 r/w 0000h fffff662h timer 2 sub-channel 5 capture/compare register cvse50 r/w 0000h fffff664h timer 2 time base status register 0 tbstate0 r/w 0101h fffff664h timer 2 time base status register 0l tbstate0l r/w 01h fffff665h timer 2 time base status register 0h tbstate0h r/w 01h fffff666h timer 2 capture/compare 1 to 4 status register 0 ccstate0 r/w 0000h fffff666h timer 2 capture/compare 1 to 4 status register 0l ccstate0l r/w 00h fffff667h timer 2 capture/compare 1 to 4 status register 0h ccstate0h r/w 00h chapter 3 cpu function 74 user?s manual u14492ej4v1ud (9/11) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value fffff668h timer 2 output delay register 0 odele0 r/w 0000h fffff668h timer 2 output delay register 0l odele0l r/w 00h fffff669h timer 2 output delay register 0h odele0h r/w 00h fffff66ah timer 2 software event capture register csce0 r/w 0000h fffff680h timer 3 tm3 r 0000h fffff682h capture/compare register 30 cc30 r/w 0000h fffff684h capture/compare register 31 cc31 r/w 0000h fffff686h timer control register 30 tmc30 r/w 00h fffff688h timer control register 31 tmc31 r/w 20h fffff689h valid edge selection register sesc r/w 00h fffff690h timer 3 clock selection register prm03 r/w 00h fffff698h timer 3 noise elimination time selection register nrc3 r/w 00h fffff800h peripheral command register phcmd w undefined fffff802h peripheral status register phs r/w 00h fffff810h dma trigger factor register 0 dtfr0 r/w 00h fffff812h dma trigger factor register 1 dtfr1 r/w 00h fffff814h dma trigger factor register 2 dtfr2 r/w 00h fffff816h dma trigger factor register 3 dtfr3 r/w 00h fffff820h power save mode register psmr r/w 00h fffff822h clock control register ckc r/w 00h fffff824h lock register lockr r 0000000xb fffff880h external interrupt mode register 0 intm0 r/w 00h fffff882h external interrupt mode register 1 intm1 r/w 00h fffff884h external interrupt mode register 2 intm2 r/w 00h fffff8d4h flash programming mode control register flpmc r/w 08h/0ch/00h fffff900h clocked serial interf ace mode register 0 csim0 r/w 00h fffff901h clocked serial interface cl ock selection register 0 csic0 r/w 00h fffff902h clocked serial interface rec eption buffer register 0 sirb0 r 0000h fffff902h clocked serial interface reception buffer register l0 sirbl0 r 00h fffff904h clocked serial in terface transmission buffer register 0 sotb0 r/w 0000h fffff904h clocked serial in terface transmission buffer register l0 sotbl0 r/w 00h fffff906h clocked serial inte rface read-only reception buffer register 0 sirbe0 r 0000h fffff906h clocked serial in terface read-only reception buffer register l0 sirbel0 r 00h chapter 3 cpu function 75 user?s manual u14492ej4v1ud (10/11) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value fffff908h clocked serial inte rface initial transmission buffer register 0 sotbf0 r/w 0000h fffff908h clocked serial in terface initial transmission buffer register l0 sotbfl0 r/w 00h fffff90ah serial i/o shift register 0 sio0 r 0000h fffff90ah serial i/o shift register l0 siol0 r 00h fffff910h clocked serial interf ace mode register 1 csim1 r/w 00h fffff911h clocked serial in terface clock selection register 1 csic1 r/w 00h fffff912h clocked serial interface reception buffer register 1 sirb1 r 0000h fffff912h clocked serial interface reception buffer register l1 sirbl1 r 00h fffff914h clocked serial interface transmission buffer register 1 sotb1 r/w 0000h fffff914h clocked serial in terface transmission buffer register l1 sotbl1 r/w 00h fffff916h clocked serial inte rface read-only reception buffer register 1 sirbe1 r 0000h fffff916h clocked serial in terface read-only reception buffer register l1 sirbel1 r 00h fffff918h clocked serial inte rface initial transmission buffer register 1 sotbf1 r/w 0000h fffff918h clocked serial in terface initial transmission buffer register l1 sotbfl1 r/w 00h fffff91ah serial i/o shift register 1 sio1 r 0000h fffff91ah serial i/o shift register l1 siol1 r 00h fffff920h prescaler mode register 3 prsm3 r/w 00h fffff922h prescaler compare register 3 prscm3 r/w 00h fffff930h fcan clock selection register prm04 r/w 00h fffffa00h asynchronous serial interface mode register 0 asim0 r/w 01h fffffa02h reception buffer register 0 rxb0 r ffh fffffa03h asynchronous serial interface status register 0 asis0 r 00h fffffa04h transmission buffer register 0 txb0 r/w ffh fffffa05h asynchronous serial interface transmission status register 0 asif0 r 00h fffffa06h clock selection register 0 cksr0 r/w 00h fffffa07h baud rate generator control register 0 brgc0 r/w ffh fffffa20h 2-frame continuous reception buffer register 1 rxb1 r undefined fffffa22h reception buffer register l1 rxbl1 r undefined fffffa24h 2-frame continuous transmission shift register 1 txs1 w undefined chapter 3 cpu function 76 user?s manual u14492ej4v1ud (11/11) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value fffffa26h transmission shift register l1 txsl1 w undefined fffffa28h asynchronous serial interface mode register 10 asim10 r/w 81h fffffa2ah asynchronous serial interface mode register 11 asim11 r/w 00h fffffa2ch asynchronous serial interface status register 1 asis1 r 00h fffffa2eh prescaler mode register 1 prsm1 r/w 00h fffffa30h prescaler compare register 1 prscm1 r/w 00h fffffa40h 2-frame continuous reception buffer register 2 rxb2 r undefined fffffa42h reception buffer register l2 rxbl2 r undefined fffffa44h 2-frame continuous transmission shift register 2 txs2 w undefined fffffa46h transmission shift register l2 txsl2 w undefined fffffa48h asynchronous serial interface mode register 20 asim20 r/w 81h fffffa4ah asynchronous serial interface mode register 21 asim21 r/w 00h fffffa4ch asynchronous serial interface status register 2 asis2 r 00h fffffa4eh prescaler mode register 2 prsm2 r/w 00h fffffa50h prescaler compare register 2 prscm2 r/w 00h fffffa60h ram access data buffer register l nbdl r/w 0000h fffffa60h ram access data buffer register ll nbdll r/w 00h fffffa61h ram access data buffer register lu nbdlu r/w 00h fffffa62h ram access data buffer register h nbdh r/w 0000h fffffa62h ram access data buffer register hl nbdhl r/w 00h fffffa63h ram access data buffer register hu nbdhu r/w 00h fffffa64h dma source address setting register sl nbdmsl r undefined fffffa66h dma source address setting register sh nbdmsh r undefined fffffa68h dma destination address setti ng register dl nbdmdl r undefined fffffa6ah dma destination address se tting register dh nbdmdh r undefined chapter 3 cpu function 77 user?s manual u14492ej4v1ud 3.4.9 programmable peri pheral i/o registers in the v850e/ia1, the 16 kb area of x0000h to x3fffh is provided as a progr ammable per ipheral i/o area. in this area, the area between x2000h and x2fffh is used exclusively for the fcan controller. the internal bus of the v850e/ia1 becomes active when the on-chip peripheral i/o r egister area (ffff000h to fffffffh) or the programmable peripheral i/o register area (xxxxm000h to xxxxnfffh) is accessed (m = xx00b, n = xx11b). however, the on-chip perip heral i/o area is allocated to the last 4 kb of the programmable peripheral i/o register area. note that when data is written to this area, the written contents are reflec ted on the on-chip peripheral i/o area. therefore, access to this area is prohibited. to access the on-chi p peripheral i/o area, be sure to specify addresses ffff000h to fffffffh. figure 3-7. programmable peri pheral i/o register (outline) 3ffffffh 3fff000h 3ffefffh xxxxnfffh xxxxm000h x3fffh x3000h x2fffh x2000h x0000h x1fffh 0000000h on-chip peripheral i/o register programmable peripheral i/o register internal local bus dedicated area for fcan controller on-chip peripheral i/o area programmable peripheral i/o area caution the can message buffer register can a llocate address xxxx freely as a programmable peripheral i/o register. but once the addr ess xxxx is set, it cannot be changed. remark m = xx00b n = xx11b the peripheral area selectio n control register (bpc) is used for programmable peripheral i/o register area selection. caution when emulating the fcan c ontroller using the in-circuit emulator (ie-v850e-mc or ie-703116- mc-em1), perform the following settings in the configuration screen that appears when the debugger is started. ? set the start address of the programmable pe ripheral i/o area that is set using the bpc register to the programable i/o area field. ? map the programmable peripheral i/o area as ?t arget? or ?emulation ram? in the memory mapping field. chapter 3 cpu function 78 user?s manual u14492ej4v1ud (1) peripheral area selecti on control register (bpc) this register can be read/ written in 16-bit units. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address initial value bpc pa15 0 pa13 pa12 pa11 pa10 pa09 pa08 pa07 pa06 pa05 pa04 pa03 pa02 pa01 pa00 fffff064h 0000h bit position bit name function enables/disables usage of prog rammable peripheral i/o area pa15 usage of programmable peripheral i/o area 0 disables usage of program mable peripheral i/o area 1 enables usage of program mable peripheral i/o area 15 pa15 13 to 0 pa13 to pa00 specifies an address in progra mmable peripheral i/o area (corresponds to a27 to a14, respectively). a list of the programmable peripheral i/o registers is shown below. chapter 3 cpu function 79 user?s manual u14492ej4v1ud (1/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxn804h can message data length register 00 m_dlc00 r/w undefined xxxxn805h can message control r egister 00 m_ctrl00 r/w undefined xxxxn806h can message time stamp register 00 m_time00 r/w undefined xxxxn808h can message data register 000 m_data000 r/w undefined xxxxn809h can message data register 001 m_data001 r/w undefined xxxxn80ah can message data register 002 m_data002 r/w undefined xxxxn80bh can message data register 003 m_data003 r/w undefined xxxxn80ch can message data register 004 m_data004 r/w undefined xxxxn80dh can message data register 005 m_data005 r/w undefined xxxxn80eh can message data register 006 m_data006 r/w undefined xxxxn80fh can message data register 007 m_data007 r/w undefined xxxxn810h can message id register l00 m_idl00 r/w undefined xxxxn812h can message id register h00 m_idh00 r/w undefined xxxxn814h can message configurati on register 00 m_conf00 r/w undefined xxxxn815h can message status register 00 m_stat00 r undefined xxxxn816h can status set/clear register 00 sc_stat00 w 0000h xxxxn824h can message data length register 01 m_dlc01 r/w undefined xxxxn825h can message control r egister 01 m_ctrl01 r/w undefined xxxxn826h can message time stamp register 01 m_time01 r/w undefined xxxxn828h can message data register 010 m_data010 r/w undefined xxxxn829h can message data register 011 m_data011 r/w undefined xxxxn82ah can message data register 012 m_data012 r/w undefined xxxxn82bh can message data register 013 m_data013 r/w undefined xxxxn82ch can message data register 014 m_data014 r/w undefined xxxxn82dh can message data register 015 m_data015 r/w undefined xxxxn82eh can message data register 016 m_data016 r/w undefined xxxxn82fh can message data register 017 m_data017 r/w undefined xxxxn830h can message id register l01 m_idl01 r/w undefined xxxxn832h can message id register h01 m_idh01 r/w undefined xxxxn834h can message configurati on register 01 m_conf01 r/w undefined xxxxn835h can message status register 01 m_stat01 r undefined xxxxn836h can status set/clear register 01 sc_stat01 w 0000h xxxxn844h can message data length register 02 m_dlc02 r/w undefined xxxxn845h can message control r egister 02 m_ctrl02 r/w undefined xxxxn846h can message time stamp register 02 m_time02 r/w undefined xxxxn848h can message data register 020 m_data020 r/w undefined remark n = 2, 6, a, or e chapter 3 cpu function 80 user?s manual u14492ej4v1ud (2/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxn849h can message data register 021 m_data021 r/w undefined xxxxn84ah can message data register 022 m_data022 r/w undefined xxxxn84bh can message data register 023 m_data023 r/w undefined xxxxn84ch can message data register 024 m_data024 r/w undefined xxxxn84dh can message data register 025 m_data025 r/w undefined xxxxn84eh can message data register 026 m_data026 r/w undefined xxxxn84fh can message data register 027 m_data027 r/w undefined xxxxn850h can message id register l02 m_idl02 r/w undefined xxxxn852h can message id register h02 m_idh02 r/w undefined xxxxn854h can message configurati on register 02 m_conf02 r/w undefined xxxxn855h can message status register 02 m_stat02 r undefined xxxxn856h can status set/clear register 02 sc_stat02 w 0000h xxxxn864h can message data length register 03 m_dlc03 r/w undefined xxxxn865h can message control r egister 03 m_ctrl03 r/w undefined xxxxn866h can message time stamp register 03 m_time03 r/w undefined xxxxn868h can message data register 030 m_data030 r/w undefined xxxxn869h can message data register 031 m_data031 r/w undefined xxxxn86ah can message data register 032 m_data032 r/w undefined xxxxn86bh can message data register 033 m_data033 r/w undefined xxxxn86ch can message data register 034 m_data034 r/w undefined xxxxn86dh can message data register 035 m_data035 r/w undefined xxxxn86eh can message data register 036 m_data036 r/w undefined xxxxn86fh can message data register 037 m_data037 r/w undefined xxxxn870h can message id register l03 m_idl03 r/w undefined xxxxn872h can message id register h03 m_idh03 r/w undefined xxxxn874h can message configurati on register 03 m_conf03 r/w undefined xxxxn875h can message status register 03 m_stat03 r undefined xxxxn876h can status set/clear register 03 sc_stat03 w 0000h xxxxn884h can message data length register 04 m_dlc04 r/w undefined xxxxn885h can message control r egister 04 m_ctrl04 r/w undefined xxxxn886h can message time stamp register 04 m_time04 r/w undefined xxxxn888h can message data register 040 m_data040 r/w undefined xxxxn889h can message data register 041 m_data041 r/w undefined xxxxn88ah can message data register 042 m_data042 r/w undefined xxxxn88bh can message data register 043 m_data043 r/w undefined xxxxn88ch can message data register 044 m_data044 r/w undefined remark n = 2, 6, a, or e chapter 3 cpu function 81 user?s manual u14492ej4v1ud (3/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxn88dh can message data register 045 m_data045 r/w undefined xxxxn88eh can message data register 046 m_data046 r/w undefined xxxxn88fh can message data register 047 m_data047 r/w undefined xxxxn890h can message id register l04 m_idl04 r/w undefined xxxxn882h can message id register h04 m_idh04 r/w undefined xxxxn894h can message configurati on register 04 m_conf04 r/w undefined xxxxn895h can message status register 04 m_stat04 r undefined xxxxn896h can status set/clear register 04 sc_stat04 w 0000h xxxxn8a4h can message data length register 05 m_dlc05 r/w undefined xxxxn8a5h can message control r egister 05 m_ctrl05 r/w undefined xxxxn8a6h can message time stamp register 05 m_time05 r/w undefined xxxxn8a8h can message data register 050 m_data050 r/w undefined xxxxn8a9h can message data register 051 m_data051 r/w undefined xxxxn8aah can message data register 052 m_data052 r/w undefined xxxxn8abh can message data register 053 m_data053 r/w undefined xxxxn8ach can message data register 054 m_data054 r/w undefined xxxxn8adh can message data register 055 m_data055 r/w undefined xxxxn8aeh can message data register 056 m_data056 r/w undefined xxxxn8afh can message data register 057 m_data057 r/w undefined xxxxn8b0h can message id register l05 m_idl05 r/w undefined xxxxn8b2h can message id register h05 m_idh05 r/w undefined xxxxn8b4h can message configurat ion register 05 m_conf05 r/w undefined xxxxn8b5h can message status register 05 m_stat05 r undefined xxxxn8b6h can status set/clear register 05 sc_stat05 w 0000h xxxxn8c4h can message data length register 06 m_dlc06 r/w undefined xxxxn8c5h can message control r egister 06 m_ctrl06 r/w undefined xxxxn8c6h can message time stamp register 06 m_time06 r/w undefined xxxxn8c8h can message data register 060 m_data060 r/w undefined xxxxn8c9h can message data register 061 m_data061 r/w undefined xxxxn8cah can message data register 062 m_data062 r/w undefined xxxxn8cbh can message data register 063 m_data063 r/w undefined xxxxn8cch can message data register 064 m_data064 r/w undefined xxxxn8cdh can message data register 065 m_data065 r/w undefined xxxxn8ceh can message data register 066 m_data066 r/w undefined xxxxn8cfh can message data register 067 m_data067 r/w undefined xxxxn8d0h can message id register l06 m_idl06 r/w undefined remark n = 2, 6, a, or e chapter 3 cpu function 82 user?s manual u14492ej4v1ud (4/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxn8d2h can message id register h06 m_idh06 r/w undefined xxxxn8d4h can message configurat ion register 06 m_conf06 r/w undefined xxxxn8d5h can message status register 06 m_stat06 r undefined xxxxn8d6h can status set/clear register 06 sc_stat06 w 0000h xxxxn8e4h can message data length register 07 m_dlc07 r/w undefined xxxxn8e5h can message control r egister 07 m_ctrl07 r/w undefined xxxxn8e6h can message time stamp register 07 m_time07 r/w undefined xxxxn8e8h can message data register 070 m_data070 r/w undefined xxxxn8e9h can message data register 071 m_data071 r/w undefined xxxxn8eah can message data register 072 m_data072 r/w undefined xxxxn8ebh can message data register 073 m_data073 r/w undefined xxxxn8ech can message data register 074 m_data074 r/w undefined xxxxn8edh can message data register 075 m_data075 r/w undefined xxxxn8eeh can message data register 076 m_data076 r/w undefined xxxxn8efh can message data register 077 m_data077 r/w undefined xxxxn8f0h can message id register l07 m_idl07 r/w undefined xxxxn8f2h can message id register h07 m_idh07 r/w undefined xxxxn8f4h can message configurat ion register 07 m_conf07 r/w undefined xxxxn8f5h can message status register 07 m_stat07 r undefined xxxxn8f6h can status set/clear register 07 sc_stat07 w 0000h xxxxn904h can message data length register 08 m_dlc08 r/w undefined xxxxn905h can message control r egister 08 m_ctrl08 r/w undefined xxxxn906h can message time stamp register 08 m_time08 r/w undefined xxxxn908h can message data register 080 m_data080 r/w undefined xxxxn909h can message data register 081 m_data081 r/w undefined xxxxn90ah can message data register 082 m_data082 r/w undefined xxxxn90bh can message data register 083 m_data083 r/w undefined xxxxn90ch can message data register 084 m_data084 r/w undefined xxxxn90dh can message data register 085 m_data085 r/w undefined xxxxn90eh can message data register 086 m_data086 r/w undefined xxxxn90fh can message data register 087 m_data087 r/w undefined xxxxn910h can message id register l08 m_idl08 r/w undefined xxxxn912h can message id register h08 m_idh08 r/w undefined xxxxn914h can message configurati on register 08 m_conf08 r/w undefined xxxxn915h can message status register 08 m_stat08 r undefined xxxxn916h can status set/clear register 08 sc_stat08 w 0000h remark n = 2, 6, a, or e chapter 3 cpu function 83 user?s manual u14492ej4v1ud (5/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxn924h can message data length register 09 m_dlc09 r/w undefined xxxxn925h can message control r egister 09 m_ctrl09 r/w undefined xxxxn926h can message time stamp register 09 m_time09 r/w undefined xxxxn928h can message data register 090 m_data090 r/w undefined xxxxn929h can message data register 091 m_data091 r/w undefined xxxxn92ah can message data register 092 m_data092 r/w undefined xxxxn92bh can message data register 093 m_data093 r/w undefined xxxxn92ch can message data register 094 m_data094 r/w undefined xxxxn92dh can message data register 095 m_data095 r/w undefined xxxxn92eh can message data register 096 m_data096 r/w undefined xxxxn92fh can message data register 097 m_data097 r/w undefined xxxxn930h can message id register l09 m_idl09 r/w undefined xxxxn932h can message id register h09 m_idh09 r/w undefined xxxxn934h can message configurati on register 09 m_conf09 r/w undefined xxxxn935h can message status register 09 m_stat09 r undefined xxxxn936h can status set/clear register 09 sc_stat09 w 0000h xxxxn944h can message data length register 10 m_dlc10 r/w undefined xxxxn945h can message control r egister 10 m_ctrl10 r/w undefined xxxxn946h can message time stamp register 10 m_time10 r/w undefined xxxxn948h can message data register 100 m_data100 r/w undefined xxxxn949h can message data register 101 m_data101 r/w undefined xxxxn94ah can message data register 102 m_data102 r/w undefined xxxxn94bh can message data register 103 m_data103 r/w undefined xxxxn94ch can message data register 104 m_data104 r/w undefined xxxxn94dh can message data register 105 m_data105 r/w undefined xxxxn94eh can message data register 106 m_data106 r/w undefined xxxxn94fh can message data register 107 m_data107 r/w undefined xxxxn950h can message id register l10 m_idl10 r/w undefined xxxxn952h can message id register h10 m_idh10 r/w undefined xxxxn954h can message configurati on register 10 m_conf10 r/w undefined xxxxn955h can message status register 10 m_stat10 r undefined xxxxn956h can status set/clear register 10 sc_stat10 w 0000h xxxxn964h can message data length register 11 m_dlc11 r/w undefined xxxxn965h can message control r egister 11 m_ctrl11 r/w undefined xxxxn966h can message time stamp register 11 m_time11 r/w undefined xxxxn968h can message data register 110 m_data110 r/w undefined remark n = 2, 6, a, or e chapter 3 cpu function 84 user?s manual u14492ej4v1ud (6/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxn969h can message data register 111 m_data111 r/w undefined xxxxn96ah can message data register 112 m_data112 r/w undefined xxxxn96bh can message data register 113 m_data113 r/w undefined xxxxn96ch can message data register 114 m_data114 r/w undefined xxxxn96dh can message data register 115 m_data115 r/w undefined xxxxn96eh can message data register 116 m_data116 r/w undefined xxxxn96fh can message data register 117 m_data117 r/w undefined xxxxn970h can message id register l11 m_idl11 r/w undefined xxxxn972h can message id register h11 m_idh11 r/w undefined xxxxn974h can message configurati on register 11 m_conf11 r/w undefined xxxxn975h can message status register 11 m_stat11 r undefined xxxxn976h can status set/clear register 11 sc_stat11 w 0000h xxxxn984h can message data length register 12 m_dlc12 r/w undefined xxxxn985h can message control r egister 12 m_ctrl12 r/w undefined xxxxn986h can message time stamp register 12 m_time12 r/w undefined xxxxn988h can message data register 120 m_data120 r/w undefined xxxxn989h can message data register 121 m_data121 r/w undefined xxxxn98ah can message data register 122 m_data122 r/w undefined xxxxn98bh can message data register 123 m_data123 r/w undefined xxxxn98ch can message data register 124 m_data124 r/w undefined xxxxn98dh can message data register 125 m_data125 r/w undefined xxxxn98eh can message data register 126 m_data126 r/w undefined xxxxn98fh can message data register 127 m_data127 r/w undefined xxxxn990h can message id register l12 m_idl12 r/w undefined xxxxn992h can message id register h12 m_idh12 r/w undefined xxxxn994h can message configurati on register 12 m_conf12 r/w undefined xxxxn995h can message status register 12 m_stat12 r undefined xxxxn996h can status set/clear register 12 sc_stat12 w 0000h xxxxn9a4h can message data length register 13 m_dlc13 r/w undefined xxxxn9a5h can message control r egister 13 m_ctrl13 r/w undefined xxxxn9a6h can message time stamp register 13 m_time13 r/w undefined xxxxn9a8h can message data register 130 m_data130 r/w undefined xxxxn9a9h can message data register 131 m_data131 r/w undefined xxxxn9aah can message data register 132 m_data132 r/w undefined xxxxn9abh can message data register 133 m_data133 r/w undefined xxxxn9ach can message data register 134 m_data134 r/w undefined remark n = 2, 6, a, or e chapter 3 cpu function 85 user?s manual u14492ej4v1ud (7/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxn9adh can message data register 135 m_data135 r/w undefined xxxxn9aeh can message data register 136 m_data136 r/w undefined xxxxn9afh can message data register 137 m_data137 r/w undefined xxxxn9b0h can message id register l13 m_idl13 r/w undefined xxxxn9b2h can message id register h13 m_idh13 r/w undefined xxxxn9b4h can message configurat ion register 13 m_conf13 r/w undefined xxxxn9b5h can message status register 13 m_stat13 r undefined xxxxn9b6h can status set/clear register 13 sc_stat13 w 0000h xxxxn9c4h can message data length register 14 m_dlc14 r/w undefined xxxxn9c5h can message control r egister 14 m_ctrl14 r/w undefined xxxxn9c6h can message time stamp register 14 m_time14 r/w undefined xxxxn9c8h can message data register 140 m_data140 r/w undefined xxxxn9c9h can message data register 141 m_data141 r/w undefined xxxxn9cah can message data register 142 m_data142 r/w undefined xxxxn9cbh can message data register 143 m_data143 r/w undefined xxxxn9cch can message data register 144 m_data144 r/w undefined xxxxn9cdh can message data register 145 m_data145 r/w undefined xxxxn9ceh can message data register 146 m_data146 r/w undefined xxxxn9cfh can message data register 147 m_data147 r/w undefined xxxxn9d0h can message id register l14 m_idl14 r/w undefined xxxxn9d2h can message id register h14 m_idh14 r/w undefined xxxxn9d4h can message configurat ion register 14 m_conf14 r/w undefined xxxxn9d5h can message status register 14 m_stat14 r undefined xxxxn9d6h can status set/clear register 14 sc_stat14 w 0000h xxxxn9e4h can message data length register 15 m_dlc15 r/w undefined xxxxn9e5h can message control r egister 15 m_ctrl15 r/w undefined xxxxn9e6h can message time stamp register 15 m_time15 r/w undefined xxxxn9e8h can message data register 150 m_data150 r/w undefined xxxxn9e9h can message data register 151 m_data151 r/w undefined xxxxn9eah can message data register 152 m_data152 r/w undefined xxxxn9ebh can message data register 153 m_data153 r/w undefined xxxxn9ech can message data register 154 m_data154 r/w undefined xxxxn9edh can message data register 155 m_data155 r/w undefined xxxxn9eeh can message data register 156 m_data156 r/w undefined xxxxn9efh can message data register 157 m_data157 r/w undefined xxxxn9f0h can message id register l15 m_idl15 r/w undefined remark n = 2, 6, a, or e chapter 3 cpu function 86 user?s manual u14492ej4v1ud (8/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxn9f2h can message id register h15 m_idh15 r/w undefined xxxxn9f4h can message configurat ion register 15 m_conf15 r/w undefined xxxxn9f5h can message status register 15 m_stat15 r undefined xxxxn9f6h can status set/clear register 15 sc_stat15 w 0000h xxxxna04h can message data length register 16 m_dlc16 r/w undefined xxxxna05h can message control r egister 16 m_ctrl16 r/w undefined xxxxna06h can message time stamp register 16 m_time16 r/w undefined xxxxna08h can message data register 160 m_data160 r/w undefined xxxxna09h can message data register 161 m_data161 r/w undefined xxxxna0ah can message data register 162 m_data162 r/w undefined xxxxna0bh can message data register 163 m_data163 r/w undefined xxxxna0ch can message data register 164 m_data164 r/w undefined xxxxna0dh can message data register 165 m_data165 r/w undefined xxxxna0eh can message data register 166 m_data166 r/w undefined xxxxna0fh can message data register 167 m_data167 r/w undefined xxxxna10h can message id register l16 m_idl16 r/w undefined xxxxna12h can message id register h16 m_idh16 r/w undefined xxxxna14h can message configurat ion register 16 m_conf16 r/w undefined xxxxna15h can message status register 16 m_stat16 r undefined xxxxna16h can status set/clear register 16 sc_stat16 w 0000h xxxxna24h can message data length register 17 m_dlc17 r/w undefined xxxxna25h can message control r egister 17 m_ctrl17 r/w undefined xxxxna26h can message time stamp register 17 m_time17 r/w undefined xxxxna28h can message data register 170 m_data170 r/w undefined xxxxna29h can message data register 171 m_data171 r/w undefined xxxxna2ah can message data register 172 m_data172 r/w undefined xxxxna2bh can message data register 173 m_data173 r/w undefined xxxxna2ch can message data register 174 m_data174 r/w undefined xxxxna2dh can message data register 175 m_data175 r/w undefined xxxxna2eh can message data register 176 m_data176 r/w undefined xxxxna2fh can message data register 177 m_data177 r/w undefined xxxxna30h can message id register l17 m_idl17 r/w undefined xxxxna32h can message id register h17 m_idh17 r/w undefined xxxxna34h can message configurat ion register 17 m_conf17 r/w undefined xxxxna35h can message status register 17 m_stat17 r undefined xxxxna36h can status set/clear register 17 sc_stat17 w 0000h remark n = 2, 6, a, or e chapter 3 cpu function 87 user?s manual u14492ej4v1ud (9/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxna44h can message data length register 18 m_dlc18 r/w undefined xxxxna45h can message control r egister 18 m_ctrl18 r/w undefined xxxxna46h can message time stamp register 18 m_time18 r/w undefined xxxxna48h can message data register 180 m_data180 r/w undefined xxxxna49h can message data register 181 m_data181 r/w undefined xxxxna4ah can message data register 182 m_data182 r/w undefined xxxxna4bh can message data register 183 m_data183 r/w undefined xxxxna4ch can message data register 184 m_data184 r/w undefined xxxxna4dh can message data register 185 m_data185 r/w undefined xxxxna4eh can message data register 186 m_data186 r/w undefined xxxxna4fh can message data register 187 m_data187 r/w undefined xxxxna50h can message id register l18 m_idl18 r/w undefined xxxxna52h can message id register h18 m_idh18 r/w undefined xxxxna54h can message configurat ion register 18 m_conf18 r/w undefined xxxxna55h can message status register 18 m_stat18 r undefined xxxxna56h can status set/clear register 18 sc_stat18 w 0000h xxxxna64h can message data length register 19 m_dlc19 r/w undefined xxxxna65h can message control r egister 19 m_ctrl19 r/w undefined xxxxna66h can message time stamp register 19 m_time19 r/w undefined xxxxna68h can message data register 190 m_data190 r/w undefined xxxxna69h can message data register 191 m_data191 r/w undefined xxxxna6ah can message data register 192 m_data192 r/w undefined xxxxna6bh can message data register 193 m_data193 r/w undefined xxxxna6ch can message data register 194 m_data194 r/w undefined xxxxna6dh can message data register 195 m_data195 r/w undefined xxxxna6eh can message data register 196 m_data196 r/w undefined xxxxna6fh can message data register 197 m_data197 r/w undefined xxxxna70h can message id register l19 m_idl19 r/w undefined xxxxna72h can message id register h19 m_idh19 r/w undefined xxxxna74h can message configurat ion register 19 m_conf19 r/w undefined xxxxna75h can message status register 19 m_stat19 r undefined xxxxna76h can status set/clear register 19 sc_stat19 w 0000h xxxxna84h can message data length register 20 m_dlc20 r/w undefined xxxxna85h can message control r egister 20 m_ctrl20 r/w undefined xxxxna86h can message time stamp register 20 m_time20 r/w undefined xxxxna88h can message data register 200 m_data200 r/w undefined remark n = 2, 6, a, or e chapter 3 cpu function 88 user?s manual u14492ej4v1ud (10/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxna89h can message data register 201 m_data201 r/w undefined xxxxna8ah can message data register 202 m_data202 r/w undefined xxxxna8bh can message data register 203 m_data203 r/w undefined xxxxna8ch can message data register 204 m_data204 r/w undefined xxxxna8dh can message data register 205 m_data205 r/w undefined xxxxna8eh can message data register 206 m_data206 r/w undefined xxxxna8fh can message data register 207 m_data207 r/w undefined xxxxna90h can message id register l20 m_idl20 r/w undefined xxxxna92h can message id register h20 m_idh20 r/w undefined xxxxna94h can message configurat ion register 20 m_conf20 r/w undefined xxxxna95h can message status register 20 m_stat20 r undefined xxxxna96h can status set/clear register 20 sc_stat20 w 0000h xxxxnaa4h can message data length register 21 m_dlc21 r/w undefined xxxxnaa5h can message control r egister 21 m_ctrl21 r/w undefined xxxxnaa6h can message time stamp register 21 m_time21 r/w undefined xxxxnaa8h can message data register 210 m_data210 r/w undefined xxxxnaa9h can message data register 211 m_data211 r/w undefined xxxxnaaah can message data register 212 m_data212 r/w undefined xxxxnaabh can message data register 213 m_data213 r/w undefined xxxxnaach can message data register 214 m_data214 r/w undefined xxxxnaadh can message data register 215 m_data215 r/w undefined xxxxnaaeh can message data register 216 m_data216 r/w undefined xxxxnaafh can message data register 217 m_data217 r/w undefined xxxxnab0h can message id register l21 m_idl21 r/w undefined xxxxnab2h can message id register h21 m_idh21 r/w undefined xxxxnab4h can message configurat ion register 21 m_conf21 r/w undefined xxxxnab5h can message status register 21 m_stat21 r undefined xxxxnab6h can status set/clear register 21 sc_stat21 w 0000h xxxxnac4h can message data length register 22 m_dlc22 r/w undefined xxxxnac5h can message control r egister 22 m_ctrl22 r/w undefined xxxxnac6h can message time stamp register 22 m_time22 r/w undefined xxxxnac8h can message data register 220 m_data220 r/w undefined xxxxnac9h can message data register 221 m_data221 r/w undefined xxxxnacah can message data register 222 m_data222 r/w undefined xxxxnacbh can message data register 223 m_data223 r/w undefined xxxxnacch can message data register 224 m_data224 r/w undefined remark n = 2, 6, a, or e chapter 3 cpu function 89 user?s manual u14492ej4v1ud (11/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxnacdh can message data register 225 m_data225 r/w undefined xxxxnaceh can message data register 226 m_data226 r/w undefined xxxxnacfh can message data register 227 m_data227 r/w undefined xxxxnad0h can message id register l22 m_idl22 r/w undefined xxxxnad2h can message id register h22 m_idh22 r/w undefined xxxxnad4h can message configurat ion register 22 m_conf22 r/w undefined xxxxnad5h can message status register 22 m_stat22 r undefined xxxxnad6h can status set/clear register 22 sc_stat22 w 0000h xxxxnae4h can message data length register 23 m_dlc23 r/w undefined xxxxnae5h can message control r egister 23 m_ctrl23 r/w undefined xxxxnae6h can message time stamp register 23 m_time23 r/w undefined xxxxnae8h can message data register 230 m_data230 r/w undefined xxxxnae9h can message data register 231 m_data231 r/w undefined xxxxnaeah can message data register 232 m_data232 r/w undefined xxxxnaebh can message data register 233 m_data233 r/w undefined xxxxnaech can message data register 234 m_data234 r/w undefined xxxxnaedh can message data register 235 m_data235 r/w undefined xxxxnaeeh can message data register 236 m_data236 r/w undefined xxxxnaefh can message data register 237 m_data237 r/w undefined xxxxnaf0h can message id register l23 m_idl23 r/w undefined xxxxnaf2h can message id register h23 m_idh23 r/w undefined xxxxnaf4h can message configurat ion register 23 m_conf23 r/w undefined xxxxnaf5h can message status register 23 m_stat23 r undefined xxxxnaf6h can status set/clear register 23 sc_stat23 w 0000h xxxxnb04h can message data length register 24 m_dlc24 r/w undefined xxxxnb05h can message control r egister 24 m_ctrl24 r/w undefined xxxxnb06h can message time stamp register 24 m_time24 r/w undefined xxxxnb08h can message data register 240 m_data240 r/w undefined xxxxnb09h can message data register 241 m_data241 r/w undefined xxxxnb0ah can message data register 242 m_data242 r/w undefined xxxxnb0bh can message data register 243 m_data243 r/w undefined xxxxnb0ch can message data register 244 m_data244 r/w undefined xxxxnb0dh can message data register 245 m_data245 r/w undefined xxxxnb0eh can message data register 246 m_data246 r/w undefined xxxxnb0fh can message data register 247 m_data247 r/w undefined xxxxnb10h can message id register l24 m_idl24 r/w undefined remark n = 2, 6, a, or e chapter 3 cpu function 90 user?s manual u14492ej4v1ud (12/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxnb12h can message id register h24 m_idh24 r/w undefined xxxxnb14h can message configurat ion register 24 m_conf24 r/w undefined xxxxnb15h can message status register 24 m_stat24 r undefined xxxxnb16h can status set/clear register 24 sc_stat24 w 0000h xxxxnb24h can message data length register 25 m_dlc25 r/w undefined xxxxnb25h can message control r egister 25 m_ctrl25 r/w undefined xxxxnb26h can message time stamp register 25 m_time25 r/w undefined xxxxnb28h can message data register 250 m_data250 r/w undefined xxxxnb29h can message data register 251 m_data251 r/w undefined xxxxnb2ah can message data register 252 m_data252 r/w undefined xxxxnb2bh can message data register 253 m_data253 r/w undefined xxxxnb2ch can message data register 254 m_data254 r/w undefined xxxxnb2dh can message data register 255 m_data255 r/w undefined xxxxnb2eh can message data register 256 m_data256 r/w undefined xxxxnb2fh can message data register 257 m_data257 r/w undefined xxxxnb30h can message id register l25 m_idl25 r/w undefined xxxxnb32h can message id register h25 m_idh25 r/w undefined xxxxnb34h can message configurat ion register 25 m_conf25 r/w undefined xxxxnb35h can message status register 25 m_stat25 r undefined xxxxnb36h can status set/clear register 25 sc_stat25 w 0000h xxxxnb44h can message data length register 26 m_dlc26 r/w undefined xxxxnb45h can message control r egister 26 m_ctrl26 r/w undefined xxxxnb46h can message time stamp register 26 m_time26 r/w undefined xxxxnb48h can message data register 260 m_data260 r/w undefined xxxxnb49h can message data register 261 m_data261 r/w undefined xxxxnb4ah can message data register 262 m_data262 r/w undefined xxxxnb4bh can message data register 263 m_data263 r/w undefined xxxxnb4ch can message data register 264 m_data264 r/w undefined xxxxnb4dh can message data register 265 m_data265 r/w undefined xxxxnb4eh can message data register 266 m_data266 r/w undefined xxxxnb4fh can message data register 267 m_data267 r/w undefined xxxxnb50h can message id register l26 m_idl26 r/w undefined xxxxnb52h can message id register h26 m_idh26 r/w undefined xxxxnb54h can message configurat ion register 26 m_conf26 r/w undefined xxxxnb55h can message status register 26 m_stat26 r undefined xxxxnb56h can status set/clear register 26 sc_stat26 w 0000h remark n = 2, 6, a, or e chapter 3 cpu function 91 user?s manual u14492ej4v1ud (13/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxnb64h can message data length register 27 m_dlc27 r/w undefined xxxxnb65h can message control r egister 27 m_ctrl27 r/w undefined xxxxnb66h can message time stamp register 27 m_time27 r/w undefined xxxxnb68h can message data register 270 m_data270 r/w undefined xxxxnb69h can message data register 271 m_data271 r/w undefined xxxxnb6ah can message data register 272 m_data272 r/w undefined xxxxnb6bh can message data register 273 m_data273 r/w undefined xxxxnb6ch can message data register 274 m_data274 r/w undefined xxxxnb6dh can message data register 275 m_data275 r/w undefined xxxxnb6eh can message data register 276 m_data276 r/w undefined xxxxnb6fh can message data register 277 m_data277 r/w undefined xxxxnb70h can message id register l27 m_idl27 r/w undefined xxxxnb72h can message id register h27 m_idh27 r/w undefined xxxxnb74h can message configurat ion register 27 m_conf27 r/w undefined xxxxnb75h can message status register 27 m_stat27 r undefined xxxxnb76h can status set/clear register 27 sc_stat27 w 0000h xxxxnb84h can message data length register 28 m_dlc28 r/w undefined xxxxnb85h can message control r egister 28 m_ctrl28 r/w undefined xxxxnb86h can message time stamp register 28 m_time28 r/w undefined xxxxnb88h can message data register 280 m_data280 r/w undefined xxxxnb89h can message data register 281 m_data281 r/w undefined xxxxnb8ah can message data register 282 m_data282 r/w undefined xxxxnb8bh can message data register 283 m_data283 r/w undefined xxxxnb8ch can message data register 284 m_data284 r/w undefined xxxxnb8dh can message data register 285 m_data285 r/w undefined xxxxnb8eh can message data register 286 m_data286 r/w undefined xxxxnb8fh can message data register 287 m_data287 r/w undefined xxxxnb90h can message id register l28 m_idl28 r/w undefined xxxxnb92h can message id register h28 m_idh28 r/w undefined xxxxnb94h can message configurat ion register 28 m_conf28 r/w undefined xxxxnb95h can message status register 28 m_stat28 r undefined xxxxnb96h can status set/clear register 28 sc_stat28 w 0000h xxxxnba4h can message data length register 29 m_dlc29 r/w undefined xxxxnba5h can message control r egister 29 m_ctrl29 r/w undefined xxxxnba6h can message time stamp register 29 m_time29 r/w undefined xxxxnba8h can message data register 290 m_data290 r/w undefined remark n = 2, 6, a, or e chapter 3 cpu function 92 user?s manual u14492ej4v1ud (14/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxnba9h can message data register 291 m_data291 r/w undefined xxxxnbaah can message data register 292 m_data292 r/w undefined xxxxnbabh can message data register 293 m_data293 r/w undefined xxxxnbach can message data register 294 m_data294 r/w undefined xxxxnbadh can message data register 295 m_data295 r/w undefined xxxxnbaeh can message data register 296 m_data296 r/w undefined xxxxnbafh can message data register 297 m_data297 r/w undefined xxxxnbb0h can message id register l29 m_idl29 r/w undefined xxxxnbb2h can message id register h29 m_idh29 r/w undefined xxxxnbb4h can message configurat ion register 29 m_conf29 r/w undefined xxxxnbb5h can message status register 29 m_stat29 r undefined xxxxnbb6h can status set/clear register 29 sc_stat29 w 0000h xxxxnbc4h can message data length register 30 m_dlc30 r/w undefined xxxxnbc5h can message control r egister 30 m_ctrl30 r/w undefined xxxxnbc6h can message time stamp register 30 m_time30 r/w undefined xxxxnbc8h can message data register 300 m_data300 r/w undefined xxxxnbc9h can message data register 301 m_data301 r/w undefined xxxxnbcah can message data register 302 m_data302 r/w undefined xxxxnbcbh can message data register 303 m_data303 r/w undefined xxxxnbcch can message data register 304 m_data304 r/w undefined xxxxnbcdh can message data register 305 m_data305 r/w undefined xxxxnbceh can message data register 306 m_data306 r/w undefined xxxxnbcfh can message data register 307 m_data307 r/w undefined xxxxnbd0h can message id register l30 m_idl30 r/w undefined xxxxnbd2h can message id register h30 m_idh30 r/w undefined xxxxnbd4h can message configurat ion register 30 m_conf30 r/w undefined xxxxnbd5h can message status register 30 m_stat30 r undefined xxxxnbd6h can status set/clear register 30 sc_stat30 w 0000h xxxxnbe4h can message data length register 31 m_dlc31 r/w undefined xxxxnbe5h can message control r egister 31 m_ctrl31 r/w undefined xxxxnbe6h can message time stamp register 31 m_time31 r/w undefined xxxxnbe8h can message data register 310 m_data310 r/w undefined xxxxnbe9h can message data register 311 m_data311 r/w undefined xxxxnbeah can message data register 312 m_data312 r/w undefined xxxxnbebh can message data register 313 m_data313 r/w undefined xxxxnbech can message data register 314 m_data314 r/w undefined remark n = 2, 6, a, or e chapter 3 cpu function 93 user?s manual u14492ej4v1ud (15/15) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits initial value xxxxnbedh can message data register 315 m_data315 r/w undefined xxxxnbeeh can message data register 316 m_data316 r/w undefined xxxxnbefh can message data register 317 m_data317 r/w undefined xxxxnbf0h can message id register l31 m_idl31 r/w undefined xxxxnbf2h can message id register h31 m_idh31 r/w undefined xxxxnbf4h can message configurat ion register 31 m_conf31 r/w undefined xxxxnbf5h can message status register 31 m_stat31 r undefined xxxxnbf6h can status set/clear register 31 sc_stat31 w 0000h xxxxnc00h can interrupt pending register ccintp r 0000h xxxxnc02h can global interrupt pending register cgintp r/w 0000h xxxxnc04h can1 interrupt pending register c1intp r/w 0000h xxxxnc0ch can stop register cstop r/w 0000h xxxxnc10h can global status register cgst r/w 0100h xxxxnc12h can global interrupt enable register cgie r/w 0a00h xxxxnc14h can main clock selection register cgcs r/w 7f05h xxxxnc18h can time stamp count register cgtsc r 0000h can message search start register cgmss w 0000h xxxxnc1ah can message search result register cgmsr r 0000h xxxxnc40h can1 address mask 0 register l c1maskl0 r/w undefined xxxxnc42h can1 address mask 0 register h c1maskh0 r/w undefined xxxxnc44h can1 address mask 1 register l c1maskl1 r/w undefined xxxxnc46h can1 address mask 1 register h c1maskh1 r/w undefined xxxxnc48h can1 address mask 2 register l c1maskl2 r/w undefined xxxxnc4ah can1 address mask 2 register h c1maskh2 r/w undefined xxxxnc4ch can1 address mask 3 register l c1maskl3 r/w undefined xxxxnc4eh can1 address mask 3 register h c1maskh3 r/w undefined xxxxnc50h can1 control register c1ctrl r/w 0101h xxxxnc52h can1 definition register c1def r/w 0000h xxxxnc54h can1 information register c1last r 00ffh xxxxnc56h can1 error count register c1erc r 0000h xxxxnc58h can1 interrupt enable register c1ie r/w 0900h xxxxnc5ah can1 bus active register c1ba r 00ffh can1 bit rate prescaler register c1brp r/w 0000h xxxxnc5ch can1 bus diagnostic information register c1dinf r 0000h xxxxnc5eh can1 synchronization control register c1sync r/w 0218h remark n = 2, 6, a, or e chapter 3 cpu function 94 user?s manual u14492ej4v1ud 3.4.10 specific registers specific registers are registers that are protected from being written with ill egal data due to inadvertent program loop (runaway), etc. the v850e/ia1 has three specific re gisters, the power save control register (psc) (refer to 8.5.2 (13) power save control register (psc) ), clock control register (ckc) (refer to 8.3.4 clock control register (ckc) ), and flash programming mode control register (flpmc) (refer to 16.7.12 flash programming mode control register (flpmc) ). 3.4.11 system wait control register (vswc) set the value shown below to this register. this register can be read/written in 8-bit uni ts (address: fffff06eh, initial value: 77h). remark if the timing of changing the flag or count value conf licts with the timing of accessing a register when a register including a status flag that indicates the status of an on-chip peripheral function (such as asif0) or a register indicating the count value of a timer (such as tm0n) is accessed, a register access retry operation is performed. as a result, a longer time may be required to access the on-chip peripheral i/o register. register name set value note system wait control register (vswc) 12h timer 1/timer 2 clock selection register (prm02) 00h or 01h note set vswc = 15h and prm02 = 00h only when the tesne1 and tesne0 bits = 11b and the csen2 to csen0 bits = 000b in timer 2 count clock/control edge selection register 0 (cse0). 3.4.12 cautions when using the v850e/ia1, the following regi sters must be set from the beginning. ? system wait control register (vswc) (see 3.4.11 system wait control register (vswc) ) ? clock control register (ckc) (see 8.3.4 clock control register (ckc) ) after setting vswc and ckc, set other registers as required. 95 user?s manual u14492ej4v1ud chapter 4 bus control function the v850e/ia1 is provided with an exte rnal bus interface function by whic h external i/o and memories, such as rom and ram, can be connected. 4.1 features 16-bit/8-bit data bus sizing function 8-space chip select function wait function programmable wait function, through which up to 7 wait states can be inserted for each memory block external wait function via wait pin idle state insertion function bus hold function external device connection enabled via bus control/port alternate function pins 4.2 bus control pins the following pins are used for connection to external devices. bus control pin (function when in control mode) func tion when in port mode register for port/control mode switching address/data bus (ad0 to ad15) pdl0 to pdl15 (port dl) pmcdl address bus (a16 to a23) pdh0 to pdh7 (port dh) pmcdh chip select (cs0 to cs7) pcs0 to pcs7 (port cs) pmccs read/write control (lwr/uwr, rd, astb) pct0, pct1, pct4, pct6 (port ct) pmcct external wait control (wait) pcm0 (port cm) internal system clock (clkout) pcm1 (port cm) bus hold control (hldrq, hldak) pcm2, pcm3 (port cm) pmccm remark in the case of single-chip mode 1 and romless mo des 0 and 1, when the system is reset, each bus control pin becomes unconditionally valid. 4.2.1 pin status during internal rom, in ternal ram, and on-chip peripheral i/o access when the internal rom and ram are accessed, both the address bus and address/data bus become undefined. the external bus control signal becomes inactive. when on-chip peripheral i/o are accessed, both the address bus an d address/data bus output the addresses of the on-chip peripheral i/o currently being acce ssed. no data is output. the external bus control signal becomes inactive. chapter 4 bus control function 96 user?s manual u14492ej4v1ud 4.3 memory block function the 256 mb memory space is divided into memory bloc ks of 2 mb and 64 mb units. the programmable wait function and bus cycle operat ion mode can be indep endently controlled for each block. the area that can be used as progr am area is the 64 mb space of addresses 0000000h to 3ffffffh. fffffffh fffffffh on-chip peripheral i/o area (4 kb) internal ram area (12 kb note 1 ) external memory area external memory area fffc000h fe00000h fdfffffh ffff000h fffefffh fc00000h fbfffffh fa00000h f9fffffh f800000h f7fffffh c000000h bffffffh 8000000h 7ffffffh 4000000h 3ffffffh 0800000h 07fffffh 0600000h 05fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h block 1 (2 mb) block 0 (2 mb) block 2 (2 mb) block 3 (2 mb) 64 mb 64 mb block 5 (2 mb) block 6 (2 mb) block 4 (2 mb) block 7 (2 mb) 3ffffffh on-chip peripheral i/o area (4 kb) note 2 internal ram area (12 kb note 1 ) 3ffc000h 3fff000h 3ffefffh 00fffffh internal rom area (1 mb) note 3 0000000h cs7, cs6, cs5 area 3 area 2 area 1 area 0 cs6 cs4 cs1 cs3 cs2, cs1, cs0 notes 1. physical internal ram: 10 kb 2. access to this area is prohibited. to access the on-chip peripheral i/o in this area, specify addresses ffff000h to fffffffh. 3. when in single-chip mode 1 and romless modes 0 and 1, this becomes an external memory area. when in single-chip mode 1, addresses 010 0000h to 01fffffh become an internal rom area. chapter 4 bus control function 97 user?s manual u14492ej4v1ud 4.3.1 chip select control function of the 256 mb memory area, the lower 8 mb (00000 00h to 07fffffh) and the hi gher 8 mb (f800000h to fffffffh) can be divided into 2 mb memory blocks by chip area selection control regi sters 0 and 1 (csc0, csc1) to control the chip select signal. the memory area can be effectively used by dividing it into memory blocks using the chip select control function. the priority order is described below. (1) chip area selection control registers 0, 1 (csc0, csc1) these registers can be read/written in 16-bit units and become valid by setting each bit to 1. if different chip select signal outputs are set to the sa me block, the priority order is controlled as follows. csc0: cs0 > cs2 > cs1 csc1: cs7 > cs5 > cs6 if both the cs0m and cs2m bits of the csc0 register ar e set to 0, cs1 is output to the corresponding block (m = 0 to 3). similarly, if both the cs5m and cs 7m bits of the csc1 register are set to 0, cs6 is output to the corresponding block (m = 0 to 3). caution write to the csc0 and csc1 registers afte r reset, and then do not change the set values. chapter 4 bus control function 98 user?s manual u14492ej4v1ud 15 cs33 csc0 address fffff060h initial value 2c11h 14 cs32 13 cs31 12 cs30 11 cs23 10 cs22 9 cs21 8 cs20 7 cs13 6 cs12 5 cs11 4 cs10 3 cs03 2 cs02 1 cs01 0 cs00 15 cs43 csc1 address fffff062h initial value 2c11h 14 cs42 13 cs41 12 cs40 11 cs53 10 cs52 9 cs51 8 cs50 7 cs63 6 cs62 5 cs61 4 cs60 3 cs73 2 cs72 1 cs71 0 cs70 bit position bit name function chip select enabled by setting csnm bit to 1. csnm cs operation cs00 cs0 output during block 0 access cs01 cs0 output during block 1 access cs02 cs0 output during block 2 access cs03 cs0 output during block 3 access cs10 to cs13 note 1 cs20 cs2 output during block 0 access cs21 cs2 output during block 1 access cs22 cs2 output during block 2 access cs23 cs2 output during block 3 access cs30 to cs33 note 2 cs40 to cs43 note 3 cs50 cs5 output during block 7 access cs51 cs5 output during block 6 access cs52 cs5 output during block 5 access cs53 cs5 output during block 4 access cs60 to cs63 note 4 cs70 cs7 output during block 7 access cs71 cs7 output during block 6 access cs72 cs7 output during block 5 access cs73 cs7 output during block 4 access 15 to 0 csnm (n = 0 to 7) (m = 0 to 3) notes 1. if both the cs0m and cs2m bits have been set to 0, if area 0 is acce ssed, cs1 will be output regardless of the setting of the cs1m bit. 2. when area 1 is accessed, cs3 will be output regardless of the setting of the cs3m bit. 3. when area 2 is accessed, cs4 will be output regardless of the setting of the cs4m bit. 4. if both the cs5m and cs7m bits have been set to 0, if area 3 is acce ssed, cs6 will be output regardless of the setting of the cs6m bit. chapter 4 bus control function 99 user?s manual u14492ej4v1ud the following diagram shows the cs signal, which is en abled for area 0 when the csc0 register is set to 0703h. when the csc0 register is set to 0703h, cs0 and cs2 ar e output to block 0 and block 1, but since cs0 has priority over cs2, cs0 is output if the addr esses of block 0 and block 1 are accessed. if the address of block 3 is accessed, both the cs03 an d cs23 bits of the csc0 register are 0, and cs1 is output. figure 4-1. example when cs c0 register is set to 0703h 3ffffffh 0600000h 05fffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h block 2 (2 mb) block 3 (2 mb) block 1 (2 mb) block 0 (2 mb) cs1 is output. cs2 is output. cs0 is output. 58 mb 2 mb 4 mb chapter 4 bus control function 100 user?s manual u14492ej4v1ud 4.4 bus cycle type control function in the v850e/ia1, the following external devices c an be connected directly to each memory block. ? sram, external rom, external i/o connected external devices are spec ified by bus cycle type c onfiguration regi sters 0, 1 (bct0, bct1). (1) bus cycle type configuration registers 0, 1 (bct0, bct1) these registers can be read/written in 16-bit units. caution write to the bct0 and bct1 registers after reset, and then do not change the set values. also, do not access an external memory area other than the one for this in itialization routine until the initial setting of the bct0 and bct1 registers is complete. however, it is possible to access external memory areas whose initial settings are complete. 15 me3 bct0 csn signal address fffff480h initial value cccch 14 11 00 13 12 11 me2 10 9 00 00 87 me1 6 1 543 me0 2 1 1 00 0 cs3 cs2 cs1 cs0 15 me7 bct1 csn signal address fffff482h initial value cccch 14 1 13 00 00 12 11 me6 10 1 987 me5 6 1 5 00 00 43 me4 2 1 10 cs6 cs5 cs4 cs7 bit position bit name function sets memory controller operation enable for each chip select note . men memory controller operation enable 0 operation disabled 1 operation enabled 15, 11, 7, 3 (bct0), 15, 11, 7, 3 (bct1) men (n = 0 to 7) note set the bct1.me6 and bct1.me5 bits to 11b (operation enable) when an external memory is connected to the cs5 area or cs6 area. set the pmccs register to x01xxxxxb when only cs 5 is connected to the external memory and cs6 is used as a port (pcs6), and set the pmccs regi ster to x10xxxxxb when only cs6 is connected to the external memory and cs5 is used as a port (pcs5). chapter 4 bus control function 101 user?s manual u14492ej4v1ud 4.5 bus access 4.5.1 number of access clocks the number of basic clocks required to access each resource is shown below. bus cycle status resource (bus width) instruction fetch operand data access internal rom (32 bits) 1 note 1 5 internal ram (32 bits) 1 note 2 1 on-chip peripheral i/o (16 bits) ? 5 note 3 programmable peripheral i/o ? 5 note 3 external memory (16 bits) 3 note 3 3 note 3 notes 1. this value is 2 in the case of instruction branch 2. this value is 2 if there is contention with data access. 3. min. value remark unit: clock/access chapter 4 bus control function 102 user?s manual u14492ej4v1ud 4.5.2 bus sizing function the bus sizing function controls the dat a bus width for each cs space. the data bus width is specified by using the bus size configuration register (bsc). (1) bus size configuration register (bsc) this register can be read/ written in 16-bit units. cautions 1. write to the bsc register after reset, and then do not change th e set values. also, do not access an external memory area other than the one for this initialization routine until the initial setting of the bsc register is complete. however, it is possible to access external memory areas who se initial settings are complete. 2. when the data bus width is specified as 8 bits, only the signals shown below become active. lwr: when accessing sram, external rom, or external i/o (write cycle) 15 0 bsc csn signal address fffff066h initial value note 0000h/5555h 14 bs70 13 0 12 bs60 11 0 10 bs50 9 0 8 bs40 7 0 6 bs30 5 0 4 bs20 3 0 2 bs10 1 0 0 bs00 cs3 cs2 cs1 cs0 cs4 cs5 cs6 cs7 note when in single-chip mode 0, 1: 5555h when in romless mode 0: 5555h when in romless mode 1: 0000h bit position bit name function sets the data bus width of csn space. bsn0 data bus width of csn space 0 8 bits 1 16 bits 14, 12, 10, 8, 6, 4, 2, 0 bsn0 (n = 0 to 7) 4.5.3 word data processing format the word data in memory can be processed using the littl e endian method for cs space selected with a chip select signal (cs0 to cs7). chapter 4 bus control function 103 user?s manual u14492ej4v1ud 4.5.4 bus width the v850e/ia1 accesses on-chip peripheral i/o and external memory in 8-bit, 16-bi t, or 32-bit units. the following shows the operation for each type of access. access all data in order starting from the lower side. (1) byte access (8 bits) (a) when the data bus width is 16 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 byte data 15 8 external data bus 2n + 1 address (b) when the data bus width is 8 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data external data bus 2n address 7 0 7 0 byte data external data bus 2n + 1 address chapter 4 bus control function 104 user?s manual u14492ej4v1ud (2) halfword access (16 bits) (a) when the data bus width is 16 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus 2n address 15 8 2n + 1 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 2 address 2n (b) when the data bus width is 8 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus address 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 2n 7 0 7 0 halfword data 15 8 external data bus address 7 0 7 0 halfword data 15 8 external data bus 2n + 2 address 2n + 1 chapter 4 bus control function 105 user?s manual u14492ej4v1ud (3) word access (32 bits) (a) when the data bus width is 16 bits (little endian) (1/2) <1> access to address (4n) 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 <2> access to address (4n + 1) 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 23 16 31 24 chapter 4 bus control function 106 user?s manual u14492ej4v1ud (a) when the data bus width is 16 bits (little endian) (2/2) <3> access to address (4n + 2) 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 4n + 5 23 16 31 24 <4> access to address (4n + 3) 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 4n + 5 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 6 address 15 8 23 16 31 24 chapter 4 bus control function 107 user?s manual u14492ej4v1ud (b) when the data bus width is 8 bits (little endian) (1/2) <1> access to address (4n) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 <2> access to address (4n + 1) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 chapter 4 bus control function 108 user?s manual u14492ej4v1ud (b) when the data bus width is 8 bits (little endian) (2/2) <3> access to address (4n + 2) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 <4> access to address (4n + 3) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 6 address 15 8 23 16 31 24 chapter 4 bus control function 109 user?s manual u14492ej4v1ud 4.6 wait function 4.6.1 programmable wait function (1) data wait control registers 0, 1 (dwc0, dwc1) to facilitate interfacing with low-speed memory or with i/os , it is possible to insert up to 7 data wait states in the starting bus cycle for each cs space. the number of wait states can be specified by program using data wait control registers 0 and 1 (dwc0, dwc1). just after system reset, all blo cks have 3 data wait states inserted. these registers can be read/written in 16-bit units. cautions 1. the internal rom area and internal ram area are not subject to programmable waits and ordinarily no wait access is carried out. the on- chip peripheral i/o area is also not subject to programmable wait states, with wait control performed by each peripheral function only. 2. write to the dwc0 and dwc1 register s after reset, and then do not change the set values. also, do not access an external memory area ot her than the one for this initialization routine until the initial set ting of the dwc0 and dwc1 registers is complete. however, it is possible to a ccess external memory areas whose initial settings are complete. 15 dwc0 csn signal address fffff484h initial value 3333h 14131211109876543210 0 dw32 dw31 dw30 0 dw22 dw21 dw20 0 dw12 dw11 dw10 0 dw02 dw01 dw00 0 dw72 dw71 dw70 0 dw62 dw61 dw60 0 dw52 dw51 dw50 0 dw42 dw41 dw40 cs3 cs2 cs1 cs0 cs7 cs6 cs5 cs4 15 dwc1 csn signal address fffff486h initial value 3333h 14131211109876543210 bit position bit name function specifies the number of wait states inserted in the csn space. dwn2 dwn1 dwn0 number of wait states inserted in csn space 0 0 0 not inserted 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 14 to 12, 10 to 8, 6 to 4, 2 to 0 dwn2 to dwn0 (n = 0 to 7) chapter 4 bus control function 110 user?s manual u14492ej4v1ud (2) address wait cont rol register (awc) in the v850e/ia1, address setup wait and address hold wa it states can be inserted before and after the t1 cycle, respectively. these wait states can be set for eac h cs space via the awc register. this register can be read/written in 16-bit units. caution write to the awc register after reset , and then do not change the set values. cs4 cs0 awc csn signal 15 ahw7 14 asw7 13 ahw6 12 asw6 11 ahw5 10 asw5 9 ahw4 8 asw4 7 ahw3 6 asw3 5 ahw2 4 asw2 3 ahw1 2 asw1 1 ahw0 0 asw0 address fffff488h initial value 0000h cs7 cs6 cs5 cs3 cs2 cs1 bit position bit name function 15, 13, 11, 9, 7, 5, 3, 1 ahwn (n = 0 to 7) sets the insertion of an address hold wait state in each csn space after the t1 cycle. 0: address hold wait state not inserted 1: address hold wait state inserted 14, 12, 10, 8, 6, 4, 2, 0 aswn (n = 0 to 7) sets the insertion of an address setup wait state in each csn space before the t1 cycle. 0: address setup wait state not inserted 1: address setup wait state inserted chapter 4 bus control function 111 user?s manual u14492ej4v1ud 4.6.2 external wait function when an extremely slow device, i/o, or asynchronous system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (wait) for synchronization with the external device. just as with programmable waits, acce ssing internal rom, internal ram, and on-chip peripheral i/o areas cannot be controlled by external waits. the external wait signal can be input asynchronously to clkout and is sampled at the falling edge of the clkout signal in the t2 and tw states of a bus cycle. if the setup/hold time in the samp ling timing is not satisfied, the wait state may or may not be inserted in the next state. 4.6.3 relationship between programm able wait and external wait a wait cycle is inserted as the result of an or operation between the wait cycle specifi ed by the set value of the programmable wait and t he wait cycle controlled by the wait pin. wait control programmable wait wait by wait pin for example, if the timings of the pr ogrammable wait and the wait pin signal are as illustrated below, three wait states will be inserted in the bus cycle. figure 4-2. example of wait insertion clkout wait pin wait by wait pin programmable wait wait control t2 tw tw tw t3 remark the circles indicate the sampling timing. chapter 4 bus control function 112 user?s manual u14492ej4v1ud 4.7 idle state insertion function to facilitate interfacing with low-speed memory devices, a set number of idle states (ti) can be inserted into the starting bus cycle after the t3 state to se cure the data output float delay time (t df ) of the memory when each cs space is read accessed. the bus cycl e following the t3 state starts after the inserted idle state(s). idle states are inserted at the following timing. ? after the read cycle for sram, external i/o, or external rom. the idle state insertion setting can be specified using the bus cycle control register (bcc). idle state insertion is automatically programmed for all memory blocks immediately after a system reset. (1) bus cycle control register (bcc) this register can be read/ written in 16-bit units. cautions 1. idle states cannot be inserted in internal rom, intern al ram, on-chip peripheral i/o, or programmable peri pheral i/o areas. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area other than the one for this initialization routine until the initial setting for this register is co mplete. however, it is possible to access external memory areas whose in itial settings are complete. cs4 cs0 bcc csn signal 15 bc71 14 0 0 00 0000 13 bc61 12 11 bc51 10 9 bc41 87 bc31 65 bc21 43 bc11 2 1 bc01 0 address fffff48ah initial value aaaah cs7 cs6 cs5 cs3 cs2 cs1 bit position bit name function 15, 13, 11, 9, 7, 5, 3, 1 bcn1 (n = 0 to 7) specifies the insertion of idle states after the t3 state in each csn space. 0: idle state not inserted 1: idle state inserted chapter 4 bus control function 113 user?s manual u14492ej4v1ud 4.8 bus hold function 4.8.1 function outline if pins pcm2 and pcm3 are specified in the contro l mode, the hldak and hldrq functions become valid. if it is determined that the hldrq pin has become active (low level) as a bus mastership request from another bus master, the external address/data bus and each strobe pin ar e shifted to high impedance and then released (bus hold state). if the hldrq pin becomes inactive (high level) an d the bus mastership request is canceled, driving of these pins begins again. during the bus hold period, the internal operations of t he v850e/ia1 continue until the external memory or on-chip peripheral i/o register is accessed. the bus hold state can be known by the hldak pin becoming active (low level). the period from when the hldrq pin becomes active (low level) to when the hldak pin becomes acti ve (low level) is at least 2 clocks. in a multiprocessor configurati on, etc., a system with multiple bus masters can be configured. 4.8.2 bus hold procedure the procedure of the bus hold function is illustrated below. <1> hldrq = 0 accepted <2> all bus cycle start requests held pending <3> end of current bus cycle <4> transition to bus idle state <5> hldak = 0 <6> hldrq = 1 accepted <7> hldak = 1 <8> releases pending bus cycle start request <9> start of bus cycle normal state bus hold state normal state hldak (output) hldrq (input) <1> <2> <3><4> <5> <6> <7><8><9> chapter 4 bus control function 114 user?s manual u14492ej4v1ud 4.8.3 operation in power save mode in the software stop or idle mode, the internal system clock is stopped. consequently , the bus hold state is not accepted and set since the hldrq pin cannot be accepted even if it becomes active. in the halt mode, the hldak pin immediately becomes active when the hldrq pin becomes active, and the bus hold state is set. when the hldrq pin becomes inactive a fter that, the hldak pin also becomes inactive. as a result, the bus hold state is cleared and the halt mode is set again. 4.8.4 bus hold timing t2 t3 th th th th ti t1 clkout (output) hldrq (input) hldak (output) a16 to a23 (output) ad0 to ad15 (i/o) astb (output) rd (output) lwr, uwr (output) csn (output) wait (input) address address undefined data address address undefined remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7 chapter 4 bus control function 115 user?s manual u14492ej4v1ud 4.9 bus priority order there are four external bus cycles: bus hold, dm a cycle, operand data access, and instruction fetch. in order of priority, bus hold is the highest, followed by dma cycle, operand data access, and instruction fetch, in that order. an instruction fetch may be inserted between a read acce ss and write access during a read modify write access. also, an instruction fetch may be inserted between bus accesses when the cpu bus is locked. table 4-1. bus priority order priority order external bus cycle bus master high bus hold external device dma cycle dma controller operand data access cpu low instruction fetch cpu 4.10 boundary operation conditions 4.10.1 program space (1) branching to the on-chip peripheral i/o area or successive fetches from the internal ram area to the on-chip peripheral i/o area are prohibited. if the above is performed (branc hing or successive fe tch), a data to be fetched is undefined and the o peration is not guaranteed. (2) if a branch instruction exists at the upper limit of the internal ram area, a prefetch operation (invalid fetch) that straddles over the on-chip peripheral i/o area does not occur. 4.10.2 data space the v850e/ia1 is provided with an address misalign function. through this function, regardless of the data format (wor d data or halfword data), data can be allocated to all addresses. however, in the case of word data and halfword data, if the data is not s ubject to boundary alignment, the bus cycle will be generated at least 2 times and bus efficiency will drop. (1) in the case of halfword-length data access when the address?s lsb is 1, the byte-len gth bus cycle will be generated 2 times. (2) in the case of word-length data access (a) when the address?s lsb is 1, bus cycles will be generated in the order of byte-length bus cycle, halfword-length bus cycle, an d byte-length bus cycle. (b) when the address?s lowest 2 bits are 10, the halfword-length bus cycle will be generated 2 times. 116 user?s manual u14492ej4v1ud chapter 5 memory ac cess control function 5.1 sram, external rom, external i/o interface 5.1.1 features sram is accessed in a minimum of 2 states. a maximum of 7 programmable data wait states can be inserted according to dwc0 and dwc1 register settings. data waits can be controlled by wait pin input. an idle state (1 state) can be inserted afte r a read/write cycle by setting the bcc register. an address hold wait state or address setup wait state can be inserted by setting the awc register. chapter 5 memory access control function 117 user?s manual u14492ej4v1ud 5.1.2 sram, external rom, external i/o access figure 5-1. sram, external rom, external i/o access timing (1/5) (a) on a read (1 wait insertion) t1 t2 tw t3 address data h clkout (output) a16 to a23 (output) ad0 to ad15 (i/o) astb (output) rd (output) uwr, lwr (output) csn (output) wait (input) address remarks 1. the circles indicate the sampling timing. 2. broken lines indicate high impedance. 3. n = 0 to 7 chapter 5 memory access control function 118 user?s manual u14492ej4v1ud figure 5-1. sram, external rom, external i/o access timing (2/5) (b) on a read (0 wait, address setup wait, address hold wait state insertion) tasw t1 tahw address address t2 t3 data h clkout (output) a16 to a23 (output) ad0 to ad15 (i/o) astb (output) rd (output) uwr, lwr (output) csn (output) wait (input) remarks 1. the circles indicate the sampling timing. 2. broken lines indicate high impedance. 3. n = 0 to 7 chapter 5 memory access control function 119 user?s manual u14492ej4v1ud figure 5-1. sram, external rom, external i/o access timing (3/5) (c) on a write (1 wait insertion) t1 t2 tw t3 address data note h clkout (output) a16 to a23 (output) ad0 to ad15 (i/o) astb (output) rd (output) uwr, lwr (output) csn (output) wait (input) address note ad0 to ad7 output invalid data when accessed to odd-numbered address byte data. ad8 to ad15 output invalid data when acce ssed to even-numbered address byte data. remarks 1. the circles indicate the sampling timing. 2. broken lines indicate high impedance. 3. n = 0 to 7 chapter 5 memory access control function 120 user?s manual u14492ej4v1ud figure 5-1. sram, external rom, external i/o access timing (4/5) (d) on a write (0 wait insertion, for 8-bit data bus) t1 t2 t3 address address address h clkout (output) a16 to a23 (output) ad8 to ad15 (i/o) ad0 to ad7 (i/o) astb (output) rd (output) uwr, lwr (output) csn (output) wait (input) data note note ad0 to ad7 output invalid data when accessed to odd-numbered address byte data. remarks 1. the circles indicate the sampling timing. 2. broken lines indicate high impedance. 3. n = 0 to 7 chapter 5 memory access control function 121 user?s manual u14492ej4v1ud figure 5-1. sram, external rom, external i/o access timing (5/5) (e) bus hold timing t2 note 1 address undefined note 2 address undefined t3 th th th th ti t1 clkout (output) a16 to a23 (output) ad0 to ad15 (i/o) hldak (output) astb (output) rd (output) uwr, lwr (output) csn (output) hldrq (input) wait (input) undefined notes 1. on a read: undefined on a write: address 2. on a read: data on a write: undefined remarks 1. the circles indicate the sampling timing. 2. broken lines indicate high impedance. 3. n = 0 to 7 122 user?s manual u14492ej4v1ud chapter 6 dma functions (dma controller) the v850e/ia1 includes a direct memory access (dma) c ontroller (dmac) that ex ecutes and controls dma transfer. the dmac controls data transf er between memory and i/o, among memories or among i/os, based on dma requests issued by the on-chip peripheral i/o (such as se rial interface, real-time puls e unit, and a/d converter), or software triggers (memory refers to in ternal ram or external memory). 6.1 features 4 independent dma channels transfer units: 8/16 bits maximum transfer count: 65,536 (2 16 ) transfer type: two-cycle transfer three transfer modes single transfer mode single-step transfer mode block transfer mode transfer requests request by interrupts from on-chip peripheral i/o (such as serial inte rface, real-time pulse unit, a/d converter) requests by software trigger transfer objects memory ? i/o memory ? memory i/o ? i/o next address setting function chapter 6 dma functions (dma controller) 123 user?s manual u14492ej4v1ud 6.2 configuration cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850e/ia1 bus interface external bus external ram external rom external i/o dma source address register (dsanh/dsanl) dma transfer count register (dbcn) dma channel control register (dchcn) dma destination address register (ddanh/ddanl) dma addressing control register (dadcn) dma disable status register (ddis) dma trigger factor register n (dtfrn) dma restart register (drst) remark n = 0 to 3 chapter 6 dma functions (dma controller) 124 user?s manual u14492ej4v1ud 6.3 control registers 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) these registers are used to set the dma source addresses (28 bits each) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, dsanh and dsanl. since these registers are 2-stage fifo buffer registers, a new source address for dma transfer can be specified during dma transfer (refer to 6.9 next address setting function ). in this case, if a new dsan register is set, the value set will be transferred to the slave register and en abled only if dma transfer ends normally, and the tcn bit of dma channel control register n (dchcn) has been set to 1 or the initn bit of the dchcn register has been set to 1 (n = 0 to 3). (1) dma source address registers 0h to 3h (dsa0h to dsa3h) these registers can be read/written in 16-bit units. be sure to set bits 12 to 14 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. when setting an addr ess of an on-chip peripheral i/o regi ster for the source address, be sure to specify an addr ess between ffff000h and fffffffh . an address of the on- chip peripheral i/o register image (3fff 000h to 3ffffffh) must not be specified. 2. do not set the dsanh register wh en dma transfer has been suspended. 15 ir dsa0h address fffff082h initial value undefined 14 0 13 0 12 0 11 sa27 10 sa26 9 sa25 8 sa24 7 sa23 6 sa22 5 sa21 4 sa20 3 sa19 2 sa18 1 sa17 0 sa16 ir dsa1h fffff08ah undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 ir dsa2h fffff092h undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 ir dsa3h fffff09ah undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 bit position bit name function 15 ir specifies the dma source address. 0: external memory, on-chip peripheral i/o 1: internal ram 11 to 0 sa27 to sa16 sets the dma source addresses (a27 to a16). during dma transfer, it stores the next dma transfer source address. chapter 6 dma functions (dma controller) 125 user?s manual u14492ej4v1ud (2) dma source address registers 0l to 3l (dsa0l to dsa3l) these registers can be read/written in 16-bit units. 15 sa15 dsa0l address fffff080h initial value undefined 14 sa14 13 sa13 12 sa12 11 sa11 10 sa10 9 sa9 8 sa8 7 sa7 6 sa6 5 sa5 4 sa4 3 sa3 2 sa2 1 sa1 0 sa0 sa15 dsa1l fffff088h undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa15 dsa2l fffff090h undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa15 dsa3l fffff098h undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 bit position bit name function 15 to 0 sa15 to sa0 sets the dma source addresses (a15 to a0). during dma transfer, it stores the next dma transfer source address. chapter 6 dma functions (dma controller) 126 user?s manual u14492ej4v1ud 6.3.2 dma destination address regi sters 0 to 3 (dda0 to dda3) these registers are used to set the dma destination address (28 bits each) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, ddanh and ddanl. since these registers are 2-stage fifo buffer register s, a new destination address for dma transfer can be specified during dma transfer (refer to 6.9 next address setting function ). in this case, if a new ddan register is set, the value set will be transferred to the slave register and enabled only if dma transfer ends normally, and the tcn bit of dma channel control register n (dchcn) has been set to 1 or the initn bit of the dchcn register has been set to 1 (n = 0 to 3). (1) dma destination address register s 0h to 3h (dda0h to dda3h) these registers can be read/written in 16-bit units. be sure to set bits 12 to 14 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. when setting an address of an on- chip peripheral i/o regist er for the destination address, be sure to specify an addres s between ffff000h and fffffffh. an address of the on-chip peripheral i/o register image (3fff000h to 3ffffffh) must not be specified. 2. do not set the ddanh register when dma transfer has been suspended. 15 ir dda0h address fffff086h initial value undefined 14 0 13 0 12 0 11 da27 10 da26 9 da25 8 da24 7 da23 6 da22 5 da21 4 da20 3 da19 2 da18 1 da17 0 da16 ir dda1h fffff08eh undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 ir dda2h fffff096h undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 ir dda3h fffff09eh undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 bit position bit name function 15 ir specifies the dma destination address. 0: external memory, on-chip peripheral i/o 1: internal ram 11 to 0 da27 to da16 sets the dma destination addresses (a27 to a16). during dma transfer, it stores the next dma transfer destination address. chapter 6 dma functions (dma controller) 127 user?s manual u14492ej4v1ud (2) dma destination address regist ers 0l to 3l (dda0l to dda3l) these registers can be read/written in 16-bit units. 15 da15 dda0l address fffff084h initial value undefined 14 da14 13 da13 12 da12 11 da11 10 da10 9 da9 8 da8 7 da7 6 da6 5 da5 4 da4 3 da3 2 da2 1 da1 0 da0 da15 dda1l fffff08ch undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 da15 dda2l fffff094h undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 da15 dda3l fffff09ch undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 bit position bit name function 15 to 0 da15 to da0 sets the dma destination addresses (a 15 to a0). during dma transfer, it stores the next dma transfer destination address. chapter 6 dma functions (dma controller) 128 user?s manual u14492ej4v1ud 6.3.3 dma transfer count regi sters 0 to 3 (dbc0 to dbc3) these 16-bit registers are used to set the byte transfer co unts for dma channel n (n = 0 to 3). they store the remaining transfer counts during dma transfer. since these registers are 2-stage fifo buffer registers, a new dma byte transfer count for dma transfer can be specified during dma transfer (refer to 6.9 next address setting function ). in this case, if a new dbcn register is set, the value set will be transferred to the slave register and enabled only if dma transfer ends normally, and the tcn bit of dma channel control register n (dchcn) has been set to 1 or the initn bit of the dchcn register has been set to 1 (n = 0 to 3). these registers are decremented by 1 per transfer. transfer is terminated if a borrow occurs. these registers can be read/written in 16-bit units. cautions 1. when performing 2-cycle transfer from the internal ram, do not set the transfer count to 2 (by setting the dbcn register to 0001h). if it is required to perform dm a transfer twice, be sure to perform dma tr ansfer for which the transfer count is set to 1 (by setting the dbcn register to 0000h) twice. 2. do not set the dbcn register when dma transfer has been suspended. remark if the dbcn register is read after a terminal count has occurred during dma transfer without the value of the dbcn register being rewritten, the value set i mmediately before dma transfer is read (0000h is not read even after completion of transfer). 15 bc15 dbc0 address fffff0c0h initial value undefined 14 bc14 13 bc13 12 bc12 11 bc11 10 bc10 9 bc9 8 bc8 7 bc7 6 bc6 5 bc5 4 bc4 3 bc3 2 bc2 1 bc1 0 bc0 bc15 dbc1 fffff0c2h undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bc15 dbc2 fffff0c4h undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bc15 dbc3 fffff0c6h undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bit position bit name function sets the byte transfer count. it stores t he remaining byte transfer count during dma transfer. dbcn (n = 0 to 3) states 0000h byte transfer count 1 or remaining byte transfer count 0001h byte transfer count 2 or remaining byte transfer count : : ffffh byte transfer count 65,536 (2 16 ) or remaining byte transfer count 15 to 0 bc15 to bc0 chapter 6 dma functions (dma controller) 129 user?s manual u14492ej4v1ud 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) these 16-bit registers are used to control the dma transfer modes for dma channel n (n = 0 to 3). these registers cannot be accessed during dma operation. these registers can be read/written in 16-bit units. be sure to set bits 0, 1, and 8 to 13 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. the ds1 and ds0 bits are used to set how many bits of data are transferred. when 8-bit data (ds1, ds0 bits = 00) is set, the lower data bus (ad0 to ad7) is not necessarily used. when the transfer data size is set to 16 bits , the transfer must start from an address with bit 1 of the lower address aligned to ?0?. in this case, the transf er cannot start from an odd address. 2. set the dadcn register when the corresponding channel is in one of the following periods (the operation is not guaranteed if set at another timing). ? time from system reset to generati on of the first dma transfer request ? time from dma transfer end (after terminal count) to generation of the next dma transfer request ? time from the forcible termination of dma transfer (after the ini tn bit of dma channel control register n (dchcn) has been set to 1) to generati on of the next dma transfer request (1/2) 15 ds1 dadc0 address fffff0d0h initial value 0000h 14 ds0 13 0 12 0 11 0 10 0 9 0 8 0 7 sad1 6 sad0 5 dad1 4 dad0 3 tm1 2 tm0 1 0 0 0 ds1 dadc1 fffff0d2h 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 00 ds1 dadc2 fffff0d4h 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 00 ds1 dadc3 fffff0d6h 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 00 bit position bit name function sets the transfer data size for dma transfer. ds1 ds0 transfer data size 0 0 8 bits 0 1 16 bits 1 0 setting prohibited 1 1 setting prohibited 15, 14 ds1, ds0 for the on-chip peripheral i/o and programm able peripheral i/o registers, ensure the transfer size matches the access size. chapter 6 dma functions (dma controller) 130 user?s manual u14492ej4v1ud (2/2) bit position bit name function sets the count direction of the source address for dma channel n (n = 0 to 3). sad1 sad0 count direction 0 0 increment 0 1 decrement 1 0 fixed 1 1 setting prohibited 7, 6 sad1, sad0 sets the count direction of the destinat ion address for dma channel n (n = 0 to 3). dad1 dad0 count direction 0 0 increment 0 1 decrement 1 0 fixed 1 1 setting prohibited 5, 4 dad1, dad0 sets the transfer mode during dma transfer. tm1 tm0 transfer mode 0 0 single transfer mode 0 1 single-step transfer mode 1 0 setting prohibited 1 1 block transfer mode 3, 2 tm1, tm0 chapter 6 dma functions (dma controller) 131 user?s manual u14492ej4v1ud 6.3.5 dma channel control regist ers 0 to 3 (dchc0 to dchc3) these 8-bit registers are used to c ontrol the dma transfer operating mode for dma channel n (n = 0 to 3). these registers can be read/written in 8-bit or 1-bit units . (however, bit 7 is read only and bits 2 and 1 are write only. if bits 2 and 1 are read, the read value is always 0.) be sure to set bits 4 to 6 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. if transfer is complete d with the mlen bit set to 1, and th e next transfer request is executed with the dma transfer (hardware dma) started by the dmarqn signal (internal signal) or an interrupt from the on-chip peri pheral i/o, the next transfer will be executed if the tcn bit is set to 1 (will not be automatically cleared to 0). 2. set the mlen bit when the corresponding ch annel is in one of the following periods (the operation is not guaranteed if set at another timing). ? time from system reset to generati on of the first dma transfer request ? time from dma transfer end (after terminal count) to genera tion of the next dma transfer request ? time from the forcible termination of dma transf er (after the initn bit has been set to 1) to generation of the next dma transfer request 3. if dma transfer is forcibly terminated in the last transfer cycl e with the mlen bit set to 1, the same operations as transfer completion (setting of the tcn bit to 1) are performed (the enn bit will be cleared to 0 in forcible terminati on regardless of the value of the mlen bit). in this case, at the next dm a transfer request, the enn bit mu st be set to 1 and the tcn bit must be read (cleared to 0). 4. during dma transfer completion (terminal coun t), each bit is updated in the order of clearing the enn bit to 0 and setting the tcn bit to 1. fo r this reason, if the tcn bit and enn bit are in the polling mode, the value indicating ?transfer not completed, and transfer prohibited? (tcn bit = 0, and enn bit = 0) may be read in some cases if the dchcn register is read while each of the above bits is being up dated (this is not an error). 5. do not set the enn and stgn bits when dm a transfer has been suspended; otherwise the operation cannot be guaranteed. chapter 6 dma functions (dma controller) 132 user?s manual u14492ej4v1ud address fffff0e0h <7> tc0 dchc0 6 0 5 0 4 0 <3> mle0 <2> init0 <1> stg0 <0> e00 initial value 00h fffff0e2h tc1 dchc1 0 0 0 mle1 init1 stg1 e11 00h fffff0e4h tc2 dchc2 0 0 0 mle2 init2 stg2 e22 00h fffff0e6h tc3 dchc3 0 0 0 mle3 init3 stg3 e33 00h bit position bit name function 7 tcn this status bit indicates whether dma transfer through dma channel n has ended or not. this bit is read-only. it is set to 1 when dm a transfer ends and cleared (to 0) when it is read. 0: dma transfer had not ended. 1: dma transfer had ended. 3 mlen when this bit is set to 1 when dma transfe r ends (at terminal count output), the enn bit is not cleared to 0 and the dma transfer enable state is retained. when the next dma transfer start trigger is the dmarqn signal (int ernal signal) or an interrupt from the on-chip peripheral i/o (hardware dma), the dma tran sfer request can be accepted even when the tcn bit is not read. when the next dma transfer start trigger is the setting of the stgn bit to 1 (software dma), the dma transfer request can be accepted by reading and clearing the tcn bit to 0. when this bit is cleared to 0 when dma transf er ends (at terminal count output), the enn bit is cleared to 0 and the dma transfer disable state is entered. at the next dma transfer request, the setting of the enn bit to 1 and the reading of the tcn bit are required. 2 initn when this bit is set to 1 during dma trans fer or dma transfer suspension, dma transfer is forcibly terminated (refer to 6.13.1 restrictions related to dma transfer forcible termination ). 1 stgn if this bit is set to 1 in the dma tran sfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. 0 enn specifies whether dma transfer through dma channel n is to be enabled or disabled. this bit is cleared to 0 when dma transfer ends. it is also cleared to 0 when dma transfer is forcibly suspended or terminated by means of setting the initn bit to 1 or by nmi input. 0: dma transfer disabled 1: dma transfer enabled caution after the enn bit is set (1), do not set the enn bit again until the number of dma transfers set by the dbcn register are complete or dma transfer is forcibly terminated using the initn bit. remark n = 0 to 3 chapter 6 dma functions (dma controller) 133 user?s manual u14492ej4v1ud 6.3.6 dma disable status register (ddis) this register holds the contents of t he enn bit of the dchcn register during forc ible interruption by nmi input (n = 0 to 3). this register is read-only, in 8-bit units. be sure to set bits 4 to 7 to 0. if they are set to 1, the operation is not guaranteed. address fffff0f0h 7 0 ddis 6 0 5 0 4 0 3 ch3 2 ch2 1 ch1 0 ch0 initial value 00h bit position bit name function 3 to 0 ch3 to ch0 reflects the contents of the enn bit of the dchcn register during forcible interruption by nmi input. the contents of this register ar e held until the next forcible interruption by nmi input or until the system is reset. 6.3.7 dma restart register (drst) the enn bit of the drst register and t he enn bit of the dchcn register are linked to each other (n = 0 to 3). this register can be read/written in 8-bit units. be sure to set bits 4 to 7 to 0. if they are set to 1, the operation is not guaranteed. address fffff0f2h 7 0 drst 6 0 5 0 4 0 3 en3 2 en2 1 en1 0 en0 initial value 00h bit position bit name function 3 to 0 en3 to en0 specifies whether dma transfer through dma channel n is to be enabled or disabled. this bit is cleared to 0 when dma transfer is completed in accordance with the terminal count output (n = 0 to 3). it is also cleared to 0 when dma transfer is fo rcibly terminated by setting the initn bit of the dchcn register to 1 or by nmi input. 0: dma transfer disabled 1: dma transfer enabled chapter 6 dma functions (dma controller) 134 user?s manual u14492ej4v1ud 6.3.8 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) these 8-bit registers are used to control the dma transfe r start trigger through interrupt requests from on-chip peripheral i/o. the interrupt requests set with these regist ers serve as dma transfer start factors. these registers can be read/written in 8-bit units. however, only bit 7 (dfn) can be read/written in 1-bit units (n = 0 to 3). be sure to set bit 6 to 0. if it is set to 1, the operation is not guaranteed. cautions 1. be sure to stop dma operation befo re making changes to dtfrn register settings. 2. an interrupt request input in a standby m ode (idle or software stop mode) cannot be used as a dma transfer start factor except for intp0 to intp6 and intp20 to intp25 (when the noise elimination by analog filter is selected). (1/2) <7> dtfr0 6543210 df0 0 ifc05 ifc04 ifc03 ifc02 ifc01 ifc00 address fffff810h initial value 00h <7> dtfr1 6543210 df1 0 ifc15 ifc14 ifc13 ifc12 ifc11 ifc10 fffff812h 00h <7> dtfr2 6543210 df2 0 ifc25 ifc24 ifc23 ifc22 ifc21 ifc20 fffff814h 00h <7> dtfr3 6543210 df3 0 ifc35 ifc34 ifc33 ifc32 ifc31 ifc30 fffff816h 00h bit position bit name function 7 dfn this is a dma transfer request flag. only 0 can be written to this flag. 0: no dma transfer request 1: dma transfer request if an interrupt that causes dma transfer occurs while dma transfer is disabled (including if it has been suspended by an nmi or forcibly te rminated by software), and if this dma transfer request must be cleared, stop the operation causing the interrupt (e.g., disable reception if serial reception is in progress), and then clear the dfn bit. if it is clear in the application that the interrupt will not occur agai n until dma transfer is resumed next, it is not necessary to stop the operation causing the interrupt. sets the interrupt source that serves as the dma transfer start factor. ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request from on-chip peripheral i/o disabled 0 0 0 0 0 1 intp0 0 0 0 0 1 0 intp1 0 0 0 0 1 1 intp2 0 0 0 1 0 0 intp3 0 0 0 1 0 1 intp4 0 0 0 1 1 0 intp5 5 to 0 0 0 0 1 1 1 intp6 ifcn5 to ifcn0 remark n = 0 to 3 chapter 6 dma functions (dma controller) 135 user?s manual u14492ej4v1ud (2/2) bit position bit name function ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 1 0 0 0 intdet0 0 0 1 0 0 1 intdet1 0 0 1 0 1 0 inttm00 0 0 1 0 1 1 intcm003 0 0 1 1 0 0 inttm01 0 0 1 1 0 1 intcm013 0 0 1 1 1 0 intp100/intcc100 0 0 1 1 1 1 intp101/intcc101 0 1 0 0 0 0 intcm100 0 1 0 0 0 1 intcm101 0 1 0 0 1 0 intp110/intcc110 0 1 0 0 1 1 intp111/intcc111 0 1 0 1 0 0 intcm110 0 1 0 1 0 1 intcm111 0 1 0 1 1 0 inttm20 0 1 0 1 1 1 inttm21 0 1 1 0 0 0 intp20/intcc20 0 1 1 0 0 1 intp21/intcc21 0 1 1 0 1 0 intp22/intcc22 0 1 1 0 1 1 intp23/intcc23 0 1 1 1 0 0 intp24/intcc24 0 1 1 1 0 1 intp25/intcc25 0 1 1 1 1 0 inttm3 0 1 1 1 1 1 intp30/intcc30 1 0 0 0 0 0 intp31/intcc31 1 0 0 0 0 1 intcm4 1 0 0 0 1 0 intdma0 1 0 0 0 1 1 intdma1 1 0 0 1 0 0 intdma2 1 0 0 1 0 1 intdma3 1 0 0 1 1 0 intcrec 1 0 0 1 1 1 intctrx 1 0 1 0 0 0 intcerr 1 0 1 0 0 1 intcmac 1 0 1 0 1 0 intcsi0 1 0 1 0 1 1 intcsi1 1 0 1 1 0 0 intsr0 1 0 1 1 0 1 intst0 1 0 1 1 1 0 intser0 1 0 1 1 1 1 intsr1 1 1 0 0 0 0 intst1 1 1 0 0 0 1 intsr2 1 1 0 0 1 0 intst2 1 1 0 0 1 1 intad0 1 1 0 1 0 0 intad1 1 1 0 1 0 1 nbdad note 1 1 0 1 1 0 nbdrew note other than above setting prohibited 5 to 0 ifcn5 to ifcn0 note pd70f3116 only remark n = 0 to 3 chapter 6 dma functions (dma controller) 136 user?s manual u14492ej4v1ud 6.4 dma bus states 6.4.1 types of bus states the dmac bus states consis t of the following 10 states. (1) ti state the ti state is an idle state, duri ng which no access request is issued. the dma request signals are sampled at the rising edge of the clkout signal. (2) t0 state dma transfer ready state (state in which a dma transfe r request has been issued and the bus mastership is acquired for the first dma transfer). (3) t1r state the bus enters the t1r state at the beginning of a read operation in the two-cycle transfer mode. address driving starts. after entering the t1r st ate, the bus invariably enters the t2r state. (4) t1ri state the t1ri state is a state in whic h the bus waits for the acknowledge signal corresponding to an external memory read request. after entering the last t1ri state, t he bus invariably enters the t2r state. (5) t2r state the t2r state corresponds to the last state of a read operation in the two-cycle transfer mode, or to a wait state. in the last t2r state, read data is sampled. after entering the last t2r state, the bus invariably enters the t1w state. (6) t2ri state the t2ri state is a state in which the bus is ready for dma transfer to on-chip peripheral i/o or internal ram (state in which the bus ma stership is acquired for dm a transfer to on-chip peripher al i/o or internal ram). after entering the last t2ri state, t he bus invariably enters the t1w state. (7) t1w state the bus enters the t1w state at the beginning of a write operatio n in the two-cycle transfer mode. address driving starts. after entering the t1w st ate, the bus invariably enters the t2w state. (8) t1wi state the t1wi state is a state in which the bus waits fo r the acknowledge signal corresponding to an external memory write request. after entering the last t1wi state, t he bus invariably enters the t2w state. (9) t2w state the t2w state corresponds to the last state of a write operat ion in the two-cycle transfer mode, or to a wait state. in the last t2w state, the writ e strobe signal is made inactive. chapter 6 dma functions (dma controller) 137 user?s manual u14492ej4v1ud (10) te state the te state corresponds to dma transfer completion. va rious internal signals are initialized (n = 0 to 3). after entering the te state, the bus invariably enters the ti state. 6.4.2 dmac bus cycle state transition except for the block transfer mode, each time the processi ng for a dma transfer is completed, the bus mastership is released. figure 6-1. dmac bus cycle (two-c ycle transfer) state transition ti t0 t1r t1ri t2r t1w t2w te ti t2ri t1wi chapter 6 dma functions (dma controller) 138 user?s manual u14492ej4v1ud 6.5 transfer mode 6.5.1 single transfer mode in single transfer mode, the dmac rel eases the bus at each byte/halfword tr ansfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. however, if a lo wer priority dma transfer request is generated within one clock after the end of a single transfer, even if the previous higher priority dma transfer request signal stays active, this request is not prioritized, and the next dma transfer a fter the bus is released for the cpu is a transfer based on the newly generated, lower priority dma transfer request. figures 6-2 to 6-5 show examples of single transfer. figure 6-2. single transfer example 1 cpu dma3 cpu cpu dma3 cpu cpu cpu cpu cpu dma3 cpu dma3 dma3 cpu cpu cpu dmarq3 (internal signal) cpu cpu dma channel 3 terminal count note note note note note the bus is always released. figure 6-3 shows a single transfer mode example in which a higher priority dma transfer request is generated. dma channels 0 to 2 are used for a block transfer, and channel 3 is used for a single transfer. figure 6-3. single transfer example 2 dma1 dma2 cpu dma2 cpu dma3 cpu cpu cpu dma3 cpu dma0 dma0 cpu dma1 dmarq3 cpu dma3 dmarq2 dmarq1 dmarq0 note note note note dma channel 0 terminal count dma channel 2 terminal count dma channel 3 terminal count dma channel 1 terminal count (internal signal) (internal signal) (internal signal) (internal signal) note the bus is always released. chapter 6 dma functions (dma controller) 139 user?s manual u14492ej4v1ud figure 6-4 shows a single transfer mode example in which a lower priority dma transfer request is generated within one clock after the end of a single transfer. dma channels 0 and 3 are used for a single transfer. when two dma transfer request signals are activated at the same time, the two dma transfers are performed alternately. figure 6-4. single transfer example 3 cpu cpu dma3 dma0 cpu dma0 cpu cpu cpu cpu dma0 cpu dma0 dma3 cpu cpu dma0 dmarq3 cpu dma0 dma channel 0 terminal count note note note note dmarq0 dma channel 3 terminal count note note note (internal signal) (internal signal) note the bus is always released. figure 6-5 shows a single transfer mode example in which two or more lower priority dma transfer requests are generated within one clock after the end of a single transfer. dma channels 0, 2, and 3 are used for a single transfer. when three or more dma transfer request signals are activated at the same time, always the two highest priority dma transfers are performed alternately. figure 6-5. single transfer example 4 dma2 cpu dma3 cpu cpu dma3 cpu cpu dma2 dma0 cpu dmarq3 dma0 note note note dmarq2 note note dmarq0 dma2 cpu dma channel 0 terminal count note dma3 cpu dma2 cpu cpu dma3 dma channel 3 terminal count note cpu cpu note dma channel 2 terminal count note (internal signal) (internal signal) (internal signal) note the bus is always released. chapter 6 dma functions (dma controller) 140 user?s manual u14492ej4v1ud 6.5.2 single-step transfer mode in single-step transfer mode, the dmac releases the bus at each byte/halfword transfer. once a dma transfer request signal is received, transfer is performed again. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. figures 6-6 and 6-7 show examples of single-step transfer. figure 6-7 shows a single-step transfer mode example in which a higher priority dma transfer request is gener ated. dma channels 0 and 1 are used for the single-step transfer. figure 6-6. single-step transfer example 1 dma1 cpu cpu cpu cpu cpu cpu cpu cpu dma1 cpu cpu dma1 dma1 cpu dmarq1 cpu cpu dma channel 1 terminal count note note note (internal signal) note the bus is always released. figure 6-7. single-step transfer example 2 dma0 dma0 cpu cpu dma1 cpu cpu cpu cpu dma1 cpu cpu dma1 dma0 cpu dmarq1 dma1 cpu dmarq0 dma channel 0 terminal count dma channel 1 terminal count note note note note note note (internal signal) (internal signal) note the bus is always released. 6.5.3 block transfer mode in the block transfer mode, once transfer starts, the dm ac continues the transfer oper ation without releasing the bus until a terminal count occurs. no other dma r equests are acknowledged during block transfer. after the block transfer ends and the dmac releases the bus, another dma transfer can be acknowledged. chapter 6 dma functions (dma controller) 141 user?s manual u14492ej4v1ud 6.6 transfer types 6.6.1 two-cycle transfer in two-cycle transfer, data transfer is performed in two cy cles, a read cycle (source to dmac) and a write cycle (dmac to destination). in the first cycle, the source address is output and reading is performed from the source to the dmac. in the second cycle, the destination address is output and writi ng is performed from the dmac to the destination. caution an idle cycle of 1 cl ock is always inserted between the read cycle and write cycle. chapter 6 dma functions (dma controller) 142 user?s manual u14492ej4v1ud 6.7 transfer target 6.7.1 transfer type and transfer target table 6-1 shows the relationship between t he transfer type and transfer target ( : transfer enabled, : transfer disabled). table 6-1. relationship between tr ansfer type and transfer target destination two-cycle transfer internal rom on-chip peripheral i/o internal ram external memory, external i/o on-chip peripheral i/o external i/o internal ram external memory source internal rom cautions 1. the operation is not guaranteed for comb inations of transfer dest ination and source marked with ? ? in table 6-1. 2. addresses between 3fff000h and 3ffffffh ca nnot be specified for the source and destination address of dma transfer. be sure to specify an address between ffff000h and fffffffh. remark during two-cycle dma transfer, if the data bus width of the transfer source a nd that of the transfer destination are different, the operation becomes as follows. if the target of the dma transfer is an on-chip peripheral i/o register (transfer source/transfer destination), be sure to specify the same transfer size as the register size. for example, in the case of dma transfer to an 8-bit register, be sure to specify byte (8-bit) transfer. <16-bit transfer> ? transfer from a 16-bit bus to an 8-bit bus a read cycle (16 bits) is generated and then a writ e cycle (8 bits) is generated twice successively. ? transfer from an 8-bit bus to a 16-bit bus a read cycle (8 bits) is generated twice successively and then a write cycle (16 bits) is generated. data is written to the transfer destination from the lowest byte in little-endian mode, and the highest byte in big-endian mode. <8-bit transfer> ? transfer from a 16-bit bus to an 8-bit bus a read cycle (the higher 8 bits go into a high-impedance state) is generated and then a write cycle (8 bits) is generated. ? transfer from an 8-bit bus to a 16-bit bus a read cycle (8 bits) is generated a nd then a write cycle (the higher 8 bits go into a high-impedance state) is generated. data is wr itten to the transfer destination from the lowest byte in little-endian mode, and the highest byte in big-endian mode. chapter 6 dma functions (dma controller) 143 user?s manual u14492ej4v1ud 6.7.2 external bus cycles during dma transfer (two-cycle transfer) the external bus cycles during dma transfe r (two-cycle transfe r) are shown below. table 6-2. external bus cycles duri ng dma transfer (two-cycle transfer) transfer target external bus cycle on-chip peripheral i/o, internal ram none ? external memory, external i/o yes sram, ex ternal rom, external i/o access cycle 6.8 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 these priorities are valid in the ti state only. in the block transfer mode , the channel used for transfer is never switched. in the single-step transfer mode, if a higher priority dma tr ansfer request is issued while the bus is released (in the ti state), the higher priority dma transfer request is acknowledged. caution do not start more than one dma channel us ing the same start factor. if more than one dma channel is started, a lower prio rity dma channel may be acknowledg ed prior to a higher priority dma channel. 6.9 next address setting function the dma source address registers (dsanh, dsanl), dm a destination address registers (ddanh, ddanl), and dma transfer count register (dbcn) are 2-stage fifo buffe r registers configured with a master register and slave register (n = 0 to 3). when the terminal count is issued, these registers ar e automatically rewritten wit h the value that was set immediately before. therefore, by making a new dma transfer setting for thes e registers and setting the enn and mlen bits of the dchcn register to 1 during dma transfer, the new dma trans fer is automatically started (however, a dma transfer end interrupt is generated even for an aut omatically started dma transfer). chapter 6 dma functions (dma controller) 144 user?s manual u14492ej4v1ud figure 6-8 shows the configurat ion of the buffer register. figure 6-8. buffer register configuration the actual dma transfer is performed bas ed on the settings of the slave register. the settings incorporated in the master and slave registers differ as follows according to the timing (time) at which the settings were made. (1) time from system reset to genera tion of first dma transfer request the settings made are incorporated in bot h the master and slave registers. (2) during dma transfer (time from generation of dma transfer request to end of dma transfer) the settings made are incorporated in only the master register, and not in the slave register (the slave register maintains the value set for the next dma transfer). however, the contents of the master register are automatically overwritten in the slave register after dma transfer ends. the value of the slave register is read if the value of each regist er is read during this period. (3) time from dma transfer end to start of next dma transfer the settings made are incorporated in bot h the master and slave registers. remark ?dma transfer end? means one of the following. ? completion of dma transfer (terminal count) ? forcible termination of dma transfer (the in itn bit of the dchcn register is set to 1) therefore, by making a new dma transfer setting for t he dsanh, dsanl, ddanh, ddanl, or dbcn register during dma transfer, values will automatically be updated to the new values after transfer note . note if making another new dma transfer setting, make sure that the current dma transfer has started first. making a new setting before the current dma transfer st arts will overwrite the val ues of both the master and slave registers. as a result, dma transfer is not performed based on the value set immediately before the dma transfer starts. data read data write master register slave register address/ count controller internal bus chapter 6 dma functions (dma controller) 145 user?s manual u14492ej4v1ud 6.10 dma transfer start factors there are two types of dma transfe r start factors, as shown below. cautions 1. do not use two or more start factors ((1 ) and (2)) in combination fo r the same channel (if two or more start factors are generated at the same time, only one of them is valid, but the valid start factor cannot be identified). the operati on is not guaranteed if two or more start factors are used in combination. 2. if dma transfer is started via software and if the software does not co rrectly detect whether the expected dma transfer opera tion has been completed through manipulation (setting to 1) of the stgn bit of the dchcn register, it cannot be guaranteed whether the next (second) manipulation of the stgn bit corresponds to the st art of ?the next dma transfer expected by software? (n = 0 to 3). for example, suppose single transfer is starte d by manipulating the stgn bit. even if the stgn bit is manipulated next (the second ti me) without checking by software whether the single transfer has actually b een executed, the next (second) dma transfer is not always executed. this is because the stgn bit may be manipulated th e second time before the first dma transfer is started or completed becau se, for example, dma transfer with a higher priority had already been starte d when the stgn bit was manipulat ed for the first time. it is therefore necessary to manipula te the stgn bit next time (the second time) after checking whether dma transfer started by the first mani pulation of the stgn bi t has been completed. completion of dma transfer can be checked by checking the contents of the dbcn register. (1) request from software if the stgn, enn, and tcn bits of t he dchcn register are set as follows, dma transfer starts (n = 0 to 3). ? stgn bit = 1 ? enn bit = 1 ? tcn bit = 0 (2) request from on-chip peripheral i/o if, when the enn and tcn bits of the dchcn register are set as shown below, an interrupt request is issued from the on-chip peripheral i/o that is set in the dtfrn register, dma transfer starts (n = 0 to 3). ? enn bit = 1 ? tcn bit = 0 chapter 6 dma functions (dma controller) 146 user?s manual u14492ej4v1ud 6.11 forcible interruption dma transfer can be forcibly interrupted by nmi input during dma transfer. at such a time, the dmac clears the enn bit of the dchcn register of all channels to 0 and the dma transfer disabled state is entered. an nmi request can then be acknowledged after the dma transfer executed during nmi input is terminated (n = 0 to 3). if dma transfer has been forcibly inte rrupted, perform forcible termination of the dma using the initn bit of the dchcn register and then initialize. 6.12 dma transfer end when dma transfer ends and the tcn bit of the dchcn register is set to 1, a dma transfer end interrupt (intdman) is issued to the interrupt controller (intc) (n = 0 to 3). 6.13 forcible termination in addition to the forcible interruption operation by m eans of nmi input, dma transfer can be forcibly terminated by the initn bit of the dchcn register (n = 0 to 3). remark because the dsan, ddan, and dbcn registers are fifo buffer registers, the values are held even after a forcible termination. also, the next transfer condition can be set even during dma transfer. but, because the dadcn and dchcn registers are not bu ffer registers, the setting during dma transfer is invalid (refer to 6.9 next address setting function and 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) ). 6.13.1 restriction related to dm a transfer forcible termination when terminating a dma transfer by setting the initn bi t of the dchcn register, the transfer may not be terminated, but just suspended, even though the initn bit is se t to 1. as a result, when the dma transfer of a channel that should have been terminated is resumed, the dm a transfer will terminate after an unexpected number of transfers are completed and a dma transfer completion interrupt may occur. [preventive measures] this problem can be avoided by implement ing any of the following workarounds. (1) stop all the transfers from dma channels temporarily. the following measure is effective if the program does not assume that th e tcn bit of the dchcn register is 1 except for the following workaround processing. (since the tcn bit of the dchcn register is cleared to 0 when it is read, execution of the following procedure (ii) under step <5> clears this bit.) <1> disable interrupts (di state). <2> read the dma restart register (drst) and transfer the enn bit of each channel to a general-purpose register (value a). <3> write 00h to the dma restart register (drst) twice note . by executing twice, the dma transfer is definitely stopped before proceeding to <4>. <4> set the initn bit of the dchcn register of the channel to be forcibly terminated to 1. chapter 6 dma functions (dma controller) 147 user?s manual u14492ej4v1ud <5> perform the following operations for value a read in step <2>. (value b) (i) clear the bit of the channel to be forcibly terminated to 0 (ii) if the tcn of the dchcn register and enn bit of the drst register of the channel that is not terminated forcibly are 1 (and makes 1), clear the bit of the channel to 0. <6> write value b in <5> to the drst register. <7> enable interrupts (ei state). note execute three times if the transfer target (trans fer source or transfer destination) is the internal ram. caution be sure to execute st ep <5> to prevent the enn bit of the drst register from being set illegally for channels that ar e terminated normally during the period of steps <2> and <3>. remark n = 0 to 3 (2) repeat setting the initn bit of the dchcn register until forcible termination of dma transfer is completed normally the procedure is shown below. <1> copy the initial transfer count of the channel to be forcibly terminated to a general-purpose register. <2> set the initn bit of the dchcn register of the channel to be forcibly terminated to 1. <3> read the value of dma transfer count register n (dbcn) of the channel to be forcibly terminated, and compare that value with the value copied in step <1>. if the two values do not match, repeat steps <2> and <3>. cautions 1. if the dbcn register is read in st ep <3>, and if dma transfer is stopped due to trouble, the remaining number of transfers will be read. if dma transfer has been forcibly terminated correctly, the init ial number of transfers will be read. 2. with this procedure, it may take some time for the channel in question to be forcibly terminated in an application in wh ich dma transfer of a channel other than that to be forcibly termina ted is frequently executed. remark n = 0 to 3 chapter 6 dma functions (dma controller) 148 user?s manual u14492ej4v1ud 6.14 times related to dma transfer the number of minimum internal system execut ion clocks for dma trans fer are shown below. table 6-3. number of minimum intern al system execution clocks in dma cycle dma cycle number of minimum inte rnal system execution clocks <1> time to respond to dma request 4 clocks note 1 internal ram access 2 clocks note 2 <2> memory access peripheral i/o register access 4 clocks + number of waits set by vswc register notes 1. if an external interrupt (intpn) is specified as a fact or of starting dma transfer, noise elimination time is added (n = 0 to 6, 100, 101, 110, 111, 20 to 25, 30, or 31). 2. two clocks are required for the dma cycle. the minimum execution clock in the dma cycl e in each transfer mode is as follows. single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note + transfer destination memory access (<2>) block transfer: dma response time (<1>) + (transfer source memory access (<2>) + 1 note + transfer destination memory access (<2>)) number of transfers note one internal system clock is always inserted bet ween the read cycle and writ e cycle of dma transfer. 6.15 precautions (1) memory boundary the transfer operation is not guarant eed if the source or the destination address exceeds the area of dma objects (external memory, internal ram, or on-chip peripheral i/o) during dma transfer. (2) transfer of misaligned data dma transfer of 16-bit bus width misaligned data is not supported. (3) bus arbitration for cpu when an external device is targeted for dma transfe r, the cpu can access the internal rom and internal ram (if they are not subject to dma transfer). when dma transfer is executed betw een the on-chip per ipheral i/o and internal ram, the cpu can access the internal rom. (4) dma start factor do not start more than one dma channel using the same start factor. if more than one dma channel is started, a lower priority dma channel may be ackn owledged prior to a higher priority dma channel. (5) restrictions related to automatic clearing of tcn bit of dchcn register the tcn bit of the dchcn register is automatically cleared to 0 when it is read. when dma transfer is executed to transfer data to or from the internal ram when two or more dma transfer channels are simultaneously used, the tcn bit may not be cleared even if it is read after completion of dma transfer (n = 0 to 3). chapter 6 dma functions (dma controller) 149 user?s manual u14492ej4v1ud caution this restriction does not apply if one of the following conditions is satisfied. ? only one channel of dma transfer is used. ? dma is not executed to transfer data to or from the internal ram. [preventive measures] to read the tcn bit of the dchcn regi ster of the dma channel that is used to transfer data to or from the internal ram, be sure to read the tcn bit three times in a row. this can accurately clear the tcn bit to 0. (6) read values of dsan and ddan registers if the values of the dsan and ddan registers are read during dma transfer, the values in the middle of being updated may be read (n = 0 to 3). for example, if the dsanh register and the dsanl regist er are read in that order when the value of the dma transfer source address (dsa n register) is ?0000ffffh? an d the counting direction is incremental (when the sadn1 and sadn0 bits of the dadcn register = 00), t he value of the dsanl register differs as follows depending on whether dma transfer is executed immedi ately after the dsanh register has been read. (a) if dma transfer does not occur while the dsan register is being read <1> reading dsanh register: dsanh = 0000h <2> reading dsanl register: dsanl = ffffh (b) if dma transfer occurs while the dsan register is being read <1> reading dsanh register: dsanh = 0000h <2> occurrence of dma transfer <3> incrementing dsan register : dsan = 00010000h <4> reading dsanl register: dsanl = 0000h 6.15.1 interrupt factors dma transfer is interrupted if a bus hold is issued. if the factor (bus hold) interrupting dma transfe r disappears, dma transfer promptly restarts. 150 user?s manual u14492ej4v1ud chapter 7 interrupt/exception processing function the v850e/ia1 is provided with an interr upt controller (intc) that can proc ess a total of 53 interrupt requests. an interrupt is an event that occu rs independently of program execution, and an except ion is an event whose occurrence is dependent on pr ogram execution. the v850e/ia1 can process interrupt requests from the on-chip peripheral hardware and external sources. moreover, exception processing can be st arted by the trap instruction (softwar e exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). eight levels of software-programmable priorities can be specified for each interrupt request. interrupt servicing starts after no fewer than 4 system clocks (80 ns (@ 50 mhz)) following the generation of an interrupt request. 7.1 features { interrupts ? non-maskable interrupts: 1 source ? maskable interrupts: 52 sources ? 8 levels of programmable priorities (maskable interrupts) ? multiple interrupt contro l according to priority ? masks can be specified for each maskable interrupt request. ? noise elimination note , edge detection, and valid edge specification for external interrupt request signals. note for details of the noise eliminator, refer to 14.4 noise eliminator. { exceptions ? software exceptions: 32 sources ? exception traps: 2 sources ( illegal opcode exception and debug trap) interrupt/exception sources ar e listed in table 7-1. chapter 7 interrupt/exception processing function 151 user?s manual u14492ej4v1ud table 7-1. interrupt/exception source list (1/2) interrupt/exception source type classification name controlling register generating source generating unit default priority exception code handler address restored pc reset interrupt reset ? reset input pin ? 0000h 00000000h undefined non-maskable interrupt nmi0 ? nmi input pin ? 0010h 00000010h nextpc exception trap0n note ? trap instruction ? ? 004nh note 00000040h nextpc software exception exception trap1n note ? trap instruction ? ? 005nh note 00000050h nextpc exception trap exception ilgop/ dbg0 ? illegal opcode/ dbtrap instruction ? ? 0060h 00000060h nextpc interrupt intp0 p0ic0 intp0 pin pin 0 0080h 00000080h nextpc interrupt intp1 p0ic1 intp1 pin pin 1 0090h 00000090h nextpc interrupt intp2 p0ic2 intp2 pin pin 2 00a0h 000000a0h nextpc interrupt intp3 p0ic3 intp3 pin pin 3 00b0h 000000b0h nextpc interrupt intp4 p0ic4 intp4 pi n pin 4 00c0h 000000c0h nextpc interrupt intp5 p0ic5 intp5 pi n pin 5 00d0h 000000d0h nextpc interrupt intp6 p0ic6 intp6 pin pin 6 00e0h 000000e0h nextpc interrupt intdet0 detic0 ad0 voltage detection adc 7 00f0h 000000f0h nextpc interrupt intdet1 detic1 ad1 voltage detection adc 8 0100h 00000100h nextpc interrupt inttm00 tm0ic0 tm00 underfl ow rpu 9 0110h 00000110h nextpc interrupt intcm003 cm03ic0 cm003 ma tch rpu 10 0120h 00000120h nextpc interrupt inttm01 tm0ic1 tm01 underfl ow rpu 11 0130h 00000130h nextpc interrupt intcm013 cm03ic1 cm013 ma tch rpu 12 0140h 00000140h nextpc interrupt intp100/ intcc100 cc10ic0 intp100 pin/ cc100 match pin/rpu 13 0150h 00000150h nextpc interrupt intp101/ intcc101 cc10ic1 intp101/intp100 pin/ cc101 match pin/rpu 14 0160h 00000160h nextpc interrupt intcm100 cm10ic0 cm100 ma tch rpu 15 0170h 00000170h nextpc interrupt intcm101 cm10ic1 cm101 ma tch rpu 16 0180h 00000180h nextpc interrupt intp110/ intcc110 cc11ic0 intp110 pin/ cc110 match pin/rpu 17 0190h 00000190h nextpc interrupt intp111/ intcc111 cc11ic1 intp111/intp110 pin/ cc111 match pin/rpu 18 01a0h 000001a0h nextpc interrupt intcm110 cm11ic0 cm110 ma tch rpu 19 01b0h 000001b0h nextpc interrupt intcm111 cm11ic1 cm111 ma tch rpu 20 01c0h 000001c0h nextpc interrupt inttm20 tm2ic0 tm20 overfl ow rpu 21 01d0h 000001d0h nextpc interrupt inttm21 tm2ic1 tm21 overfl ow rpu 22 01e0h 000001e0h nextpc interrupt intp20/ intcc20 cc2ic0 intp20 pin/cc20 match pin/ rpu 23 01f0h 000001f0h nextpc interrupt intp21/ intcc21 cc2ic1 intp21 pin/cc21 match pin/ rpu 24 0200h 00000200h nextpc interrupt intp22/ intcc22 cc2ic2 intp22 pin/cc22 match pin/ rpu 25 0210h 00000210h nextpc interrupt intp23/ intcc23 cc2ic3 intp23 pin/ cc23 match pin/rpu 26 0220h 00000220h nextpc interrupt intp24/ intcc24 cc2ic4 intp24 pin/ cc24 match pin/rpu 27 0230h 00000230h nextpc interrupt intp25/ intcc25 cc2ic5 intp25 pin cc25 match pin/rpu 28 0240h 00000240h nextpc maskable interrupt inttm3 tm3ic0 tm3 overfl ow rpu 29 0250h 00000250h nextpc note n = 0 to fh chapter 7 interrupt/exception processing function 152 user?s manual u14492ej4v1ud table 7-1. interrupt/exception source list (2/2) interrupt/exception source type classification name controlling register generating source generating unit default priority exception code handler address restored pc interrupt intp30/ intcc30 cc3ic0 intp30 pin/cc30 match pi n/rpu 30 0260h 00000260h nextpc interrupt intp31/ intcc31 cc3ic1 intp31 pin/cc31 match pi n/rpu 31 0270h 00000270h nextpc interrupt intcm4 cm4ic0 cm4 matc h signal rpu 32 0280h 00000280h nextpc interrupt intdma0 dmaic0 end of dm a0 transfer dma 33 0290h 00000290h nextpc interrupt intdma1 dmaic1 end of dma1 transfer dma 34 02a0h 000002a0h nextpc interrupt intdma2 dmaic2 end of dma2 transfer dma 35 02b0h 000002b0h nextpc interrupt intdma3 dmaic3 end of dma3 transfer dma 36 02c0h 000002c0h nextpc interrupt intcrec canic0 can1 recepti on complete fcan 37 02d0h 000002d0h nextpc interrupt intctrx canic1 can1 transmission complete fcan 38 02e0h 000002e0h nextpc interrupt intcerr canic2 can1 communication error fcan 39 02f0h 000002f0h nextpc interrupt intcmac canic3 can illegal write fcan 40 0300h 00000300h nextpc interrupt intcsi0 csiic0 csi0 transmission/ reception complete sio 41 0310h 00000310h nextpc interrupt intcsi1 csiic1 csi1 transmission/ reception complete sio 42 0320h 00000320h nextpc interrupt intsr0 sric0 uart0 reception complete sio 43 0330h 00000330h nextpc interrupt intst0 stic0 uart0 transmission complete sio 44 0340h 00000340h nextpc interrupt intser0 seic0 uart0 recept ion error sio 45 0350h 00000350h nextpc interrupt intsr1 sric1 uart1 reception complete sio 46 0360h 00000360h nextpc interrupt intst1 stic1 uart1 transmission complete sio 47 0370h 00000370h nextpc interrupt intsr2 sric2 uart2 reception complete sio 48 0380h 00000380h nextpc interrupt intst2 stic2 uart2 transmission complete sio 49 0390h 00000390h nextpc interrupt intad0 adic0 end of ad0 conversion adc 50 03a0h 000003a0h nextpc maskable interrupt intad1 adic1 end of ad1 conversion adc 51 03b0h 000003b0h nextpc remarks 1. default priority: the priority order when two or more maskable interrupt requests are generated at the same time. the highest priority is 0. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, the value of the pc saved when an interrupt is acknowledged during division (div, divh, divu, divhu) in struction execution is the value of the pc of the current instruction (div, divh, divu, divhu). nextpc: the pc value that starts the processing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). chapter 7 interrupt/exception processing function 153 user?s manual u14492ej4v1ud 7.2 non-maskable interrupt a non-maskable interrupt request is acknowledged unconditi onally, even when interrupts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence over all the other interrupts. a non-maskable interrupt request is input from the nmi pin. when the valid edge specifi ed by bit 0 (esn0) of the external interrupt mode register 0 (intm0) is detected on the nmi pin, the interrupt occurs. while the service program of the non -maskable interrupt is being executed, another non-maskable interrupt request is held pending. the pending nmi is acknowledged after the or iginal service program of the non-maskable interrupt under execution has been terminated (by the reti instruction). note that if two or more nmi requests are input during the execution of the serv ice program for an nmi, the number of nmis that will be acknowledged after the reti instruction is executed is only one. chapter 7 interrupt/exception processing function 154 user?s manual u14492ej4v1ud 7.2.1 operation if a non-maskable interrupt is generated by nmi input, t he cpu performs the following processing, and transfers control to the handler routine. (1) saves the restored pc to fepc. (2) saves the current psw to fepsw. (3) writes exception code 0010h to the higher halfword (fecc) of ecr. (4) sets the np and id bits of the psw and clears the ep bit. (5) sets the handler address (00000010h) corresponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non-mask able interrupt is shown in figure 7-1. figure 7-1. servicing configur ation of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h 1 0 1 00000010h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing chapter 7 interrupt/exception processing function 155 user?s manual u14492ej4v1ud figure 7-2. acknowledging non -maskable interrupt request (a) if a new nmi request is generated while an nmi ser vice program is being executed main routine nmi request nmi request (psw.np = 1) nmi request held pending regardless of the value of the np bit of the psw pending nmi request processed (b) if a new nmi request is generated twice while an nmi service program is being executed main routine nmi request nmi request held pending because nmi service program is being processed only one nmi request is acknowledged even though two nmi requests are generated nmi request held pending because nmi service program is being processed chapter 7 interrupt/exception processing function 156 user?s manual u14492ej4v1ud 7.2.2 restore execution is restored from the non-maskable inte rrupt servicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. (1) restores the values of the pc and the psw from fepc and fepsw, res pectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. (2) transfers control back to the address of the restored pc and psw. figure 7-3 illustrates how the reti instruction is processed. figure 7-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the psw.ep bit and psw.np bit ar e changed by the ldsr instruction during non- maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid lines show the cpu processing flow. chapter 7 interrupt/exception processing function 157 user?s manual u14492ej4v1ud 7.2.3 non-maskable interrupt status flag (np) the np flag is a status flag that i ndicates that non-maskable interrupt (nmi ) servicing is under execution. this flag is set when an nmi interrupt has been acknowl edged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged. 31 0 psw initial value 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 7 np indicates whether nmi interrupt servicing is in progress. 0: no nmi interrupt servicing 1: nmi interrupt currently being serviced 7.2.4 edge detection function (1) external interrupt m ode register 0 (intm0) external interrupt mode register 0 (intm0) is a register that spec ifies the valid edge of a non-maskable interrupt (nmi). the nmi valid edge can be specified to be either t he rising edge or the falling edge by the esn0 bit. this register can be read/written in 8-bit or 1-bit units. address fffff880h 7 0 intm0 6 0 5 0 4 0 3 0 2 0 1 0 <0> esn0 initial value 00h bit position bit name function 0 esn0 specifies the nmi pin?s valid edge. 0: falling edge 1: rising edge chapter 7 interrupt/exception processing function 158 user?s manual u14492ej4v1ud 7.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. t he v850e/ia1 has 52 maskable interrupt sources. if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight le vels of priorities can be spec ified by using the interrupt control registers (programmable priority control). when an interrupt request has been ackno wledged, the acknowledgement of other maskable interrupt requests is disabled and the interrupt disabled (di) status is set. when the ei instruction is ex ecuted in an interrupt servici ng routine, the interrupt enabled (ei) status is set, which enables servicing of interrupts having a hi gher priority than the interrupt request in progress (specified by the interrupt control register). note that only in terrupts with a higher priority will have th is capability; interrupts with the same priority level cannot be nested. however, if multiple interrupts are exec uted, the following processing is necessary. <1> save eipc and eipsw in memory or a general-purpos e register before executi ng the ei instruction. <2> execute the di instruct ion before executing the reti instruction, then reset ei pc and eipsw with the values saved in <1>. 7.3.1 operation if a maskable interrupt occurs by int input, the cpu perfo rms the following processing, and transfers control to a handler routine. (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower halfword of ecr (eicc). (4) sets the id bit of the psw and clears the ep bit. (5) sets the handler address corresponding to each interrupt to the pc, and transfers control. the servicing configurati on of a maskable interrupt is shown in figure 7-4. chapter 7 interrupt/exception processing function 159 user?s manual u14492ej4v1ud figure 7-4. servicing configur ation of maskable interrupt int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc acknowledged yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address note for the ispr register, see 7.3.6 in-service priori ty register (ispr) . the int input masked by the interrupt controllers and the int input that o ccurs while another interrupt is being serviced (when psw.np = 1 or psw.id = 1) are held pending internally by the interrupt controller. in such case, if the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 as set by the reti and ldsr instructions, input of the pending int starts the new ma skable interrupt servicing. chapter 7 interrupt/exception processing function 160 user?s manual u14492ej4v1ud 7.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. (1) restores the values of the pc and the psw from eipc and eipsw bec ause the ep bit of the psw is 0 and the np bit of the psw is 0. (2) transfers control to the address of the restored pc and psw. figure 7-5 illustrates the processi ng of the reti instruction. figure 7-5. reti instruction processing note for the ispr register, see 7.3.6 in-service priori ty register (ispr) . caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark the solid lines show the cpu processing flow. psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw chapter 7 interrupt/exception processing function 161 user?s manual u14492ej4v1ud 7.3.3 priorities of maskable interrupts the v850e/ia1 provides multiple interr upt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts c an be controlled by priority levels. there are two types of priority leve l control: control based on the default priority leve ls, and control based on the programmable priority levels that are spec ified by the interrupt priority level s pecification bit (xxprn ) of the interrupt control register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupts ar e serviced in order depending on the priority level allocated to each interrupt request type (default priority level) befor ehand. for more information, refer to table 7-1 interrupt/exception source list . the programmable priority control cu stomizes interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is a cknowledged, the id flag of psw is automat ically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing t he ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 ) chapter 7 interrupt/exception processing function 162 user?s manual u14492ej4v1ud figure 7-6. example of servicing in which a nother interrupt request is issued while an interrupt is bei ng serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution the values of the eipc and eipsw regi sters must be saved be fore executing multiple interrupts. when returning from multiple inte rrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. chapter 7 interrupt/exception processing function 163 user?s manual u14492ej4v1ud figure 7-6. example of servicing in which a nother interrupt request is issued while an interrupt is bei ng serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution the values of the eipc and eipsw regi sters must be saved be fore executing multiple interrupts. when returning from multiple in terrupt servicing, restor e the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority chapter 7 interrupt/exception processing function 164 user?s manual u14492ej4v1ud figure 7-7. example of servicing interr upt requests generate d simultaneously default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt requests b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. caution the values of the eipc and eipsw regi sters must be saved be fore executing multiple interrupts. when returning from multiple inte rrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remark a to c in the figure are the temporary names of in terrupt requests shown for the sake of explanation. chapter 7 interrupt/exception processing function 165 user?s manual u14492ej4v1ud 7.3.4 interrupt control register (xxicn) an interrupt control register is assigned to each in terrupt request (maskable inte rrupt) and sets the control conditions for each maskable interrupt request. this register can be read/written in 8-bit or 1-bit units. caution read the xxifn bit of the xxicn register in the interrupt disable d (di) state. otherwise if the timing of interrupt acknowledgeme nt and bit reading conflict, normal values may not be read. address fffff110h to fffff176h <7> xxifn xxicn <6> xxmkn 5 0 4 0 3 0 <2> xxprn2 <1> xxprn1 <0> xxprn0 initial value 47h bit position bit name function 7 xxifn this is an interrupt request flag. 0: interrupt request not issued 1: interrupt request issued the flag xxlfn is reset automatically by the hardware if an interrupt request is acknowledged. 6 xxmkn this is an interrupt mask flag. 0: enables interrupt servicing 1: disables interr upt servicing (pending) 8 levels of priority order ar e specified for each interrupt. xxprn2 xxprn1 xxprn0 interrupt priority specification bit 0 0 0 specifies level 0 (highest). 0 0 1 specifies level 1. 0 1 0 specifies level 2. 0 1 1 specifies level 3. 1 0 0 specifies level 4. 1 0 1 specifies level 5. 1 1 0 specifies level 6. 1 1 1 specifies level 7 (lowest). 2 to 0 xxprn2 to xxprn0 remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 ) the address and bit of each interrupt control register are as follows. chapter 7 interrupt/exception processing function 166 user?s manual u14492ej4v1ud table 7-2. addresses and bits of interrupt control registers (1/2) bit address register <7> <6> 5 4 3 <2> <1> <0> fffff110h p0ic0 p0if0 p0mk0 0 0 0 p0pr02 p0pr01 p0pr00 fffff112h p0ic1 p0if1 p0mk1 0 0 0 p0pr12 p0pr11 p0pr10 fffff114h p0ic2 p0if2 p0mk2 0 0 0 p0pr22 p0pr21 p0pr20 fffff116h p0ic3 p0if3 p0mk3 0 0 0 p0pr32 p0pr31 p0pr30 fffff118h p0ic4 p0if4 p0mk4 0 0 0 p0pr42 p0pr41 p0pr40 fffff11ah p0ic5 p0if5 p0mk5 0 0 0 p0pr52 p0pr51 p0pr50 fffff11ch p0ic6 p0if6 p0mk6 0 0 0 p0pr62 p0pr61 p0pr60 fffff11eh detic0 detif0 detmk0 0 0 0 detpr02 detpr01 detpr00 fffff120h detic1 detif1 detmk1 0 0 0 detpr12 detpr11 detpr10 fffff122h tm0ic0 tm0if0 tm0mk0 0 0 0 tm0pr02 tm0pr01 tm0pr00 fffff124h cm03ic0 cm03if0 cm03mk0 0 0 0 cm03pr02 cm03pr01 cm03pr00 fffff126h tm0ic1 tm0if1 tm0mk1 0 0 0 tm0pr12 tm0pr11 tm0pr10 fffff128h cm03ic1 cm03if1 cm03mk1 0 0 0 cm03pr12 cm03pr11 cm03pr10 fffff12ah cc10ic0 cc10if0 cc10mk0 0 0 0 cc10pr02 cc10pr01 cc10pr00 fffff12ch cc10ic1 cc10if1 cc10mk1 0 0 0 cc10pr12 cc10pr11 cc10pr1 0 fffff12eh cm10ic0 cm10if0 cm10mk0 0 0 0 cm10pr02 cm10pr01 cm10pr00 fffff130h cm10ic1 cm10if1 cm10mk1 0 0 0 cm10pr12 cm10pr11 cm10pr10 fffff132h cc11ic0 cc11if0 cc11mk0 0 0 0 cc11pr02 cc11pr01 cc11pr00 fffff134h cc11ic1 cc11if1 cc11mk1 0 0 0 cc11pr12 cc11pr11 cc11pr10 fffff136h cm11ic0 cm11if0 cm11mk0 0 0 0 cm11pr02 cm11pr01 cm11pr00 fffff138h cm11ic1 cm11if1 cm11mk1 0 0 0 cm11pr12 cm11pr11 cm11pr10 fffff13ah tm2ic0 tm2if0 tm2mk0 0 0 0 tm2pr02 tm2pr01 tm2pr00 fffff13ch tm2ic1 tm2if1 tm2mk1 0 0 0 tm2pr12 tm2pr11 tm2pr10 fffff13eh cc2ic0 cc2if0 cc2mk0 0 0 0 cc2pr02 cc2pr01 cc2pr00 fffff140h cc2ic1 cc2if1 cc2mk1 0 0 0 cc2pr12 cc2pr11 cc2pr10 fffff142h cc2ic2 cc2if2 cc2mk2 0 0 0 cc2pr22 cc2pr21 cc2pr20 fffff144h cc2ic3 cc2if3 cc2mk3 0 0 0 cc2pr32 cc2pr31 cc2pr30 fffff146h cc2ic4 cc2if4 cc2mk4 0 0 0 cc2pr42 cc2pr41 cc2pr40 fffff148h cc2ic5 cc2if5 cc2mk5 0 0 0 cc2pr52 cc2pr51 cc2pr50 fffff14ah tm3ic0 tm3if0 tm3mk0 0 0 0 tm3pr02 tm3pr01 tm3pr00 fffff14ch cc3ic0 cc3if0 cc3mk0 0 0 0 cc3pr02 cc3pr01 cc3pr00 fffff14eh cc3ic1 cc3if1 cc3mk1 0 0 0 cc3pr12 cc3pr11 cc3pr10 fffff150h cm4ic0 cm4if0 canmk2 0 0 0 cm4pr02 cm4pr01 cm4pr00 fffff152h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff154h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff156h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff158h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff15ah canic0 canif0 canmk0 0 0 0 canpr02 canpr01 canpr00 fffff15ch canic1 canif1 canmk1 0 0 0 canpr12 canpr11 canpr10 fffff15eh canic2 canif2 canmk2 0 0 0 canpr22 canpr21 canpr20 fffff160h canic3 canif3 canmk3 0 0 0 canpr32 canpr31 canpr30 fffff162h csiic0 csiif0 csimk0 0 0 0 csipr02 csipr01 csipr00 chapter 7 interrupt/exception processing function 167 user?s manual u14492ej4v1ud table 7-2. addresses and bits of interrupt control registers (2/2) bit address register <7> <6> 5 4 3 <2> <1> <0> fffff164h csiic1 csiif1 csimk1 0 0 0 csipr12 csipr11 csipr10 fffff166h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff168h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff16ah seic0 seif0 semk0 0 0 0 sepr02 sepr01 sepr00 fffff16ch sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff16eh stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff170h sric2 srif2 srmk2 0 0 0 srpr22 srpr21 srpr20 fffff172h stic2 stif2 stmk2 0 0 0 stpr22 stpr21 stpr20 fffff174h adic0 adif0 admk0 0 0 0 adpr02 adpr01 adpr00 fffff176h adic1 adif1 admk1 0 0 0 adpr12 adpr11 adpr10 chapter 7 interrupt/exception processing function 168 user?s manual u14492ej4v1ud 7.3.5 interrupt mask register s 0 to 3 (imr0 to imr3) these registers set the interrupt ma sk state for the maskable interrupts. the xxmkn bit of the imr0 to imr3 registers is equivalent to the xxmkn bit of the xxicn register. imrm can be read/written in 16-bit units (m = 0 to 3). when the imrm register is divided into two registers: higher 8 bits (imrmh register) and lower 8 bits (imrml register), these registers can be r ead/written in 8-bit or 1-bit units. caution the device file defines the xxmkn bit of th e xxicn register as a reser ved word. if a bit is manipulated with the name xxmkn, th erefore, the xxicn register, rath er than the imrm register, is rewritten (as a result, the imrm register is also rewritten). <15> cm10mk0 <7> detmk0 imr0 <14> cc10mk1 <6> p0mk6 <13> cc10mk0 <5> p0mk5 <12> cm03mk1 <4> p0mk4 <11> tm0mk1 <3> p0mk3 <10> cm03mk0 <2> p0mk2 <9> tm0mk0 <1> p0mk1 <8> detmk1 <0> p0mk0 address fffff100h initial value ffffh <15> cc3mk1 <7> cc2mk0 imr1 <14> cc3mk0 <6> tm2mk1 <13> tm3mk0 <5> tm2mk0 <12> cc2mk5 <4> cm11mk1 <11> cc2mk4 <3> cm11mk0 <10> cc2mk3 <2> cc11mk1 <9> cc2mk2 <1> cc11mk0 <8> cc2mk1 <0> cm10mk1 address fffff102h initial value ffffh <15> stmk1 <7> canmk2 imr2 <14> srmk1 <6> canmk1 <13> semk0 <5> canmk0 <12> stmk0 <4> dmamk3 <11> srmk0 <3> dmamk2 <10> csimk1 <2> dmamk1 <9> csimk0 <1> dmamk0 <8> canmk3 <0> cm4mk0 address fffff104h initial value ffffh 15 1 7 1 imr3 14 1 6 1 13 1 5 1 12 1 4 1 11 1 <3> admk1 10 1 <2> admk0 9 1 <1> stmk2 8 1 <0> srmk2 address fffff106h initial value ffffh bit position bit name function 15 to 0 (imr0 to 2), 0 to 3 (imr3) xxmkn interrupt mask flag 0: interrupt servicing enabled 1: interrupt servicing disabled (pending) remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 ) chapter 7 interrupt/exception processing function 169 user?s manual u14492ej4v1ud 7.3.6 in-service priori ty register (ispr) this register holds the priority leve l of the maskable interrupt currently a cknowledged. when an interrupt request is acknowledged, the bit of this register co rresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the inte rrupt request having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only, in 8-bit or 1-bit units. caution in the interrupt enabled (ei) state, if an interrupt is acknowle dged during the reading of the ispr register, the value of the ispr register may be r ead after the bit is set to 1 by this interrupt acknowledgement. to read the value of the ispr register properly before interrupt acknowledgement, read it in the in terrupt disabled (di) state. address fffff1fah <7> ispr7 ispr <6> ispr6 <5> ispr5 <4> ispr4 <3> ispr3 <2> ispr2 <1> ispr1 <0> ispr0 initial value 00h bit position bit name function 7 to 0 ispr7 to ispr0 indicates priority of interrupt currently acknowledged 0: interrupt request with priority n not acknowledged 1: interrupt request with priority n acknowledged remark n = 0 to 7 (priority level) chapter 7 interrupt/exception processing function 170 user?s manual u14492ej4v1ud 7.3.7 maskable interrupt status flag (id) the id flag is bit 5 of the psw and th is controls the maskable interrupt?s operating state, and stores control information regarding enabling or disabling of interrupt requests. 31 0 psw initial value 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 5 id indicates whether maskable interrupt servicing is enabled or disabled. 0: maskable interrupt request acknowledgement enabled 1: maskable interrupt request acknowledgement disabled (pending) this bit is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. non-maskable interrupt requests and e xceptions are acknowledged regardless of this flag. when a maskable interr upt is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request generated during t he acknowledgement disabled period (id = 1) is acknowledged when the xxifn bit of xxicn register is set to 1, and the id flag is reset to 0. 7.3.8 interrupt trigger mode selection the valid edge of the intpn, adtrg0, adtrg1, ti ud10, tiud11, tcud10, t cud11, tclr10, tclr11, tclr3, and ti3 pins can be selected by program. the edge that can be sele cted as the valid edge is one of the following (n = 0 to 6, 20 to 25, 30, 31, 100, 101, 110, 111). ? rising edge ? falling edge ? both the rising and falling edges when the intpn, adtrg0, adtrg1, tiud10, tiud11, tcud10, tcud11, tclr10, tclr11, tclr3, and ti3 signals are edge-detected, they become an interrupt source or capture/trigger. the valid edge is specified by exter nal interrupt mode registers 1 and 2 (i ntm1 and intm2), signal edge selection registers 10 and 11 (sesa10 and sesa11), the valid edge select ion register (sesc), and tm2 input filter mode registers 0 to 5 (fem0 to fem5). chapter 7 interrupt/exception processing function 171 user?s manual u14492ej4v1ud (1) external interrupt mode re gisters 1, 2 (intm1, intm2) these registers specify the valid edge for external interrupt requests (intp0 to intp6), input via external pins. the correspondence between each regi ster and the external interrupt reques ts that register controls is shown below. ? intm1: intp0, intp1, intp2/adtrg0, intp3/adtrg1 ? intm2: intp4 to intp6 intp2 and intp3 function alternately as adtrg0 and ad trg1 (a/d converter external trigger input). therefore, if the external trigger mode has been set by the trg0 to trg2 bits of a/d converter mode register n0 (adscmn0), setting the es20 and es21, and es30 and es31 bits of intm1 also specifies the valid edge of the external trigger input (adtrg0 and adtrg1) (n = 0, 1). the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). these registers can be read/wri tten in 8-bit or 1-bit units. 7 es31 intm1 6 es30 5 es21 4 es20 3 es11 2 es10 1 es01 0 es00 address fffff882h initial value 00h intp3/adtrg1 intp2/adtrg0 intp1 intp0 7 0 intm2 6 0 5 es61 4 es60 3 es51 2 es50 1 es41 0 es40 address fffff884h initial value 00h intp6 intp5 intp4 bit position bit name function specifies the valid edge of the intpn, adtrg0 and adtrg1 pins. esn1 esn0 operation 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 7 to 0 (intm1), 5 to 0 (intm2) esn1, esn0 (n = 0 to 6) chapter 7 interrupt/exception processing function 172 user?s manual u14492ej4v1ud (2) signal edge selection registers 10, 11 (sesa10, sesa11) these registers specify the valid edge of external interrupt requests (intp100, intp101, intp110, intp111, tiud10, tiud11, tcud10, tcud11, tclr10, and tclr11), input vi a external pins. the correspondence between each register and the exter nal interrupt requests that regi ster controls is shown below. ? sesa10: tiud10, tcud10, tclr10, intp100, intp101 ? sesa11: tiud11, tcud11, tclr11, intp110, intp111 the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). these registers can be read/wri tten in 8-bit or 1-bit units. cautions 1. the bits of the sesa1n register ca nnot be changed during tm 1n operation (tm1cen bit of timer control registers 10, 11 (tmc10, tmc11) = 1). 2. the tm1cen bit must be set (1) befo re using the tcud10/intp100, tclr10/intp101, tcud11/intp110, and tclr11/intp111 pins as intp100, intp101, intp110, and intp111, even if not using timer 1. 3. before setting the intp100, intp101, intp110, intp111, tiud 10, tiud11, tcud10, tcud11, tclr10, and tclr11 pins to the trigger mode, set the pmc1 register. if the pmc1 register is set after th e sesa10 and sesa11 registers have been set, an illegal interrupt may occur as soon as the pmc1 register is set. chapter 7 interrupt/exception processing function 173 user?s manual u14492ej4v1ud (1/2) 7 tesud01 sesa10 6 tesud00 5 cesud01 4 cesud00 3 ies1011 2 ies1010 1 ies1001 0 ies1000 address fffff5edh initial value 00h tiud10, tcud10 tclr10 intp101 intp100 7 tesud11 sesa11 6 tesud10 5 cesud11 4 cesud10 3 ies1111 2 ies1110 1 ies1101 0 ies1100 address fffff60dh initial value 00h tclr11 tiud11, tcud11 intp111 intp110 bit position bit name function specifies the valid edge of the tiud10, tiud11, tcud10, and tcud11 pins. tesudn1 tesudn0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 7, 6 tesudn1, tesudn0 cautions 1. the values set to the tesudn1 and tesudn0 bits are valid only in udc mode a note 1 and udc mode b note 1 . 2. if tm1n operation has been specified in mode 4 note 2 , the valid edge specification (tesudn1 and tesudn0 bits) for the tiud1n and tcud1n pins is invalid. specifies the valid edge of the tclr10 and tclr11 pins. cesudn1 cesudn0 valid edge 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level 5, 4 cesudn1, cesudn0 the setting values of the cesudn1 and cesudn0 bits and the operation of tm1n are as follows. 00: tm1n cleared after detection of tclr1n rising edge 01: tm1n cleared after detection of tclr1n falling edge 10: tm1n holds cleared status while tclr1n input is low level 11: tm1n holds cleared status while tclr1n input is high level caution the values set to the cesudn1 and cesudn0 bits are valid only in udc mode a note 1 . remark n = 0, 1 notes 1. see 9.2.4 (2) timer unit mode re gisters 0, 1 (tum0, tum1) 2. see 9.2.4 (6) prescaler mode regi sters 10, 11 (prm10, prm11) chapter 7 interrupt/exception processing function 174 user?s manual u14492ej4v1ud (2/2) bit position bit name function specifies the valid edge of the pin selected using the csln bit of the csl1n register (intp1n1, intp1n0). ies1n11 ies1n10 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 3, 2 ies1n11, ies1n10 specifies the valid edge of the intp100 and intp110 pins. ies1n01 ies1n00 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1, 0 ies1n01, ies1n00 1 1 both rising and falling edges remark n = 0, 1 chapter 7 interrupt/exception processing function 175 user?s manual u14492ej4v1ud (3) valid edge selection register (sesc) this register specifies the valid edge for external inte rrupt requests (intp30, intp 31, tclr3, and ti3), input via external pins. the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). this register can be read/written in 8-bit or 1-bit units. cautions 1. the tm3cae and tm3ce bits of timer control register 30 (tmc30) must be set (1) before using the ti3/tclr3/intp30 and to3/intp31 pins as intp30 and intp31, even if not using timer 3. 2. before setting the intp30, intp31, tclr3, and ti3 pins to the trigger mode, set the pmc2 register. if the pmc2 register is set after the sesc register has been set, an illegal interrupt may occur as soon as the pmc2 register is set. 7 tes31 sesc 6 tes30 5 ces31 4 ces30 3 ies311 2 ies310 1 ies301 0 ies300 address fffff689h initial value 00h ti3 tclr3 intp31 intp30 bit position bit name function 7, 6 tes31, tes30 specifies the valid edge of the intp30, intp31, tclr3, and ti3 pins. xesn1 xesn0 operation 0 0 falling edge 5, 4 ces31, ces30 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 3, 2 ies311, ies310 1, 0 tes301, tes300 remark n = 3, 30, 31 chapter 7 interrupt/exception processing function 176 user?s manual u14492ej4v1ud (4) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) these registers specify the valid edge fo r external interrupt requests input to timer 2 (intp20 to intp25). the correspondence between each r egister and the external interrupt reques t that register controls is shown below. ? fem0: intp20 ? fem1: intp21 ? fem2: intp22 ? fem3: intp23 ? fem4: intp24 ? fem5: intp25 the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). these registers can be read/wri tten in 8-bit or 1-bit units. cautions 1. the stfte bit of timer 2 clock stop re gister 0 (stopte0) must be cleared (0) before using the ti2/intp20, to21/intp21, to22 /intp22, to23/intp23, to24/intp24, and tclr2/intp25 pins as intp20, intp21, intp22, intp23, intp24, and intp25, even if not using timer 2. 2. before setting the intp2n pin to the trigge r mode, set the pmc2 register. if the pmc2 register is set after the femn register h as been set, an illegal interrupt may occur as soon as the pmc2 register is set (n = 0 to 5). chapter 7 interrupt/exception processing function 177 user?s manual u14492ej4v1ud (1/2) 7 dfen00 fem0 6 0 5 0 4 0 3 edge010 2 edge000 1 tms010 0 tms000 address fffff630h initial value 00h intp20 7 dfen01 fem1 6 0 5 0 4 0 3 edge011 2 edge001 1 tms011 0 tms001 address fffff631h initial value 00h intp21 7 dfen02 fem2 6 0 5 0 4 0 3 edge012 2 edge002 1 tms012 0 tms002 address fffff632h initial value 00h intp22 7 dfen03 fem3 6 0 5 0 4 0 3 edge013 2 edge003 1 tms013 0 tms003 address fffff633h initial value 00h intp23 7 dfen04 fem4 6 0 5 0 4 0 3 edge014 2 edge004 1 tms014 0 tms004 address fffff634h initial value 00h intp24 7 dfen05 fem5 6 0 5 0 4 0 3 edge015 2 edge005 1 tms015 0 tms005 address fffff635h initial value 00h intp25 bit position bit name function 7 dfen0n specifies the filter of the intp2n pin. 0: analog filter 1: digital filter caution when the dfen0n bit = 1, the sam pling clock of the digital filter is f xxtm2 (clock of tm20 and tm21 selected by prm02 register). specifies the valid edge of the intp2n pin. edge01n edge00n operation 0 0 interrupt by intcc2n note 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges 3, 2 edge01n, edge00n note set when intcc2n is selected by a match between tm20, tm21 and the sub- channel compare register (s pecified by the tms01n, tms00n bits) (n = 0 to 5). remark n = 0 to 5 chapter 7 interrupt/exception processing function 178 user?s manual u14492ej4v1ud (2/2) bit position bit name function selects the capture input note . tms01n tms00n operation 0 0 used as a pin 0 1 digital filter (noise eliminator specification) 1 0 timer-based captur e to sub-channel 1 1 1 timer-based captur e to sub-channel 2 1, 0 tms01n, tms00n note selection of capture input based on intcm100 and intcm101 is valid only for the fem1 and fem2 registers. set the tms01m and tms00m bits of t he femm register to 00b or 01b. all other settings are prohibited (m = 1, 3 to 5). sub-channels 1 and 2 of timer 2 can be captured by intp21, intp22, and intcm100, intcm101. an example is given below. (a) when sub-channel 1 is captured by intcm101 fem1 register = xxxxxx10b tmic0 register = 00000010b (b) when sub-channel 2 is captured by intcm101 fem2 register = xxxxxx11b tmic0 register = 00001000b remark n = 0 to 5 chapter 7 interrupt/exception processing function 179 user?s manual u14492ej4v1ud 7.4 software exception a software exception is generated when the cpu ex ecutes the trap instru ction, and can be always acknowledged. 7.4.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfe rs control to the handler routine. (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). (4) sets the ep and id bits of the psw. (5) sets the handler address (00000040h or 00000050h) corre sponding to the software exception to the pc, and transfers control. figure 7-8 illustrates the processi ng of a software exception. figure 7-8. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (the vector is a value from 00h to 1fh.) the handler address is determined by the trap instruction?s operand (vector). if the vector is 00h to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h. chapter 7 interrupt/exception processing function 180 user?s manual u14492ej4v1ud 7.4.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instru ction, the cpu carries out the following pr ocessing and shifts control to the restored pc?s address. (1) loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. (2) transfers control to the address of the restored pc and psw. figure 7-9 illustrates the processi ng of the reti instruction. figure 7-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is n ecessary to set psw.ep back to 1 using the ldsr instruction immediately befo re the reti instruction. remark the solid lines show the cpu processing flow. chapter 7 interrupt/exception processing function 181 user?s manual u14492ej4v1ud 7.4.3 exception status flag (ep) the ep flag is bit 6 of psw, and is a status flag used to indica te that exception processing is in progress. it is set when an exception occurs. 31 0 psw initial value 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 6 ep shows that exception processing is in progress. 0: exception processing not in progress. 1: exception processing in progress. chapter 7 interrupt/exception processing function 182 user?s manual u14492ej4v1ud 7.5 exception trap an exception trap is an interrupt that is requested when an illegal ex ecution of an instruction takes place. in the v850e/ia1, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 7.5.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an in struction applicable to this illegal instruction is executed. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution since it is possible to assign this instru ction to an illegal opcode in the future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the follo wing processing, and transfers control to the handler routine. (1) saves the restored pc to dbpc. (2) saves the current psw to dbpsw. (3) sets the np, ep, and id bits of the psw. (4) sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. figure 7-10 illustrates the proce ssing of the exception trap. chapter 7 interrupt/exception processing function 183 user?s manual u14492ej4v1ud figure 7-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore recovery from an exception trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. (1) loads the restored pc and psw from dbpc and dbpsw. (2) transfers control to the address indicated by the restored pc and psw. figure 7-11 illustrates the restore pr ocessing from an exception trap. figure 7-11. restore processing from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc chapter 7 interrupt/exception processing function 184 user?s manual u14492ej4v1ud 7.5.2 debug trap the debug trap is an exception that can be acknowledged every time and is generated by exec ution of the dbtrap instruction. when the debug trap is generat ed, the cpu performs the following processing. (1) operation (1) saves the restored pc to dbpc. (2) saves the current psw to dbpsw. (3) sets the np, ep and id bits of the psw. (4) sets the handler address (00000060h) corresponding to the debug trap to the pc and transfers control. figure 7-12 illustrates the pr ocessing of the debug trap. figure 7-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h debug monitor routine processing cpu processing chapter 7 interrupt/exception processing function 185 user?s manual u14492ej4v1ud (2) restore restoration from a debug trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. (1) loads the restored pc and psw from dbpc and dbpsw. (2) transfers control to the address i ndicated by the restored pc and psw. figure 7-13 illustrates the processi ng for restoring from a debug trap. figure 7-13. processing for restoring from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc chapter 7 interrupt/exception processing function 186 user?s manual u14492ej4v1ud 7.6 multiple interrupt servicing control multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be interrupted during servicing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is acknowledged and serviced first. if there is an interrupt request with a lower priority leve l than the interrupt request cu rrently being serviced, that interrupt request is held pending. maskable interrupt multiple servicing control is executed when interrupts are enabled (id = 0). thus, if multiple interrupts are executed, it is necessary for interrupts to be enabled (id = 0) even during an in terrupt servicing routine. if a maskable interrupt or a software e xception is generated in a maskable inte rrupt or software exception service program, it is necessary to save eipc and eipsw. this is accomplished by the following procedure. (1) acknowledgement of maskable interrupts in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (inte rrupt acknowledgement enabled) ... ... maskable interrupt acknowledgement ... ... ? di instruction (interr upt acknowledgement disabled) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction chapter 7 interrupt/exception processing function 187 user?s manual u14492ej4v1ud (2) generation of exception in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ... ? trap instruction exception such as trap instruction acknowledged. ... ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction the priority order for multiple interr upt servicing control has 8 levels, fr om 0 to 7 for each maskable interrupt request (0 is the highest priority), but it can be set as desired via software. setting of the priority order level is done using the xxprn0 to xxprn2 bits of the interrupt request control regist er (xxlcn), which is provided for each maskable interrupt request. after system reset, an interrupt request is masked by the xxmkn bit and the priority order is set to level 7 by the xxprn0 to xxprn2 bits. the priority order of maskable interrupts is as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been sus pended as a result of multiple servic ing control is resumed after the servicing of the higher priority interrupt has been co mpleted and the reti instru ction has been executed. a pending interrupt request is acknowledged after the cu rrent interrupt servici ng has been completed and the reti instruction has been executed. caution in a non-maskable interrupt servicing routin e (time until the reti instruction is executed), maskable interrupts are susp ended and not acknowledged. 7.7 interrupt response time the following table describes the v850e/ia 1 interrupt response time (from interr upt generation to start of interrupt servicing). chapter 7 interrupt/exception processing function 188 user?s manual u14492ej4v1ud figure 7-14. pipeline operation at inte rrupt request acknowledgement (outline) internal clock instruction 1 instruction 2 interrupt acknowledgement operation instruction (start instruction of interrupt servicing routine) interrupt request if id ex df wb ifx idx 4 system clocks if interleave access note if id ex int1 int2 int3 int4 if ifx note for details of interleave access, refer to 8.1.2 2-clock branch in v850e1 architecture user?s manual (u14559e) . remark int1 to int4: interrupt acknowledgement processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt response time (internal system clock (f xx )) external interrupt internal interrupt intp0 to intp6, intp20 to intp25 intp20 to intp25 intp100, intp101, intp110, intp111 intp30, intp31 condition minimum 4 4 + analog delay time 4 + digital noise filter 4 + note 1 + digital noise filter maximum 7 note 2 7 + analog delay time 7 + digital noise filter 7 + note 1 + digital noise filter the following cases are exceptions. ? in idle/software stop mode ? external bus access ? two or more interrupt request non-sampling instructions are executed in succession ? access to on-chip peripheral i/o register ? access to programmable peripheral i/o register notes 1. the number of internal system clocks are as follows. ? for timers 10, 11 (tm10, tm11) using intp 100, intp101, intp110, and intp111 as external interrupt inputs (see 9.2.4 (1) timer 1/timer 2 cl ock selection register (prm02) ): f clk = f xx /2 (prm2 bit = 1): 2 f clk = f xx /4 (prm2 bit = 0): 4 ? for timer 3 (tm3) using intp30 and intp31 as external interrupt inputs (see 9.4.4 (1) timer 3 clock selection register (prm03) ): f clk = f xx (prm3 bit = 1): 2 f clk = f xx /2 (prm3 bit = 0): 4 2. when ld instruction is executed to internal rom (during align access) chapter 7 interrupt/exception processing function 189 user?s manual u14492ej4v1ud 7.8 periods in which interrupts are not acknowledged an interrupt is acknowledged while an instruction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sampli ng instruction and the next instruct ion (interrupt is held pending). the interrupt request non-sampling instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the load, store, and bit mani pulation instructions for the interrupt control register ( xxlcn), in-service priority register (ispr), power save control register (psc), and interrupt mask registers 0 to 3 (imr0 to imr3) ? the store instruction for the command register (prcmd) ? the load, store, and bit mani pulation instructions for t he registers related to csi 190 user?s manual u14492ej4v1ud chapter 8 clock generation function the clock generator (cg) generates and controls the internal system clock (f xx ) that is supplied to each internal unit, such as the cpu. 8.1 features ? multiplier function using a phase locked loop (pll) synthesizer ? clock sources ? oscillation by connecting a resonator ? external clock ? power saving modes ? halt mode ? idle mode ? software stop mode ? internal system clock output function 8.2 configuration x1 x2 clock generator (cg) cksel (f x ) cpu, on-chip peripheral i/o time base counter (tbc) clkout f xx remark f x : external resonator or external clock frequency f xx : internal system clock chapter 8 clock generation function 191 user?s manual u14492ej4v1ud 8.3 input clock selection the clock generator consists of an oscillator and a pll synthesizer. for example, connecting a 5.0 mhz crystal resonator or ceramic resonator to pins x1 an d x2 enables a 50 mhz internal system clock (f xx ) to be generated when the multiplier is 10. also, an external clock can be input di rectly to the oscillator. in this case, the clock signal should be input only to pin x1 (pin x2 should be left open). two bas ic operation modes are provi ded for the clock generator. these are pll mode and direct mode. the operation mode is selected by the cksel pin. the input to this pin is latched on reset. cksel operating mode 0 pll mode 1 direct mode caution the input level for the cksel pin must be fixed. if it is switched during operation, a malfunction may occur. 8.3.1 direct mode in direct mode, an external clock is divided by two and the divided clock is supplied as the internal system clock. the maximum frequency that can be input in direct mode is 50 mhz. the v850e/ia1 is mainly used in application systems in which operates at relatively low frequencies. caution in direct mode, an exter nal clock must be input (an ex ternal resonator should not be connected). 8.3.2 pll mode in pll mode, an external resonator is connected or external clock is input and multiplied by the pll synthesizer. the multiplied pll output is divided by the division ratio s pecified by the clock control register (ckc) to generate a system clock that is 10, 5, 2. 5, or 1 times the frequency (f x ) of the external resonator or external clock. after reset, an internal system clock (f xx ) that is 1 time the frequency (1 f x ) of the input clock frequency (f x ) is generated. when a frequency that is 10 times (10 f x ) the input clock frequency (f x ) is generated, a system with low noise and low power consumption can be realized because a frequency of up to 50 mhz is obtained based on a 5 mhz external resonator or external clock. in pll mode, if the clock supply from an external resonator or external clock source stops, operation of the internal system clock (f xx ) based on the self-propelled frequency of the clock gen erator?s internal voltage controlled oscillator (vco) continues. in this case, f xx is undefined. however, do not devise an application method expecting to use this self-propelled frequency. example: clocks when pll mode (f xx = 10 f x ) is used internal system clock frequency (f xx ) external resonator or external clock frequency (f x ) 50.000 mhz 5.0000 mhz 40.000 mhz 4.0000 mhz chapter 8 clock generation function 192 user?s manual u14492ej4v1ud caution when using the pll mode, only an f x (4 to 5 mhz) value for which 10 f x does not exceed the system clock maximum frequency (50 mhz) can be used for the oscillation frequency or external clock frequency. when 5 f x , 2.5 f x , or 1 f x is used, a frequency of 4 to 6.4 mhz can be used. remark note the following when pll mode is selected (f xx = 5 f x , f xx = 2.5 f x , or f xx = 1 f x ) if the v850e/ia1 need not be oper ated at high frequency, use f xx = 5 f x , f xx = 2.5 f x , or f xx = 1 f x to reduce the power consumption by loweri ng the system clock frequency using software. 8.3.3 peripheral command register (phcmd) this is an 8-bit register that is used to set protection for writing to registers that can significantly affect the system so that the application system is not halted unexpectedly due to erroneous program execution. this register can be written only in 8-bit units (when it is read, undefined data is read out). writing to the first specific register (ckc or flpmc regist er) is only valid after first writing to the phcmd register. because of this, the register value can be overwritten on ly with the specified sequence, preventing an illegal write operation from being performed. 7 6 5 4 3 2 1 0 address initial value phcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 fffff800h undefined bit position bit name function 7 to 0 reg7 to reg0 registration code (arbitrary 8-bit data) the specific registers targeted are as follows. ? clock control register (ckc) ? flash programming mode control register (flpmc) the generation of an illegal store oper ation can be checked with the prerr bi t of the peripheral status register (phs). chapter 8 clock generation function 193 user?s manual u14492ej4v1ud 8.3.4 clock control register (ckc) the clock control register is an 8-bit register that controls the internal system clock (f xx ) in pll mode. it can be written to only by a specific sequence co mbination so that it cannot easily be ov erwritten by mistake due to erroneous program execution. this register can be read/written in 8-bit units. caution do not change bits ckdi v2 to ckdiv0 in direct mode. 7 6 5 4 3 2 1 0 address initial value ckc 0 0 tbcs cesel 0 ckdiv2 ckdiv1 ckdiv0 fffff822h 00h bit position bit name function 5 tbcs selects the time base counter clock. 0: f x /2 8 1: f x /2 9 for details, see 8.6.2 time base counter (tbc) . 4 cesel specifies the functions of the x1 and x2 pins. 0: a resonator is connected to the x1 and x2 pins 1: an external clock is connected to the x1 pin when cesel = 1, the oscillator feedback loop is disconnected to prevent current leak in software stop mode. sets the internal sy stem clock frequency (f xx ) when pll mode is used. ckdiv2 ckdiv1 ckdiv0 internal system clock (f xx ) 0 0 0 f x 0 0 1 2.5 f x 0 1 1 5 f x 1 1 1 10 f x other than above setting prohibited 2 to 0 ckdiv2 to ckdiv0 caution when changing the internal system clock during operation, be sure to set the clock to be changed after setting the ckdiv2 to ckdiv0 bits to 000 (f x ). example clock generator settings ckc register operation mode cksel pin ckdiv2 ckdiv1 ckdiv0 input clock (f x ) internal system clock (f xx ) direct mode high-level input 0 0 0 16 mhz 8 mhz 0 0 0 5 mhz 5 mhz 0 0 1 5 mhz 12.5 mhz 0 1 1 5 mhz 25 mhz pll mode low-level input 1 1 1 5 mhz 50 mhz other than above setting pr ohibited setting prohibited chapter 8 clock generation function 194 user?s manual u14492ej4v1ud data is set in the clock control register (ckc) according to the following sequence. <1> disable interrupts (set the np bit of psw to 1). <2> prepare data in any one of the general-purpose registers to set in the specific register. <3> write arbitrary data to the per ipheral command register (phcmd). <4> set the clock control register (c kc) (with the following instructions). ? store instruction (st/sst instruction) <5> insert five or more nop instructions (5 inst ructions (<5> to <9>)) <10> release the interrupt disabled st ate (set the np bit of psw to 0). [sample coding] <1> ldsr rx, 5 <2> mov 0x07, r10 <3> st.b r10, phcmd [r0] <4> st.b r10, ckc [r0] <5> nop <6> nop <7> nop <8> nop <9> nop <10> ldsr ry, 5 remark rx: value written to psw ry: value returned to psw no special sequence is required to read the specific register. cautions 1. if an interrupt is ac knowledged between the issuing of da ta to the phcmd (<3>) and writing to the specific register immediately after (<4>), the write ope ration to the specific register is not performed and a protection e rror (the prerr bit of the phs register = 1) may occur. therefore, set the np bit of the psw to 1 (<1> ) to disable interrupt acknowledgement. also disable interrupt acknowledgement as well when selecting a bit manipulation instruction for the specific register setting. 2. although the data written to the phcmd register is dummy data however, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the phcmd register (<3>). the same method should be a pplied when using a general- purpose register for addressing. 3. before executing this processing, complete all dma transfer operations. chapter 8 clock generation function 195 user?s manual u14492ej4v1ud 8.3.5 peripheral status register (phs) if a write operation is not performed in the correct sequence including access to the command register for the protection-targeted internal registers, writing is not performed and a protecti on error is generated, setting the status flag (prerr) to 1. this flag is a cumula tive flag. after checking the prerr flag, it is cleared to 0 by an instruction. this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 <0> address initial value phs 0 0 0 0 0 0 0 prerr fffff802h 00h bit position bit name function 0 prerr protection error 0: protection error does not occur 1: protection error occurs the operation conditions of the prerr flag are as follows. set conditions: <1> if the operation of the relevant store instruction for the on-chip peripheral i/o is not a write operation for the phcmd register, but the peri pheral specific register is written to. <2> if the first store instruction operation after the write operation to the phcmd register is for memory other than the specific registers and on-chip peripheral i/o. reset conditions: <1> if the prerr flag of the phs register is set to 0. <2> if the system is reset chapter 8 clock generation function 196 user?s manual u14492ej4v1ud 8.4 pll lockup the lockup time (frequency stabilization time) is the time from when the power is turned on or the software stop mode is released until the phas e locks at the prescribed frequency. the state until this stab ilization occurs is called a lockup state, and the stabilized state is called a lock state. (1) lock register (lockr) the lock register (lockr) has a lock flag that re flects the stabilized state of the pll frequency. this register is read-only, in 8-bit or 1-bit units. caution when the pll is locked, the lock flag is 0. if the system then enters an unlocked state due to a standby, the lock flag becomes 1. if anything othe r than a standby causes the system to enter an unlocked state, the lock flag is not affected (lock = 0). 7 6 5 4 3 2 1 <0> address initial value lockr 0 0 0 0 0 0 0 lock fffff824h 0000000xb bit position bit name function 0 lock this is a read-only flag that indicates the pll state. this flag holds the value 0 as long as a lockup state is maintained and is not initialized by a system reset. 0: indicates that the pll is locked. 1: indicates that the pll is not locked (unlock state). if the clock stops, the power fails, or some other factor operates to cause an unlock state to occur, for control processing that depends on software execution speed, such as real-time processing, be sure to judge the lock flag using software immediately after operation begins so that processing does not begin until after the clock stabilizes. on the other hand, static processing such as the setting of internal hardware or the initialization of register data or memory data can be executed without wa iting for the lock flag to be reset. the relationship between the oscillation stabilization time (the time from when t he resonator starts to oscillate until the input waveform stabilizes) when a resonator is used, and the pll lockup time (the time until frequency stabilizes) is shown below. oscillation stabilization time < pll lockup time chapter 8 clock generation function 197 user?s manual u14492ej4v1ud 8.5 power save control 8.5.1 overview the power save function has the following three modes. (1) halt mode in this mode, the clock generator (oscillator and p ll synthesizer) continues to operate, but the cpu?s operation clock stops. since the supply of clocks to on-chip peripheral functions other than the cpu continues, operation continues. t he power consumption of the overall system can be reduced by intermittent operation that is achieved due to a combinat ion of halt mode and normal operation mode. the system is switched to halt mode by a specific instruct ion (the halt instruction). (2) idle mode in this mode, the clock generator (oscillator and pll synthesizer) continues to operate, but the supply of internal system clocks is stopped, which causes the overall system to stop. when the system is released from idle mode, it can be switched to normal operation mode quickly because the oscillator?s oscillation stabi lization time need not be secured. the system is switched to idle mode acco rding to the psmr register setting. idle mode is located midway between software stop mode and halt mode in relation to the clock stabilization time and current consumption. it is used fo r situations in which a low current consumption mode is to be used and the clock stabilization time is to be eliminated after the mode is released. (3) software stop mode in this mode, the overall system is stopped by stopping the clock generator (oscillator and pll synthesizer). the system enters an ultra-low pow er consumption state in which only leak current is lost. the system is switched to software stop mode according to a psmr register setting. (a) pll mode the system is switched to software stop mode by se tting the register according to software. the pll synthesizer?s clock output is stopped at the same ti me that the oscillator is stopped. after software stop mode is released, the oscillator?s oscillation stabilization time must be secured until the system clock stabilizes. also, pll lockup time may be required depending on the program. when a resonator or external clock is connected, following the rel ease of the software stop mode, execution of the program is started after the count time of the time base counter has elapsed. (b) direct mode to stop the clock, set the x1 pin to low level. afte r the release of software st op mode, execution of the program is started after the count time of the time base counter has elapsed. chapter 8 clock generation function 198 user?s manual u14492ej4v1ud table 8-1 shows the operation of t he clock generator in normal operation mode, halt mode, idle mode, and software stop mode. an effective low power consumption system can be re alized by combining these modes and switching modes according to the required use. figure 8-1. power save mode state transition diagram note intpn (n = 0 to 6, 20 to 25) however, when a digital filter using clock sampli ng is selected as the noise eliminator for intp20 to intp25, the software stop or idle mode cannot be released. normal operation mode software stop mode set stop mode idle mode set idle mode release according to reset, nmi, or maskable interrupt note set halt mode release according to reset, nmi, or maskable interrupt halt mode release according to reset, nmi, or maskable interrupt note chapter 8 clock generation function 199 user?s manual u14492ej4v1ud table 8-1. clock generator oper ation using power save control clock source power save mode oscillator pll synthesizer clock supply to peripheral i/o clock supply to cpu normal operation halt mode ? idle mode ? ? oscillation with resonator software stop mode ? ? ? ? normal operation ? halt mode ? ? idle mode ? ? ? pll mode external clock software stop mode ? ? ? ? normal operation ? ? halt mode ? ? ? idle mode ? ? ? ? direct mode external clock software stop mode ? ? ? ? remark : operating ? : stopped chapter 8 clock generation function 200 user?s manual u14492ej4v1ud 8.5.2 control registers (1) power save mode register (psmr) this is an 8-bit register that controls power save m ode. it is effective only when the stb bit of the psc register is set to 1. writing to the psmr register is exec uted by the store instruction (st/sst instruction) and a bit manipulation instruction (set1/clr1 /not1 instruction). this register can be read/written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 <0> address initial value psmr 0 0 0 0 0 0 0 psm fffff820h 00h bit position bit name function 0 psm specifies idle mode or software stop mode. 0: switches the system to idle mode 1: switches the system to software stop mode (2) command register (prcmd) this is an 8-bit register that is us ed to set protection for write operations to registers that can significantly affect the system so that the a pplication system is not halted unexpectedl y due to erroneous program execution. writing to the first spec ific register (power save control register (psc)) is only valid after first writing to the prcmd register. because of this, the r egister value can be overwri tten only by the specified sequence, preventing an illegal writ e operation from being performed. this register can only be written in 8-bit uni ts. the undefined data is read out if read. 7 6 5 4 3 2 1 0 address initial value prcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 fffff1fch undefined bit position bit name function 7 to 0 reg7 to reg0 registration code (arbitrary 8-bit data) the specific register targeted is t he power save control register (psc). chapter 8 clock generation function 201 user?s manual u14492ej4v1ud (3) power save control register (psc) this is an 8-bit register that controls the power save function. this register, which is one of the specific registers, is effective only when accessed by a specific sequence duri ng a write operation. this register can be read/written in 8-bit or 1-bit units. caution it is impossible to set stb bit and nmim or intm bit at the same time. be sure to set stb bit after setting nmim or intm bit. 7 6 <5> <4> 3 2 <1> 0 address initial value psc 0 0 nmim intm 0 0 stb 0 fffff1feh 00h bit position bit name function 5 nmim this is the enable/disable setting bit for standby mode release using valid edge input of nmi. 0: enables nmi cancellation 1: disables nmi cancellation 4 intm this is the enable/disable setting for st andby mode release using an unmasked maskable interrupt (intpn) (n = 0 to 6, 20 to 25, 30, 31, 100, 101, 110, 111). 0: enables maskable interrupt cancellation 1: disables maskable interrupt cancellation 1 stb indicates the standby mode status. if 1 is written to this bit, the system ent ers idle or software stop mode (set by the psm bit of the psmr register). when standby mode is released, this bit is automatically reset to 0. 0: standby mode is released 1: standby mode is in effect data is set in the power save control regist er (psc) according to the following sequence. <1> set the power save mode register ( psmr) (with the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <2> prepare data in any one of the general-purpose registers to set in the specific register. <3> write arbitrary data to the command register (prcmd). <4> set the power save control register (psc) (with the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> insert the nop instructions (5 instructions (<5> to <9>). chapter 8 clock generation function 202 user?s manual u14492ej4v1ud [sample coding] <1> st.b r11, psmr [r0] ; set psmr register <2> mov 0x07, r10 ; prepare data for setting specific register in arbitrary general-purpose register <3> st.b r10, prcmd [r0] ; write prcmd register <4> st.b r10, psc [r0] ; set psc register <5> nop ; dummy instruction <6> nop ; dummy instruction <7> nop ; dummy instruction <8> nop ; dummy instruction <9> nop ; dummy instruction (next instruction) ; execution routine after software stop mode and idle mode release no special sequence is required to read the specific register. cautions 1. a store instruction for the command regi ster does not acknowledge in terrupts. this coding is made on assumption that <3> and <4> above are executed by the program with consecutive store instructions. if another inst ruction is set between <3> and <4>, the above sequence may become in effectiv e when the interrupt is ackno wledged by that instruction, and a malfunction of the program may result. 2. although the data written to the prcmd regi ster is dummy data, u se the same register as the general-purpose register used in specific register setting (< 4>) for writing to the prcmd register (<3>). the same method should be applied when using a general-purpose register for addressing. 3. at least 5 nop instructions must be inserted after executi ng a store instruction to the psc register to set software stop or idle mode. 4. before executing this processing, complete all dma transfer operations. chapter 8 clock generation function 203 user?s manual u14492ej4v1ud 8.5.3 halt mode (1) setting and operation status in halt mode, the clock generator (oscillator and pll synthesizer) continues to op erate, but the operation clock of the cpu is stopped. sinc e the supply of clocks to on-chip pe ripheral i/o units other than the cpu continues, operation continues. t he power consumption of the overall system can be reduced by setting the system to halt mode while the cpu is idle. the system is switched to halt mode by the halt instruction. although program execution stops in halt mode, the contents of all regi sters, internal ram, and ports are maintained in the state they were in immediately bef ore halt mode began. also, operation continues for all on-chip peripheral i/o units (other than ports) that do not depend on cpu instruction processing. table 8-2 shows the status of each hardware unit in halt mode. table 8-2. operation status in halt mode function operation status clock generator operating internal system clock operating cpu stopped ports maintained on-chip peripheral i/o (e xcluding ports) operating internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are maintained in the state they were in immediately before halt mode began. ad0 to ad15 a16 to a23 rd, astb uwr, lwr cs0 to cs7 hldrq hldak wait operating clkout clock output chapter 8 clock generation function 204 user?s manual u14492ej4v1ud (2) release of halt mode halt mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (intpn), or reset pin input (n = 0 to 6, 20 to 25, 30, 31, 100, 101, 110, 111). (a) release by a non-maskable interrupt request or an unmasked maska ble interrupt request halt mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority. however, if the system is set to halt mode during an interrupt servicing routine, operation will differ as follows. (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being serviced, halt mode is released, but the newly generated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt reques t that is currently being servic ed, halt mode is released and the newly generated interrupt request is acknowledged. table 8-3. operation after halt mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction (b) release by reset pin input this is the same as a normal reset operation. chapter 8 clock generation function 205 user?s manual u14492ej4v1ud 8.5.4 idle mode (1) setting and operation status in idle mode, the clock generator (oscillator and pll sy nthesizer) continues to oper ate, but the supply of internal system clocks is stopped which c auses the overall system to stop. when idle mode is released, the system can be swit ched to normal operation mode quickly because the oscillator?s oscillation stabilization time or the pll lockup time need not be secured. the system is switched to idle mode by setting the psc or psmr register using a store instruction (st or sst instruction) or a bit manipulation instruct ion (set1, clr1, or not1 instruction) (see 8.5.2 control registers ). in idle mode, program execution is stopped, and the c ontents of all registers, internal ram, and ports are maintained in the state they were in immediately be fore execution stopped. the operation of on-chip peripheral i/o units (excluding ports) also is stopped. table 8-4 shows the status of each hardware unit in idle mode. table 8-4. operation status in idle mode function operation status clock generator operating internal system clock stopped cpu stopped ports maintained on-chip peripheral i/o (excluding ports) stopped note internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are maintained in the state they were in immediately before idle mode began. ad0 to ad15 a16 to a23 high impedance rd uwr, lwr cs0 to cs7 high-level output hldak high impedance hldrq wait input (no sampling) astb high-level output clkout low-level output note nbd cannot be used in idle mode. chapter 8 clock generation function 206 user?s manual u14492ej4v1ud (2) release of idle mode idle mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (intpn) note , or reset pin input (n = 0 to 6, 20 to 25). note when a digital filter using clock sampling is select ed as the noise eliminator for intp20 to intp25, the idle mode cannot be released. (a) release by a non-maskable interrupt request or an unmasked maska ble interrupt request the idle mode can be released by an interrupt reques t only when transition to idle mode is performed with the intm and nmim bits of the psc register set to 0. idle mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request (intpn) regardless of the priority. however, if the system is set to idle mode during a maskable interrupt servicing routine, operation will differ as follows (n = 0 to 6, 20 to 25). (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being serviced, idle mode is released, but the newly generated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt reques t that is currently being servic ed, idle mode is released and the newly generated interrupt request is acknowledged. table 8-5. operation after idle mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction if the system is set to idle mode during an nmi se rvicing routine, idle mode is released, but the interrupt is not acknowledged (interrupt is held pending). interrupt servicing that is started when idle mode is released by nmi pin input is handled in the same way as normal nmi interrupt servicing that occurs during an emergency (because the nmi interrupt handler address is unique). therefor e, when a program must be able to distinguish between these two situations, a software status mu st be prepared in advance and that status must be set before setting the psmr register using a store instruction or a bi t manipulation instruction. by checking for this status during nmi interrupt servicing, an ordinar y nmi can be distinguished from the processing that is started when idle mode is released by nmi pin input. (b) release by reset pin input this is the same as a normal reset operation. chapter 8 clock generation function 207 user?s manual u14492ej4v1ud 8.5.5 software stop mode (1) setting and operation status in software stop mode, the clock generator (oscillator and pll synthesizer) is stopped. the overall system is stopped, and ultra-low power consumption is achieved in which only leak current is lost. the system is switched to software st op mode by using a store instructi on (st or sst instruction) or bit manipulation instruction (set1, clr1, or not1 in struction) to set the psc and psmr registers (see 8.5.2 control registers ). when pll mode and resonator connection mode (cesel bit of ckc register = 0) are used, the oscillator?s oscillation stabilization time must be secu red after software stop mode is released. in both pll and direct modes, following the release of software stop mode, exec ution of the program is started after the count time of the time base counter has elapsed. although program execution stops in so ftware stop mode, the contents of all registers, internal ram, and ports are maintained in the state they were in im mediately before software stop mode began. the operation of all on-chip peripheral i/o uni ts (excluding ports) is also stopped. table 8-6 shows the status of each hardware unit in software stop mode. table 8-6. operation stat us in software stop mode function operation status clock generator stopped internal system clock stopped cpu stopped ports retained note 1 on-chip peripheral i/o (excluding ports) stopped note 2 internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are retained in the state before software stop mode has been set note 1 . ad0 to ad15 a16 to a23 high impedance rd uwr, lwr cs0 to cs7 high-level output hldak high impedance hldrq wait input (no sampling) astb high-level output clkout low-level output notes 1. when the v dd5 value is within the operable range. ho wever, even if it drops below the minimum operable voltage, as long as the data retention voltage v dddr is maintained, the contents of only the internal ram will be retained. 2. nbd cannot be used in software stop mode. chapter 8 clock generation function 208 user?s manual u14492ej4v1ud (2) release of software stop mode software stop mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (intpn) note , or reset pin input. also, to release software stop mode when pll mode (cksel pin = low level) and resonator connection mode (cesel bit of ckc register = 0) are used, the oscillator?s oscillation stabilization time must be secured (n = 0 to 6, 20 to 25). moreover, pll lockup time may be required depending on the program. see 8.4 pll lockup for details. note when a digital filter using clock sampling is select ed as the noise eliminator for intp20 to intp25, the software stop mode cannot be released. (a) release by a non-maskable interrupt request or an unmasked maska ble interrupt request the software stop mode can be released by an interru pt request only when transition to software stop mode is performed with the intm and nmim bits of the psc register set to 0. software stop mode is released by a non-maska ble interrupt request or by an unmasked maskable interrupt request (intpn) regardless of the priority. however, if the system is set to software stop mode during a maskable interrupt servicing routine, oper ation will differ as follows (n = 0 to 6, 20 to 25). (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being serviced, software stop mode is released, but the newly gen erated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt request that is currently being serviced, software stop mode is released and the newly generated interrupt request is acknowledged. table 8-7. operation after software stop mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction if the system is set to software stop mode during an nmi servicing routine, software stop mode is released, but the interrupt is not ackn owledged (interrupt is held pending). interrupt servicing that is started when software st op mode is released by nmi pin input is handled in the same way as normal nmi interrupt servicin g that occurs during an emergency (because the nmi interrupt handler address is unique). therefor e, when a program must be able to distinguish between these two situations, a software status mu st be prepared in advance and that status must be set before setting the psmr register using a store in struction or a bit manipulation instruction. by checking for this status during nmi interrupt se rvicing, an ordinary nmi can be distinguished from the servicing that is started when software stop mode is released by nmi pin input. (b) release by reset pin input this is the same as a normal reset operation. chapter 8 clock generation function 209 user?s manual u14492ej4v1ud 8.6 securing oscillation stabilization time 8.6.1 oscillation stabilizatio n time security specification two specification methods can be used to secure the ti me from when software stop mode is released until the stopped oscillator stabilizes. (1) securing the time using an on-chip time base counter software stop mode is released when a valid edge is input to the nmi pin or a maskable interrupt request is input (intpn). when a valid edge is input to the pin ca using the start of oscillat ion, the time base counter (tbc) starts counting, and the time until the clock output from the oscillator stabilizes is secured during that counting time (n = 0 to 6, 20 to 25). oscillation stabilization time = tbc counting time after a fixed time, internal system clock output be gins, and processing branches to the nmi interrupt or maskable interrupt (intpn) handler address. oscillation waveform (x2) set software stop mode oscillator is stopped clkout (output) internal main clock stop state nmi (input) note time base counter?s counting time note valid edge: when specified as the rising edge. the nmi pin should usually be set to an inactive level (for example, high level when the valid edge is specified as the falling edge) in advance. software stop mode is immediately released if an operat ion is performed according to nmi valid edge input or maskable interrupt request input (intpn) timing in which software stop mode is set until the cpu acknowledges the interrupt. if direct mode or external clock connection mode (cesel bit of ckc register = 1) is used, program execution begins after the count time of the time base counter has elapsed. also, even if pll mode and resonato r connection mode (cesel bit of ckc register = 0) are used, program execution begins after the oscillation stabilization time is secured according to the time base counter. chapter 8 clock generation function 210 user?s manual u14492ej4v1ud (2) securing the time according to th e signal level width (reset pin input) software stop mode is released due to falling edge input to the reset pin. the time until the clock output from t he oscillator stabilizes is secured acco rding to the low level width of the signal that is input to the pin. the supply of internal system clocks begins after a rising edge is input to the reset pin, and processing branches to the handler addr ess used for a system reset. oscillation waveform (x2) set software stop mode oscillator is stopped internal main clock stop state internal system reset signal oscillation stabilization time secured by reset reset (input) undefined clkout (output) undefined 8.6.2 time base counter (tbc) the time base counter (tbc) is used to secure the oscillator?s oscillation stabilization time when software stop mode is released. when an external clock is connected (cesel bit of ckc regi ster = 1) or a resonator is connected (pll mode and cesel bit of ckc register = 0), the tbc counts the o scillation stabilization time after software stop mode is released, and program execution begi ns after the count is completed. the tbc count clock is selected according to the tbcs bit of the ckc register, and the next counting time can be set. table 8-8. counting time examples (f xx = 10 f x ) counting time tbcs bit count clock f x = 4.0000 mhz f x = 5.0000 mhz 0 f x /2 8 16.4 ms 13.2 ms 1 f x /2 9 32.8 ms 26.3 ms f xx : internal system clock f x : external oscillation frequency 211 user?s manual u14492ej4v1ud chapter 9 timer/counter function (real-time pulse unit) 9.1 timer 0 9.1.1 features (timer 0) timers 00, 01 (tm00, tm01) are 16-bit timer/counters that are ideal for cont rolling high-speed inverters such as motors. ? 3-phase pwm output function pwm mode 0 (symmetric triangular wave) pwm mode 1 (asymmetric triangular wave) pwm mode 2 (sawtooth wave) ? interrupt culling function culling ratios (1/1, 1/2, 1/4, 1/8, 1/16) ? forcible 3-phase pwm output stop function 3-phase pwm output can be forcibly stopped by inputting a signal from external signal input pin eson during anomalies. this function can also be used when the clock is stopped. ? real-time output function 3-phase pwm output or rectangular wave out put can be selected at the desired timing. ? output of positive phase and neg ative phase or positive phase and in-phase of 3-phase pwm output chapter 9 timer/counter function (real-time pulse unit) 212 user?s manual u14492ej4v1ud 9.1.2 function overview (timer 0) ? 16-bit timer (tm0n) for 3-phase pwm inverter control: 2 channels ? compare registers: 4 registers 2 channels ? 12-bit dead-time timers (dtmn0 to dtmn2): 3 timers 2 channels ? count clock division selectable by prescaler (set the frequency of the count clock to 40 mhz or less) ? base clock (f clk ): 2 types (set f clk to 40 mhz or less) f xx and f xx /2 can be selected ? prescaler division ratio the following division ratios can be selected according to the base clock (f clk ). base clock (f clk ) division ratio f xx selected f xx /2 selected 1/1 f xx f xx /2 1/2 f xx /2 f xx /4 1/4 f xx /4 f xx /8 1/8 f xx /8 f xx /16 1/16 f xx /16 f xx /32 1/32 f xx /32 f xx /64 ? interrupt request sources ? compare-match interrupt request: 2 types intcm0n3 generated by cm0n3 match signal ? underflow interrupt request: 2 types inttm0n generated by underflow ? external pulse output (to0n0 to to0n5): 6 2 channels remark f xx : internal system clock n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 213 user?s manual u14492ej4v1ud 9.1.3 basic configuration the basic configuration is shown below. figure 9-1. block diagram of ti mer 0 (mode 0: symmetric triangular wave, mode 1: asymmetric triangular wave) f xx /2 bfcmn3 cm0n3 bfcmn0 cm0n0 bfcmn1 cm0n1 bfcmn2 cm0n2 tm0n s/r 1/1 1/2 1/4 1/8 1/16 1/32 16 16 12 f clk intcm0n3 inttm0n r s r s r s dtmn2 dtmn1 dtmn0 dtrrn 6 to0n0 (u phase) to0n1 (u phase) to0n2 (v phase) to0n3 (v phase) to0n4 (w phase) to0n5 (w phase) selector output control by external input (eson), tm0n timer operation underflow underflow underflow alvub alvvb alvwb r s r s r s r s r s r s alvto f xx remarks 1. tm0n: timer register cm0n0 to cm0n3: compare registers bfcmn0 to bfcmn3: buffer registers dtrrn: dead-time timer reload register dtmn0 to dtmn2: dead-time timers alvto: bit 7 of tomrn register alvub: bit 6 of tomrn register alvvb: bit 5 of tomrn register alvwb: bit 4 of tomrn register s/r: set/reset 2. n = 0, 1 3. f xx : internal system clock 4. f clk : base clock (40 mhz (max.)) chapter 9 timer/counter function (real-time pulse unit) 214 user?s manual u14492ej4v1ud figure 9-2. block diagram of ti mer 0 (mode 2: sawtooth wave) bfcmn3 cm0n3 bfcmn0 cm0n0 bfcmn1 cm0n1 bfcmn2 cm0n2 tm0n 1/1 1/2 1/4 1/8 1/16 1/32 16 16 12 intcm0n3 r s r s r s dtmn2 dtmn1 dtmn0 dtrrn to0n0 (u phase) to0n1 (u phase) to0n2 (v phase) to0n3 (v phase) to0n4 (w phase) to0n5 (w phase) underflow underflow underflow f xx /2 selector clear output control by external input (eson), tm0n timer operation f clk r s r s r s r s r s r s alvub alvvb alvwb alvto f xx remarks 1. tm0n: timer register cm0n0 to cm0n3: compare registers bfcmn0 to bfcmn3: buffer registers dtrrn: dead-time timer reload register dtmn0 to dtmn2: dead-time timers alvto: bit 7 of tomrn register alvub: bit 6 of tomrn register alvvb: bit 5 of tomrn register alvwb: bit 4 of tomrn register 2. n = 0, 1 3. f xx : internal system clock 4. f clk : base clock (40 mhz (max.)) chapter 9 timer/counter function (real-time pulse unit) 215 user?s manual u14492ej4v1ud (1) timers 00, 01 (tm00, tm01) tm0n operates as a 16-bit up/down ti mer or up timer. the cycle is c ontrolled by compare register 0n3 (cm0n3) (n = 0, 1). tm0n start/stop is controlled by the tm0cen bit of timer control register 0n (tmc0n). division by the prescaler can be selected for the count clock from among f clk , f clk /2, f clk /4, f clk /8, f clk /16, f clk /32 with the prm02 to prm00 bits of the tmc0n register (f clk : base clock, see 9.1.4 (1) timer 0 clock selection register (prm01) ). the conditions when tm0n becomes 0000h are as follows. ? reset input ? tm0cen bit = 0 ? tm0n register and compare register 0n3 (cm0n3) match (pwm mode 2 (sawtooth wave) only) ? immediately after overflow or underflow the tm0n timer has 3 operation modes, shown in tabl e 9-1. the operation mode is selected with timer control register 0n (tmc0n). table 9-1. timer 0 operation modes operation mode count operation timer clear source interrupt source bfcmn3 cm0n3 transfer timing bfcmn0 to bfcmn2 cm0n0 to cm0n2 transfer timing pwm mode 0 (symmetric triangular wave) up/down ? inttm0n intcm0n3 inttm0n inttm0n pwm mode 1 (asymmetric triangular wave) up/down ? inttm0n intcm0n3 inttm0n inttm0n intcm0n3 pwm mode 2 (sawtooth wave) up intcm0n3 intcm0n3 intcm0n3 intcm0n3 caution an interrupt does not occur and the operati on of timer 0 is not affected even if tm0icn, cm03icn, or the interrupt mask flag of the imr0 register (tm0mkn or cm03mkn) is set (interrupts disabled) as the interrupt source. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 216 user?s manual u14492ej4v1ud (2) dead-time timers 00 to 02, 10 to 12 (dtm00 to dtm02, dtm10 to dtm12) dtmn0 to dtmn2 are dedicated 12-bit down timers th at generate dead time suit able for inverter control application. dtmn0 to dtmn2 operate as one-shot timers. counting by a dead-time timer is enabled or disabled by the tm0cedn bit of timer control register 0n (tmc0n) and cannot be controlled by software. dead-time timer count start and stop is controlled by hardware. a dead-time timer starts counting down when the value of the dead-time timer reload register n (dtrrn) is transferred in synchronization with the com pare match timing of cm0n0 to cm0n2. when the value of a dead-time timer changes from 000h to fffh, the dead-time timer generates an underflow signal, and the time r stops at the value fffh. if the value of a dead-time timer matches the value of the corresponding compare register before underflow of the dead-time timer takes place, the value of dtrrn is transferred to the dead-time timer again, and the timer starts down counting. the count clock of the dead-time ti mer is fixed to the base clock (f clk ), and the dead-time width is (set value of dtrrn + 1)/base clock (f clk ). if tm0n operates in pwm mode 0, pwm mode 1 with the dead-time timer count operation disabled, an inverted signal without dead time is output to to0n0 and to0n1, to0n2 and to 0n3, and to0n4 and to0n5. (3) dead-time timer reload re gisters 0, 1 (dtrr0, dtrr1) dtrrn register is a 12-bit register used to set the values of the three dead-time timers (dtmn0 to dtmn2 registers) (n = 0, 1). however, a value is transferred from the dtrrn register to each dead-time register independently. dtrrn can be read/written in 16-bit units. all 0s are read for the higher 4 bits when 16-bit read access is performed to the dtrrn register. 14 0 13 0 12 0 2 3 4 5 6 7 8 9 10 11 15 0 10 dtrr0 address fffff570h initial value 0fffh 14 0 13 0 12 0 2 3 4 5 6 7 8 9 10 11 15 0 10 dtrr1 address fffff5b0h initial value 0fffh cautions 1. changing the value of the dtrrn regi ster during tm0n operation (tm0cen bit of tmc0n register = 1) is prohibited. 2. be sure to write 0 to the higher 4 bits. (4) compare registers 000 to 002, 010 to 012 (cm000 to cm002, cm010 to cm012) cm0n0 to cm0n2 are 16-bit registers that always compar e their own values with the value of tm0n. if the value of a compare register matches the value of tm0n, the compare register outputs a trigger signal, and changes the contents of the flip-flop (f/f) connected to the compar e register. each of cm0n0 to cm0n2 is provided with a buffer register (bfcmn0 to bfcmn2), so that the contents of the buffer are transferred to cm0n0 to cm0n2 at the next transfer timing. transfer is enabled or disabled by the bften bit of the tmc0n register. chapter 9 timer/counter function (real-time pulse unit) 217 user?s manual u14492ej4v1ud (5) compare registers 003, 013 (cm003, cm013) cm0n3 is a 16-bit register that always compare its valu e with the value of tm0n. if the values match, cm0n3 outputs an interrupt signal (intcm0n3). cm0n3 controls th e maximum count value of tm0n, and if the values match, it performs the following operati ons at the next timer count clock. ? in triangular wave setting mode (pwm modes 0, 1): switches tm0n operation from up count to down count ? sawtooth wave setting mode (pwm mode 2): clears the count value of tm0n cm0n3 also has a buffer register (bfcmn3) and transfers the buffer contents at the timing of the next transfer to cm0n3. transfer enable or disable is contro lled by the bfte3 bit of the tmc0n register. (6) buffer registers cm00 to cm02, cm10 to cm 12 (bfcm00 to bfcm02, bfcm10 to bfcm12) bfcmn0 to bfcmn2 are 16-bit regist ers that transfer data to the co mpare register (cm0n0 to cm0n2) corresponding to each buffer register when an inte rrupt signal (intcm0n3/inttm0n) is generated. bfcmn0 to bfcmn2 can be read/wri tten in 16-bit units. caution the set values of the bfcmn0 to bfcmn2 registers are transferred to the cm0n0 to cm0n2 registers in the following timing (n = 0, 1). ? when tm0cen bit of tmc0n register = 0: tran sfer at next operation timing after writing to bfcmn0 to bfcmn2 registers ? when tm0cen bit of tmc0n register = 1: value of bfcmn0 to bfcmn2 registers is transferred to cm0n0 to cm 0n2 registers upon occurrence of inttm0n or intcm0n3. at this time, transfer enable or disable is co ntrolled by the bften bit of the timer control register (tmc0n). 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm00 address fffff572h initial value ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm10 address fffff5b2h initial value ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm01 address fffff574h initial value ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm11 address fffff5b4h initial value ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm02 address fffff576h initial value ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm12 address fffff5b6h initial value ffffh chapter 9 timer/counter function (real-time pulse unit) 218 user?s manual u14492ej4v1ud (7) buffer registers cm03, cm13 (bfcm03, bfcm13) bfcmn3 is a 16-bit register that tr ansfers data to the compare register at any timing. transfer enable or disable is controlled by the bfte3 bit of the tmc0n register. bfcmn3 can be read/written in 16-bit units. cautions 1. the set value of the bfcmn3 register is transferred to the cm0n3 register in the following timing (n = 0, 1). ? when tm0cen bit of tmc0n register = 0: transfer at next ope ration timing after writing to bfcmn3 register ? when tm0cen bit of tmc0n register = 1: va lue of bfcmn3 register is transferred to cm0n3 register upon occurrence of inttm0n. at this time, transfer enable or disable is controlled by the bfte3 bit of th e timer control register (tmc0n). 2. setting the bfcmn3 regist er to 0000h is prohibited. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm03 address fffff578h initial value ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm13 address fffff5b8h initial value ffffh chapter 9 timer/counter function (real-time pulse unit) 219 user?s manual u14492ej4v1ud 9.1.4 control registers (1) timer 0 clock selection register (prm01) the prm01 register is used to select the base clock (f clk ) of timer 0 (tm0n). it can be read/written in 8-bit or 1-bit units. caution always set this register before using the timer. 7 0 prm01 6 0 5 0 4 0 3 0 2 0 1 0 0 prm1 address fffff5d0h initial value 00h bit position bit name function 0 prm1 specifies the base clock (f clk ) of timer 0 (tm0n) (see figure 9-3 ). 0: f xx /2 (when f xx > 40 mhz) 1: f xx (when f xx 40 mhz) remark f xx : internal system clock figure 9-3. timer 00 and timer 01 clock timer 00 timer 01 prm1 f clk f xx /2 select f xx remarks 1. f xx : internal system clock 2. f clk : base clock chapter 9 timer/counter function (real-time pulse unit) 220 user?s manual u14492ej4v1ud (2) timer control registers 00, 01 (tmc00, tmc01) tmc0n register is a 16-bit register that sets the operation of timer 0 (tm0n). the tmc0n register can be read/ written in 16-bit units. if the higher 8 bits of the tmc0n register are used as the tmc0nh register and the lower 8 bits as the tmc0nl register, the register can be read/ written in 8-bit or 1-bit units. caution to operate timer 0, first set tm 0cen = 0 and then set tm0cen = 1. (1/4) <14> stint0 13 cul02 12 cul01 2 mbfte 3 bften 4 bfte3 <5> tm0ced0 6 0 7 0 8 prm00 9 prm01 10 prm02 11 cul00 <15> tm0ce0 1 mod01 0 mod00 tmc00 address fffff57ah initial value 0508h <14> stint1 13 cul02 12 cul01 2 mbfte 3 bften 4 bfte3 <5> tm0ced1 6 0 7 0 8 prm00 9 prm01 10 prm02 11 cul00 <15> tm0ce1 1 mod01 0 mod00 tmc01 address fffff5bah initial value 0508h bit position bit name function 15 tm0cen specifies the operation of tm0n. 0: count disabled (stops afte r all count values are cleared) 1: count enabled caution when tm0cen = 0, to0n0 to to0n5 output becomes high impedance. 14 stintn specifies interrupt during tm0n timer start. 0: don?t generate interrupt at operation start 1: generate interrupt at operation start when stintn bit = 1, an interrupt is generated immediately after the rising edge of the tm0cen signal. when the mod01 bit = 0 (triangular wave mode), the inttm0n interrupt (see figure 9-4 ) is generated, and when the mod01 bit = 1 (sawtooth wave mode), the intcm0n3 interrupt is generated. caution changing the stintn bit during tm0n operation (tm0cen bit = 1) is prohibited. specifies the interrupt culling ratio. cul02 cul01 cul00 interrupt culling ratio 0 0 0 1/1 0 0 1 1/2 0 1 0 1/4 0 1 1 1/8 1 0 0 1/16 other than above culling is not performed 13 to 11 cul02 to cul00 remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 221 user?s manual u14492ej4v1ud (2/4) bit position bit name function 13 to 11 cul02 to cul00 cautions 1. inttm0n and intcm0n3 interrupts can be culled with the same culling ratio (1/1, 1/2, 1/4, 1/8, 1/16). 2. even when bfte3 bit = 1, bften bit = 1 (settings to transfer data from bfcmn0 to bfcmn3 registers to cm0n0 to cm0n3 registers), transfer is not performed with the generation timing of culled inttm0n and intcm0n3 interrupts if the mbfte bit = 0. 3. if the culling ratio is changed during count operation, the new culling ratio is applied after an interrupt has occurred with the culling ratio prior to the change (see figure 9-5) . specifies the count clock for tm0n. prm02 prm01 prm00 count clock 0 0 0 f clk 0 0 1 f clk /2 0 1 0 f clk /4 0 1 1 f clk /8 1 0 0 f clk /16 1 0 1 f clk /32 other than above setting prohibited 10 to 8 prm02 to prm00 caution the division ratio switch timing is from when the tm0n value has become 0000h and an inttm0n interrupt has occurred. therefore, in the timing that corresponds to interrupt culling, the division ratio is not switched. remark for the base clock (f clk ), see 9.1.4 (1) timer 0 clock selection register (prm01) . 5 tm0cedn specifies the operation of dtmn0 to dtmn2 timers. 0: dtmn0 to dtmn2 perform count operation 1: dtmn0 to dtmn2 stopped cautions 1. changing the tm0cedn bit during tm0n operation (tm0cen = 1) is prohibited. 2. if tm0n is operated when the tm0cedn bit = 1, a signal without dead time is output to the to0n0 to to0n5 pins. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 222 user?s manual u14492ej4v1ud (3/4) bit position bit name function specifies transfer of data from bfcmn3 register to cm0n3 register. 0: transfer disabled 1: transfer enabled the transfer timing from the bfcmn3 regist er to the cm0n3 register is as follows. bfte3 tm0n operation mode bfcmn3 cm0n3 transfer timing 0 all modes don?t transfer 1 pwm mode 0 (symmetric triangular wave) inttm0n 1 pwm mode 1 (asymmetric triangular wave) inttm0n 1 pwm mode 2 (sawtooth wave) intcm0n3 4 bfte3 when the bfte3 bit = 1, the value of the bfcmn3 register is transferred to the cm0n3 register upon occurrence of an inttm0n or intcm0n3 interrupt. specifies transfer of data from bfcmn0 to bfcmn2 registers to cm0n0 to cm0n2 registers. 0: transfer disabled 1: transfer enabled bften tm0n operation mode bfcmn0 to bfcmn2 cm0n0 to cm0n2 transfer timing 0 all modes don?t transfer 1 pwm mode 0 (symmetric triangular wave) inttm0n 1 pwm mode 1 (asymmetric triangular wave) inttm0n, intcm0n3 1 pwm mode 2 (sawtooth wave) intcm0n3 3 bften when the bften bit = 1, the values of the bfcmn0 to bfcmn2 registers are transferred to the cm0n0 to cm0n2 registers upon occurrence of an inttm0n or intcm0n3 interrupt. when culling of inttm0n and intcm0n3 interrupts is set with the cul02 to cul00 bits, specifies whether enable or dis able the bfte3 and bften bit settings upon occurrence of an interrupt for culling. 0: disable the set values of bfte3, bften bits upon occurrence of a culling interrupt 1: enable the set values of bfte3, bften bits upon occurrence of a culling interrupt the various combinations are as follows. operation upon occurrence of interrupt for culling mbfte 0 1 0 bfcmn0 to bfcmn2 cm0n0 to cm0n2 transfer disabled bfcmn0 to bfcmn2 cm0n0 to cm0n2 transfer disabled bften 1 bfcmn0 to bfcmn2 cm0n0 to cm0n2 transfer disabled bfcmn0 to bfcmn2 cm0n0 to cm0n2 transfer enabled 0 bfcmn3 cm0n3 transfer disabled bfcmn3 cm0n3 transfer disabled bfte3 1 bfcmn3 cm0n3 transfer disabled bfcmn3 cm0n3 transfer enabled 2 mbfte . remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 223 user?s manual u14492ej4v1ud (4/4) bit position bit name function specifies the operation mode of tm0n. mod 01 mod 00 operation mode tm0n operation timer clear source bfcmn3 cm0n3 timing bfcmn0 to bfcmn2 cm0n0 to cm0n2 timing 0 0 pwm mode 0 (symmetric triangular wave) up/down ? inttm0n inttm0n 0 1 pwm mode 1 (asymmetric triangular wave) up/down ? inttm0n inttm0n, intcm0n3 1 0 pwm mode 2 (sawtooth wave) up intcm0n3 intcm0n3 intcm0n3 1 1 setting prohibited 1, 0 mod01, mod00 caution changing the value of the mod01, mod00 bits during tm0n operation (tm0cen bit = 1) is prohibited. remark n = 0, 1 figure 9-4. specification of inttm 0n interrupt during pwm mode 0 (symmetric triangular wave), pwm mode 1 (asymmetric triangular wave) (mod 01, mod00 bits of tmc0n register = 0n) cm0n3 tm0n count value 0000h tm0cen specification from occurrence of inttm0n at first start after reset is possible with stintn bit inttm0n occurrence can be specified with stintn bit inttm0n occurrence inttm0n occurrence timer operation stopped remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 224 user?s manual u14492ej4v1ud figure 9-5. interrupt culling processing (a) pwm mode 0 (symmetric triangular wave) cm0n3 tm0n count value 0000h cul02 to cul00 inttm0n occurrence interrupt request interrupt culling 1/1 cycle interrupt culling 1/2 cycle inttm0n occurrence inttm0n occurrence inttm0n occurrence 000 001 remark n = 0, 1 (b) pwm mode 1 (asymmetric triangular wave) cm0n3 tm0n count value 0000h cul02 to cul00 inttm0n occurrence intcm0n3 occurrence interrupt request intcm0n3 occurrence intcm0n3 occurrence intcm0n3 occurrence inttm0n occurrence interrupt culling 1/1 cycle interrupt culling 1/2 cycle inttm0n occurrence inttm0n occurrence 000 001 remark n = 0, 1 (c) pwm mode 2 (sawtooth wave) cm0n3 tm0n count value 0000h cul02 to cul00 intcm0n3 occurrence interrupt request intcm0n3 occurrence interrupt culling 1/1 cycle interrupt culling 1/2 cycle intcm0n3 occurrence intcm0n3 occurrence 000 001 remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 225 user?s manual u14492ej4v1ud figure 9-6. interrupt culling ratio change timing (relationship between stintn bit se tting and cul bit change): pwm mode 1 (asymmetric triangular wave) inttm0n inttm0n inttm0n inttm0n inttm0n inttm0n inttm0n inttm0n intcm0n3 intcm0n3 intcm0n3 intcm0n3 intcm0n3 intcm0n3 intcm0n3 intcm0n3 000 001 010 interrupt culling 1/1 cycle interrupt culling 1/2 cycle interrupt culling 1/4 cycle tm0cen bit tm0n count value cul02 to cul00 bits stintn = 1 inttm0n inttm0n inttm0n inttm0n inttm0n intcm0n3 intcm0n3 intcm0n3 intcm0n3 inttm0n intcm0n3 inttm0n intcm0n3 intcm0n3 001 010 000 interrupt culling 1/2 cycle interrupt culling 1/4 cycle interrupt culling 1/1 cycle tm0cen bit tm0n count value cul02 to cul00 bits stintn = 1 inttm0n inttm0n inttm0n inttm0n intcm0n3 intcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n intcm0n3 inttm0n intcm0n3 intcm0n3 001 010 000 interrupt culling 1/2 cycle interrupt culling 1/4 cycle interrupt culling 1/1 cycle tm0cen bit tm0n count value cm0n3 0000h cm0n3 0000h cm0n3 0000h cul02 to cul00 bits stintn = 1 caution if, in tm0n, to realize the inttm0n and intc m0n3 culling function, the culling ratio is set to a value other than 1/1 with bits cul 02 to cul00 and counting is star ted, the subsequent interrupt output sequence will differ due to the set value of the stintn bit at count start. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 226 user?s manual u14492ej4v1ud (3) timer unit control regist ers 00, 01 (tuc00, tuc01) tuc0n register is an 8-bit register that controls to0n0 to to0n5 outputs. tuc0n can be read/written in 8-bit or 1-bit units. however, bit 0 is read-only. 7 0 tuc00 6 0 5 0 4 0 3 0 2 0 <1> tors0 <0> tosta0 address fffff57ch initial value 01h 7 0 tuc01 6 0 5 0 4 0 3 0 2 0 <1> tors1 <0> tosta1 address fffff5bch initial value 01h bit position bit name function 1 torsn flag that restarts to0n0 to to0n5 pin output that was forcibly stopped by eson pin input. causes output to resume by writing ?1? to torsn bit. cautions 1. if the level is set for the eson pin input level (tomr register toedg1 bit = 1, toedg0 bit = 0 or 1), the output disabled state is not released (tostan bit = 1) even if ?1? is written to the torsn bit while the output is disabled (tostan bit = 1). if the input level is inactive, the output disabled state is released (tostan bit = 0). the value of the torsn bit is held. 2. if the edge is set for the eson pin input (toedg1 bit = 0, toedg0 bit = 0 or 1), the output disabled state is released (tostan bit = 0) by writing ?1? to the torsn bit while the output is disabled (tostan bit = 1). 3. after reset, be sure to write ?1? to the torsn bit prior to starting output of to0n0 to to0n5. ?0? is read when the torsn bit is read. 0 tostan to0n0 to to0n5 pin output status flag through eson pin input 0: output enabled status 1: output disabled status remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 227 user?s manual u14492ej4v1ud (4) timer output mode registers 0, 1 (tomr0, tomr1) the tomrn register controls timer output from the to0n0 to to0n5 pins. to prevent abnormal output from pins to0n0 to to 0n5 due to illegal access, data write to the tomrn register consists of the following two sequences. (a) write access to the tomr write enable register (specn), followed by (b) write access to the tomrn register write is not enabled hardware-wise unless t he these two sequences are implemented. tomrn can be read/written in 8-bit units. caution when interrupt requests are generated dur ing write access to the tomrn register (after write access to the specn regist er and prior to write to the tomrn register), write processing to the tomrn register may not be performed normally if access to other addresses is performed using the internal bus during servicing of these interrupts. add one of the following processing items during th e tomrn register write routine. ? prior to write access to the tomrn register , disable acknowledge of all interrupts of cpu. ? following write access to the to mrn register, check that wr ite was performed normally. (1/2) 7 alvto tomr0 6 alvub 5 alvvb 4 alvwb 3 tosp 2 0 1 toedg1 0 toedg0 address fffff57dh initial value 00h 7 alvto tomr1 6 alvub 5 alvvb 4 alvwb 3 tosp 2 0 1 toedg1 0 toedg0 address fffff5bdh initial value 00h bit position bit name function 7 alvto specifies the active level of to0n0, to0n2, and to0n4 pins. 0: active level is low level 1: active level is high level caution changing the alvto bit during tm0n operation (tm0cen = 1) is prohibited. 6 alvub specifies the output level of the to0n1 pin. 0: inverted level of active level set by alvto bit 1: active level set by alvto bit when the alvub bit = 1, the output level of the to0n1 output is the same as to0n0. caution changing the alvub bit during tm0n operation (tm0cen = 1) is prohibited. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 228 user?s manual u14492ej4v1ud (2/2) bit position bit name function 5 alvvb specifies the output level of the to0n3 pin. 0: inverted level of active level set by alvto bit 1: active level set by alvto bit when the alvvb bit = 1, the output level of the to0n3 output is the same as to0n2. caution changing the alvvb bit during tm0n operation (tm0cen = 1) is prohibited. 4 alvwb specifies the output level of the to0n5 pin. 0: inverted level of active level set by alvto bit 1: active level set by alvto bit when the alvwb bit = 1, the output level of the to0n5 output is the same as to0n4. caution changing the alvwb bit during tm0n operation (tm0cen = 1) is prohibited. 3 tosp controls to0n0 to to0n5 pin output stop through eson pin input. 0: enables eson pin input 1: disables eson pin input cautions 1. the output stop status can be released by writing ?1? to the torsn bit of the tuc0n register. the operation continues even if output is prohibited for all timers and counters. 2. before changing the eson pin input status from disable to enable (changing tosp bit from 1 to 0), write ?1? to the torsn bit of the tuc0n register to reset the eson pin input status. these bits select the valid edge or level when setting forcible stop of to0n0 to to0n5 output through eson pin input with the tosp bit. toedg1 toedg0 operation 0 0 rising edge 0 1 falling edge 1 0 low level 1 1 high level 1, 0 toedg1, toedg0 cautions 1. changing the toedg1, toedg0 bits during tm0n operation (tm0cen = 1) is prohibited. 2. before changing the settings of bits toedg1 and toedg0, write ?1? to the torsn bit of the tuc0n register to reset the eson pin input status. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 229 user?s manual u14492ej4v1ud examples of the output waveforms of to000 and to00 1 when the higher 4 bits (alvto, alvub, alvvb, and alvwb) of the tomrn register are set in pwm mode 0 (symmetric triangular waves) are shown below. figure 9-7. output waveforms of to000 and to001 in pwm mode 0 (symmetric triangular waves) (without dead time (tm0ced0 bit = 1)) (a) tomr0 register value = 80h tm00 = cm000 to000 to001 tm00 = cm000 (b) tomr0 register value = 00h tm00 = cm000 to000 to001 tm00 = cm000 (c) tomr0 register value = c0h tm00 = cm000 to000 to001 tm00 = cm000 (d) tomr0 register value = 40h tm00 = cm000 to000 to001 tm00 = cm000 chapter 9 timer/counter function (real-time pulse unit) 230 user?s manual u14492ej4v1ud figure 9-8. output waveforms of to000 and to001 in pwm mode 0 (symmetric triangular waves) (with dead time (tm0ced0 bit = 0)) (a) tomr0 register value = 80h tm00 = cm000 to000 to001 tm00 = cm000 dead time period dead time period (b) tomr0 register value = 00h tm00 = cm000 to000 to001 tm00 = cm000 dead time period dead time period (c) tomr0 register value = c0h tm00 = cm000 to000 to001 tm00 = cm000 dead time period dead time period (d) tomr0 register value = 40h tm00 = cm000 to000 to001 tm00 = cm000 dead time period dead time period chapter 9 timer/counter function (real-time pulse unit) 231 user?s manual u14492ej4v1ud data setting to timer output mode registers 0, 1 (t omr0, tomr1) is done in the following sequence. <1> prepare the data to be set to timer output mode r egisters 0, 1 (tomr0, tomr1) in a general-purpose register. <2> write data to the tomr write ena ble registers 0, 1 (sepc0, spec1). <3> set timer output mode registers 0, 1 (tomr0, to mr1) (performed with the fo llowing instructions). ? store instruction (st/sst instructions) ? bit manipulation instruction (set1/clr1/not1 instructions) [description example] <1> mov 0x04, r10 <2> st.b r10, specn [r0] <3> st.b r10, tomrn [r0] remark n = 0, 1 to read the tomrn register, no s pecial sequence is required. cautions 1. disable interrupts be tween specn issue (<2>) and tomrn register write that immediately follows (<3>). 2. the data written to the specn register is dummy data; use the same register as the general- purpose register used to set the tomrn regi ster (<3> in the ab ove example) for specn register write (<2> in the above example). the same applies when using a general-purpose register for addressing. 3. do not write to the specn register or tomrn register via dma transfer. chapter 9 timer/counter function (real-time pulse unit) 232 user?s manual u14492ej4v1ud (5) pwm output enable regist ers 0, 1 (poer0, poer1) the poern register is used to make the external pulse output (to0n0 to to0n5) status inactive by software. poern can be read/written in 8-bit or 1-bit units. 7 0 poer0 6 0 <5> oe210 <4> oe200 <3> oe110 <2> oe100 <1> oe010 <0> oe000 address fffff57fh initial value 00h 7 0 poer1 6 0 <5> oe211 <4> oe201 <3> oe111 <2> oe101 <1> oe011 <0> oe001 address fffff5bfh initial value 00h bit position bit name function 5 oe21n specifies output status of to0n5 pin. 0: to0n5 output status is high impedance. 1: to0n5 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. 4 oe20n specifies output status of to0n4 pin. 0: to0n4 output status is high impedance. 1: to0n4 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. 3 oe11n specifies output status of to0n3 pin. 0: to0n3 output status is high impedance. 1: to0n3 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. 2 oe10n specifies output status of to0n2 pin. 0: to0n2 output status is high impedance. 1: to0n2 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. 1 oe01n specifies output status of to0n1 pin. 0: to0n1 output status is high impedance. 1: to0n1 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. 0 oe00n specifies output status of to0n0 pin. 0: to0n0 output status is high impedance. 1: to0n0 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 233 user?s manual u14492ej4v1ud (6) pwm software timing output regi sters 0, 1 (psto0, psto1) the pston register is used to perform settings to output the desired waveforms to the external pulse output pins (to0n0 to to0n5) by software. pston can be read/written in 8-bit or 1-bit units. cautions 1. when the value of the torton bit has been changed from 0 to 1 during timer output (setting changed to software output), the ti ming is delayed by the dead-time portion when the output level differ s from the timer output signa l during output due to the settings of the uportn, vportn, and wportn bits. when the output level is the same as th e timer output signal dur ing output due to the settings of the uportn, vportn, and wpor tn bits, output is pe rformed maintaining the same output level. 2. if software output is enabled (torton bit = 1), the inttm0n a nd intcm0n3 interrupts and to0n0 to to0n5 output statuses are as follows during tm0n operation (tm0cen bit = 1). inttm0n and intcm0n3 interrupts: cont inue occurring at each timing in accordance with timer and compare operations. to0n0 to to0n5 outputs: software output has priority. 3. if the torton bit is changed from 1 to 0 during tm0n operation (tm0cen bit = 1), the software output state is retained for the to0n0 to to0n5 outputs until one of the set/reset condition of the flip-flop for the to 0n0 to to0n5 outputs shown in (a) below is generated. (a) set/reset conditions of flip-flop for to0n0 to to0n5 outputs output status operation mode conditions triangular wave mode (pwm mode 0, 1) compare match while tm0n is counting up timer output sawtooth wave mode (pwm mode 2) match between tm0n and cm0n3 registers set software output ? set (to 1) uportn, vportn, and wportn bits triangular wave mode (pwm mode 0, 1) compare match while tm0n is counting down timer output sawtooth wave mode (pwm mode 2) compare match with tm0n reset software output ? clear (to 0) uportn, vportn, and wportn bits remark n = 0, 1 4. if the same value is written to the up ortn (vportn, wportn) bit when torton = 1, the to0n0 and to0n1 outputs (to0n2 and to 0n3, to0n4 and to0n5) are not changed. chapter 9 timer/counter function (real-time pulse unit) 234 user?s manual u14492ej4v1ud (1/2) <7> torto0 psto0 6 0 5 0 4 0 3 0 <2> uport0 <1> vport0 <0> wport0 address fffff57eh initial value 00h <7> torto1 psto1 6 0 5 0 4 0 3 0 <2> uport1 <1> vport1 <0> wport1 address fffff5beh initial value 00h bit position bit name function 7 torton specifies to0n0 to to0n5 output control. 0: timer output 1: software output the change of the to0n0 to to0n5 signals during software output occurs when the torton bit is set (to 1) and a value is written to the uportn, vportn, and wportn bits. a dead-time timer can also be used. 2 uportn specifies the to0n0 (u phase)/to0n1 (u phase) pin output value. caution if the uportn bit setting value is changed when torton = 1, the dead-time setting becomes valid for the to0n0/to0n1 output signal in the same way as during normal timer operation. 1 vportn specifies the to0n2 (v phase)/to0n3 (v phase) pin output value. caution if the vportn bit setting value is changed when torton = 1, the dead-time setting becomes valid for the to0n2/to0n3 output signal in the same way as during normal timer operation. remark n = 0, 1 alvto bit: bit 7 of the tomrn register alvub bit: bit 6 of the tomrn register alvvb bit: bit 5 of the tomrn register uportn operation to0n0 inverted level of alvto bit setting when alvub = 0 level of alvto bit setting 0 to0n1 when alvub = 1 inverted level of alvto bit setting to0n0 level of alvto bit setting when alvub = 0 inverted level of alvto bit setting 1 to0n1 when alvub = 1 level of alvto bit setting vportn operation to0n2 inverted level of alvto bit setting when alvvb = 0 level of alvto bit setting 0 to0n3 when alvvb = 1 inverted level of alvto bit setting to0n2 level of alvto bit setting when alvvb = 0 inverted level of alvto bit setting 1 to0n3 when alvvb = 1 level of alvto bit setting chapter 9 timer/counter function (real-time pulse unit) 235 user?s manual u14492ej4v1ud (2/2) bit position bit name function 0 wportn specifies the to0n4 (w phase )/to0n5 (w phase) pin output value. caution if the wportn bit setting value is changed when torton = 1, the dead-time setting becomes valid for the to0n4/to0n5 output signal in the same way as during normal timer operation. remark n = 0, 1 alvto bit: bit 7 of the tomrn register alvwb bit: bit 4 of the tomrn register the to0n0 to to0n5 pins can be set to timer output by a match between tm0n and the compare register or to software output using the pston register (torton bit = 1). software output has the priority over timer output. consequently, when the setting changes from tm0cen = 1 (timer operation enabled), torton = 1 (software output enabled) to tm0cen = 1 (timer operation enabled), torton = 0 (software output disabled), the to0n0 to to0n5 pins continue to perform software output until the occurrence of the firs t f/f set/reset due to a match between tm0n and the compare register after the torton bit setting changes. the relationship between th e settings of the torton and tm0cen bits when alvto = 1 and the output of to0n0 (positive phase side) is shown on the following pages (the negative phase side (to 0n1, to0n3, and to0n5) is dependent on the alvub, alvvb, and alvwb bits, so refe r to the explanations of each of these bits). wportn operation to0n4 inverted level of alvto bit setting when alvwb = 0 level of alvto bit setting 0 to0n5 when alvwb = 1 inverted level of alvto bit setting to0n4 level of alvto bit setting when alvwb = 0 inverted level of alvto bit setting 1 to0n5 when alvwb = 1 level of alvto bit setting chapter 9 timer/counter function (real-time pulse unit) 236 user?s manual u14492ej4v1ud figure 9-9. when uportn = 1 is set immediately before torton = 0 (switched by active value) cm0n3 0000h tm0n count value f/f intcm0n3 inttm0n to0n0 tm0cen torton uportn timer output note 1 note 2 note 3 software output timer output p1 t1 cm0n3 cm0n3 cm0n3 note 2 note 2 note 1 note 4 notes 1. f/f set by compare match during up count 2. f/f reset by compare match during down count 3. f/f set by writing uportn bit 4. f/f reset by writing uportn bit remark n = 0, 1 if the setting of the torton bit changes from 1 to 0 while the uportn bit is set to 1 in the p1 period in figure 9-9 above, the f/f continues to hold the tort on bit setting of ?1? until the t1 timing. however, because the f/f is reset at the t1 timing (by a compare match of tm0n during down counting), the to0n0 output changes from 1 to 0. chapter 9 timer/counter function (real-time pulse unit) 237 user?s manual u14492ej4v1ud figure 9-10. when uportn = 0 is set immediately before torton = 0 (switched by inactive value) cm0n3 0000h tm0n count value f/f intcm0n3 inttm0n to0n0 tm0cen torton uportn timer output note 1 note 3 software output timer output p1 t2 cm0n3 cm0n3 cm0n3 note 2 note 1 note 2 note 4 notes 1. f/f set by compare match during up count 2. f/f reset by compare match during down count 3. f/f set by writing uportn bit 4. f/f reset by writing uportn bit remark n = 0, 1 if the setting of the torton bit changes from 1 to 0 while the uportn bit is set to 0 in the p1 period in figure 9- 10 above, the f/f continues to hold the torton bit setting of ?0? until the t2 timing. however, because the f/f is set at the t2 timing (by a compare match of tm0n during up counting), the to0n0 output changes from 1 to 0. note that to0n0 to to0n5 output will st op if the torton bit setting is changed from 1 to 0 while the tm0cen bit is 0. chapter 9 timer/counter function (real-time pulse unit) 238 user?s manual u14492ej4v1ud figure 9-11. when uportn = 0 is se t immediately before torton = 1 cm0n3 0000h tm0n count value f/f intcm0n3 inttm0n to0n0 tm0cen torton uportn timer output software output timer output t3 cm0n3 cm0n3 cm0n3 note 2 note 1 note 1 note 2 note 1 note 4 note 3 notes 1. f/f set by compare match during up count 2. f/f reset by compare match during down count 3. f/f set by writing uportn bit 4. f/f reset by writing uportn bit remark n = 0, 1 if the setting of the torton bit changes from 0 to 1 while the uportn bit is set to 0 during tm0n operation (tm0cen = 1), the to0n0 output changes from 1 to 0 because the f/f is reset at the t3 timing. examples of the software output waveforms of to 000 and to001 based on the settings of the torton, uportn, vportn, and wportn bits are shown on the following pages. chapter 9 timer/counter function (real-time pulse unit) 239 user?s manual u14492ej4v1ud figure 9-12. software output w aveforms of to000 and to001 (without dead time (tm0ced0 = 1)) (a) tomr0 register value = 80h uport0 1 to000 to001 uport0 0 (b) tomr0 register value = 00h uport0 1 to000 to001 uport0 0 (c) tomr0 register value = c0h uport0 1 to000 to001 uport0 0 (d) tomr0 register value = 40h uport0 1 to000 to001 uport0 0 chapter 9 timer/counter function (real-time pulse unit) 240 user?s manual u14492ej4v1ud figure 9-13. software output waveforms of to 000 and to001 (with dead time (tm0ced0 = 0)) (a) tomr0 register value = 80h uport0 1 to000 to001 uport0 0 dead-time period dead-time period (b) tomr0 register value = 00h uport0 1 to000 to001 uport0 0 dead-time period dead-time period (c) tomr0 register value = c0h uport0 1 to000 to001 uport0 0 dead-time period dead-time period (d) tomr0 register value = 40h uport0 1 to000 to001 uport0 0 dead-time period dead-time period chapter 9 timer/counter function (real-time pulse unit) 241 user?s manual u14492ej4v1ud figure 9-14. software output wavef orms of to000 and to001 when ?1? is written to uport0 bit while torto0 = 1 (when tomr0 register value = 80h) (a) without dead ti me (tm0ced0 = 1) uport0 1 uport0 0 uport0 1 to000 to001 (b) with dead time (tm0ced0 = 0) uport0 1 uport0 0 uport0 1 to000 to001 dead-time period dead-time period the following table shows the output status of external pulse out put (in the case of to0n0). table 9-2. output status of extern al pulse output (in case of to0n0) oe00n bit torton, uportn bits tm0cen bit to0n0 0 0/1 0/1 high impedance 0 high impedance 0 1 timer output 1 1 0/1 output by uportn bit remarks 1. oe00n bit: bit 0 of poern register torton bit: bit 7 of pston register uportn bit: bit 2 of pston register tm0cen bit: bit 15 of tmc0n register 2. n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 242 user?s manual u14492ej4v1ud (7) tomr write enable registers 0, 1 (spec0, spec1) the specn register enables write to the tomrn register. unless write to the tomrn register is performed following immediately after write to the specn register (any data can be written), write processing to the tomrn register is not performed normally. normally, 0000h is read. the specn register can be read/ written in 16-bit units. remark n = 0, 1 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1 0 0 0 spec0 address fffff580h initial value 0000h 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1 0 0 0 spec1 address fffff5c0h initial value 0000h chapter 9 timer/counter function (real-time pulse unit) 243 user?s manual u14492ej4v1ud 9.1.5 operation remarks 1. in the description of the operation in 9.1.5, it is assumed that eac h bit that affects the output of to0n0 to to0n5 is set as follows. alvto = 1, alvub = 0, alvvb = 0, alvwb = 0, torton = 0 2. f/f mentioned in 9.1.5 is a flip-flop that controls outpu t of the to0n0 to to0n5 pins. (1) basic operation timer 0 (tm0n) is a 16-bit interval timer that operates as an up/down timer or as an up timer. the cycle is controlled by compare register 0n3 (cm0n3) (n = 0, 1). all tm0n bits are cleared (0) by reset input and count operation is stopped. count operation enable/disable is controlled by the tm0cen bit of timer control register 0n (tmc0n). the count operation is started by setting the tm0cen bit to 1 by software. resetting the tm0cen bit to 0 clears tm0n and stops the count operation. when the value of compare register 0n3 (cm0n3) set beforehand and the value of the tm0n counter match, a match interrupt (intcm0n3) is generated. the count clock to tm0n can be sele cted from among 6 internal clocks with the tmc0n register. if the tm0n has been set as an up/down timer, an underflow interrupt (inttm0n) is generated when tm0n becomes 0000h during down counting. the tm0n has the following three operation modes, wh ich are selected with timer control register 0n (tmc0n). ? pwm mode 0: triangular wave modulation (right-left symmetric waveform control) ? pwm mode 1: triangular wave modulation (right-left asymmetric waveform control) ? pwm mode 2: sawtooth wave modulation control table 9-3. timer 0 (tm0n) operation modes tmc0n register mod01 mod00 operation mode tm0n operation timer clear source interrupt source bfcmn3 cm0n3 timing bfcmn0 to bfcmn2 cm0n0 to cm0n2 timing 0 0 pwm mode 0 (symmetric triangular wave) up/down ? inttm0n intcm0n3 inttm0n inttm0n 0 1 pwm mode 1 (asymmetric triangular wave) up/down ? inttm0n intcm0n3 inttm0n inttm0n intcm0n3 1 0 pwm mode 2 (sawtooth wave) up intcm0n3 intcm0n3 intcm0n3 intcm0n3 1 1 setting prohibited caution changing bits mod01, mod00 during tm 0n operation (tm0cen = 1) is prohibited. remark n = 0, 1 the various operation modes are described below. chapter 9 timer/counter function (real-time pulse unit) 244 user?s manual u14492ej4v1ud (2) pwm mode 0: triangular wave modulation (right-left sy mmetric waveform control) [setting procedure] (a) set pwm mode 0 (symmetric triangular wave) with bits mod01 and mod00 of the tmc0n register. also set the active level of pins to0n0 to to0n5 with the alvto bit of the tomrn register (n = 0, 1). (b) set the count clock of tm0n with bits prm02 to prm00 of the tmc0n regist er. the transfer operation from bfcmn3 to cm0n3 is set with bit bfte3, and t he transfer operation from bfcmn0 to bfcmn2 to cm0n0 to cm0n2 is set with bit bften. (c) set the initial values. (i) specify the interrupt culling ratio with bits cul02 to cul00 of the tmc0n register. (ii) set the half-cycle width of the pwm cycle in bfcmn3. ? pwm cycle = bfcmn3 value 2 tm0n count clock (the tm0n count clock is set with the tmc0n register.) (iii) set the dead-time width in dtrrn. ? dead-time width = (dtrrn + 1)/f clk f clk : base clock (iv) set the set/reset timing of the f/f us ed in the pwm cycle in bfcmn0 to bfcmn2. (d) clear (0) the tm0cedn bit of the tmc0n register to enable dead-time timer operation. set tm0cedn = 1 when not using dead time. (e) setting (1) the tm0cen bit of the tmc0n register starts tm0n counting, and a 6-channel pwm signal is output from pins to0n0 to to0n5. cautions 1. setting cm0n3 to 0000h is prohibited. 2. setting bfcmnx > bfcmn3 is prohibited when the tm0cen bit of the tmc0n register = 0 because output of the to0n0 to to0n5 pins is inverted from the setting (x = 0 to 2). in addition, setting bfcmnx > bfcmn3 is also prohibited when the tm0cen bit of the tmc0n register = 1 and the cm0nx register = 0. remark the tm0cen bit of the tmc0n register indicate s transfer operation under the following conditions. ? when tm0cen bit of tmc0n register is 0 transfer to the cm0n0 to cm0n2 registers is performed at the next base clock (f clk ) after writing to registers bfcmn0 to bfcmn2. ? when tm0cen bit of tmc0n register is 1 the value of the bfcmn0 to bfcmn2 registers is transferred to the cm0n0 to cm0n2 registers upon occurrence of the inttm0n interrupt. transfer enable/disable at this time is controlled by bit bften of the tmc0n register. chapter 9 timer/counter function (real-time pulse unit) 245 user?s manual u14492ej4v1ud [operation] in pwm mode 0, tm0n performs up/down count operat ion. when tm0n = 0000h during down counting, an underflow interrupt (inttm0n) is generated, and when tm0n = cm0n3 during up counting, a match interrupt (intcm0n3) is generated (n = 0, 1). switching from up counting to down counting is pe rformed when tm0n and cm0n3 match (intcm0n3), and switching from down counting to up counting is performed when tm0n underflow occurs after tm0n becomes 0000h. the pwm cycle in this mo de is (bfcmn3 value 2 tm0n count clock). concerning setting of data to bfcmn3, the next pwm cycle width is set to bfcmn3. the data of bfcmn3 is autom atically transferred by hardware to cm0n3 upon generation of the inttm0n interrupt. furthermore, calculation is performed by so ftware processing started by inttm0n, and the data for the next cycle is set to bfcmn3. data setting to cm0n0 to cm0n2, which control the pwm duty, is explained next. setting of data to cm0n0 to cm0n2 consists in se tting the duty output from bfcmn0 to bfcmn2. the values of bfcmn0 to bfcmn2 are automatically transferred by hardware to cm0n0 to cm0n2 upon generation of the inttm0n interrupt. furthermore, software processing is started up and calculation performed, and set/reset timing of the f/f for the next cycle is set to bfcmn0 to bfcmn2. the pwm cycle and the pwm duty are se t in the above procedure. the f/f set/reset conditions upon match of cm0n0 to cm0n2 are as follows. ? set: cm0n0 to cm0n2 match detection during tm0n up-count operation ? reset: cm0n0 to cm0n2 match detection during tm0n down-count operation in this mode, the f/f set/reset timi ng is performed in the same timing (right-left symmetric control). the values of dtrrn are transferred to the corresponding dead-time timers (dtmn0 to dtmn2) in synchronization with the set/reset timing of the f/f, and down counting is start ed. dtmn0 to dtmn2 count down to 000h, and stop when they count down further to fffh. dtmn0 to dtmn2 can automatically ge nerate a width (dead time) at which th e active levels of the positive phase (to0n0, to0n2, to0n4) and negative phase (to0n1, to0n3, to0n5) do not overlap. in this way, software processing is started by an in terrupt (inttm0n) that occurs once during every pwm cycle after initial setting has been performed, and by se tting the pwm cycle and pwm duty to be used in the next cycle, it is possible to autom atically output a pwm waveform to to0n0 to to0n5 pins taking into consideration the dead-time width (in case of interrupt culling ratio of 1/1). chapter 9 timer/counter function (real-time pulse unit) 246 user?s manual u14492ej4v1ud [output waveform width in respect to set value] ? pwm cycle = bfcmn3 2 t tm0n ? dead-time width t dnm = (dtrrn + 1)/f clk ? active width of positive phas e (to0n0, to0n2, to0n4 pins) = { (cm0n3 ? cm0nx up ) + (cm0n3 ? cm0nx down ) } t tm0n ? t dnm ? active width of negative ph ase (to0n1, to0n3, to0n5 pins) = (cm0nx down + cm0nx up ) t tm0n ? t dnm ? in this mode, cm0nx up = cm0nx down (however, within the same pwm cycle). since cm0nx up and cm0nx down in the negative phase formula are prepared in a separate pwm cycle, cm0nx up cm0nx down . f clk : base clock t tm0n : tm0n count clock cm0nx up : set value of cm0n0 to cm0n2 while tm0n is counting up cm0nx down : set value of cm0n0 to cm0n2 while tm0n is counting down the pin level when the to0n0 to to0n5 pins are reset is the high impedance state. when the control mode is selected thereafter, the fo llowing levels are output unt il the tm0n is started. ? to0n0, to0n2, to0n4? when low active high level when high active low level ? to0n1, to0n3, to0n5? when low active low level when high active high level the active level is set with the alvto bit of t he tomrn register. the default is low active. caution if a value such that the positive phase or negative phase active width is ?0? or a negative value in the above formula, the to0n0 to to0n5 pins out put a waveform fixed to the inactive level waveform wit h active width ?0?. remark m = 0 to 2 n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 247 user?s manual u14492ej4v1ud figure 9-15. operation timing in pwm mode 0 (symmetric triangular wave) t t t t cm0n3 (d) cm0n3 (e) aa bb cm0nx match cm0nx match cm0nx match cm0nx match bc e a df b a ef d intcm0n3 inttm0n intcm0n3 inttm0n c tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx bfcmn3 cm0n3 dtmnx f/f cm0nx interrupt request 0000h remarks 1. the above figure shows the timing chart when bfte3 and bften of the tmc0n register are 1, and transfer from bfcmn3 to cm0n3, or from bfcmnx to cm0nx is enabled. transfer is not performed when bfte3 = 0 or bften = 0. 2. n = 0, 1 3. x = 0 to 2 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. to not use dead time, set the tm0cedn bit of the tmc0n register to 1. 6. the above figure shows an active high case. figure 9-16 shows the overall operation image. chapter 9 timer/counter function (real-time pulse unit) 248 user?s manual u14492ej4v1ud figure 9-16. overall operation image of pwm mode 0 (symmetric triangular wave) cm0n3 tm0n count value to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output 0000h cm0n2 cm0n2 cm0n1 cm0n1 cm0n0 cm0n0 cm0n3 cm0n2 cm0n2 cm0n1 cm0n1 cm0n0 cm0n0 without dead time with dead time remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 249 user?s manual u14492ej4v1ud next, an example of the operation timing, which depends on the values set to cm0n0 to cm0n2 (bfcmn0 to bfcmn2) is shown. (a) when cm0nx (bfcmnx) cm0n3 is set figure 9-17. operation timing in pwm mode 0 (symmetric triangular wave, bfcmnx cm0n3) t t cm0n3 cm0n3 aa cm0nx match cm0nx match bfcmnx cm0n3 bfcmnx cm0n3 a bfcmnx cm0n3 a inttm0n intcm0n3 intcm0n3 inttm0n tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active high case. when a value greater than cm0n3 is set to bfcm nx, the positive phase si de (to0n0, to0n2, to0n4 pins) outputs a low level, and t he negative phase side (to0n1, to0n3, to0n5 pins) continues to output a high level. this feature is effective for outputti ng a low-level or high-level width exceeding the pwm cycle in an application such as inve rter control. furthermore, if cm0nx = cm0n3 is set, matching of tm0n and cm0nx is detected during down coun ting by tm0n, so that the f/f remains reset as is, and does not get set. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. chapter 9 timer/counter function (real-time pulse unit) 250 user?s manual u14492ej4v1ud (b) when cm0nx (bfcmnx) = 0000h is set figure 9-18. operation timing in pwm mode 0 (symmetric triangular wave, bfcmnx = 0000h) t t t cm0n3 cm0n3 aa cm0nx match cm0nx match cm0nx match 0000h 0000h a 0000h a inttm0n intcm0n3 intcm0n3 inttm0n tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active high case. since tm0n = cm0nx = 0000h match is detected during up counting by tm0n, the f/f is just set and does not get reset. even when the setting value is 0000h, f/f is changed in the cycle during which transfer is performed from bfcmnx to cm0nx similarl y to when the setting value is other than 0000h. figure 9-19 shows the change timing from the 100% duty state. chapter 9 timer/counter function (real-time pulse unit) 251 user?s manual u14492ej4v1ud figure 9-19. change timing from 100% duty state (pwm mode 0) cm0n3 tm0n count value bfcm0nx cm0nx dtmnx f/f interrupt request positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) 0000h 0000h b c a 0000h 0000h note b cm0n3 cm0n3 aa cm0nx match cm0nx match cm0nx match cm0n3 bb t t t t t t inttm0n inttm0n inttm0n inttm0n cm0nx match cm0nx match cm0nx match a intcm0n3 intcm0n3 intcm0n3 intcm0n3 note f/f is reset upon inttm0n occurrence. remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active high case. chapter 9 timer/counter function (real-time pulse unit) 252 user?s manual u14492ej4v1ud (3) pwm mode 1: triangular wave modulation (right-left asy mmetric waveform control) [setting procedure] (a) set pwm mode 1 (asymmetric triangular wave) wit h bits mod01 and mod00 of the tmc0n register. also set the active level of pins to0n0 to to0n5 with the alvto bit of the tomrn register (n = 0, 1). (b) set the count clock of tm0n with bits prm02 to prm00 of the tmc0n regist er. the transfer operation from bfcmn3 to cm0n3 is set with bit bfte3, and t he transfer operation from bfcmn0 to bfcmn2 to cm0n0 to cm0n2 is set with bit bften. (c) set the initial values. (i) specify the interrupt culling ratio with bi ts cul02 to cul00 of the tmc0n register. (ii) set the half-cycle width of the pwm cycle in bfcmn3. ? pwm cycle = bfcmn3 value 2 tm0n count clock (the tm0n count clock is set with the tmc0n register.) (iii) set the dead-time width in dtrrn. ? dead-time width = (dtrrn + 1)/f clk f clk : base clock (iv) set the set timing of the f/f used in the pwm cycle in bfcmn0 to bfcmn2. (d) clear (0) the tm0cedn bit of the tmc0n register to enable dead-time timer operation. set tm0cedn = 1 when not using dead time. (e) setting (1) the tm0cen bit of the tmc0n register starts tm0n counting, and a 6-channel pwm signal is output from pins to0n0 to to0n5. caution setting cm0n3 to 0000h is prohibited. remark the tm0cen bit of the tmc0n register indicate s transfer operation under the following conditions. ? when tm0cen bit of tmc0n register is 0 transfer to the cm0n0 to cm0n2 registers is performed at the next base clock (f clk ) after writing to registers bfcmn0 to bfcmn2. ? when tm0cen bit of tmc0n register is 1 the value of the bfcmn0 to bfcmn2 registers is transferred to the cm0n0 to cm0n2 registers upon occurrence of the inttm0n or intcm0n3 interrupt. transfer enable/disable at this time is controlled by bit bften of the tmc0n register. chapter 9 timer/counter function (real-time pulse unit) 253 user?s manual u14492ej4v1ud [operation] in pwm mode 1, tm0n performs up/down count operat ion. when tm0n = 0000h during down counting, an underflow interrupt (inttm0n) is generated, and when tm0n = cm0n3 during up counting, a match interrupt (intcm0n3) is generated (n = 0, 1). switching from up counting to down counting is pe rformed when tm0n and cm0n3 match (intcm0n3), and switching from down counting to up counting is performed by inttm0n. the pwm cycle in this mo de is (bfcmn3 value 2 tm0n count clock). concerning setting of data to bfcmn3, the next pwm cycle width is set to bfcmn3. the data of bfcmn3 is autom atically transferred by hardware to cm0n3 upon generation of the inttm0n interrupt. furthermore, calculation is performed by so ftware processing started by inttm0n, and the data for the next cycle is set to bfcmn3. data setting to cm0n0 to cm0n2, which control the pwm duty, is explained next. setting of data to cm0n0 to cm0n2 consists in se tting the duty output from bfcmn0 to bfcmn2. the values of bfcmn0 to bfcmn2 are automatically transferred by hardware to cm0n0 to cm0n2 upon generation of the inttm0n and intcm0n3 (tm0n and cm0n3 match interrupts). furthermore, software processing is started up and calculation performed, and the set/reset timing of t he f/f after a half cycle is set in bfcmn0 to bfcmn2. the pwm cycle and the pwm duty are se t in the above procedure. the f/f set/reset conditions upon match of cm0n0 to cm0n2 are as follows. ? set: cm0n0 to cm0n2 match detection during tm0n up-count operation ? reset: cm0n0 to cm0n2 match detection during tm0n down-count operation the values of dtrrn are transferred to the corres ponding dead-time timers (dtmn0 to dtmn2) in synchronization with the set/reset timing of the f/f, and down counting is start ed. dtmn0 to dtmn2 count down to 000h, and stop when they count down further to fffh. dtmn0 to dtmn2 can automatically ge nerate a width (dead time) at which th e active levels of the positive phase (to0n0, to0n2, to0n4) and negative phase (to0n1, to0n3, to0n5) do not overlap. in this way, software processing is started by tw o interrupts (inttm0n and intcm0n3) that occur during every pwm cycle after initial setting has been perform ed, and by setting the pwm cycle and pwm duty to be used after a half cycle, it is possible to automatically output a pwm waveform to to0n0 to to0n5 pins taking into consideration the dead-time width (in ca se of interrupt culling ratio of 1/1). the difference between right-left symmetric waveform contro l and control in this mode (right-left asymmetric waveform control) is that bfcmn0 to bfcmn2 are trans ferred to cm0n0 to cm0n2, and that the interrupt signals that start software processi ng consist just of inttm0n (generated once per pwm cycle) in the case of right-left symmetric waveform control, and inttm0n and intcm0n3 (generated twice per pwm cycle, or once per half cycle) in the case of ri ght-left asymmetric waveform control. chapter 9 timer/counter function (real-time pulse unit) 254 user?s manual u14492ej4v1ud [output waveform width in respect to set value] ? pwm cycle = bfcmn3 2 t tm0n ? dead-time width t dnm = (dtrrn + 1)/f clk ? active width of positive phas e (to0n0, to0n2, to0n4 pins) = { (cm0n3 ? cm0nx up ) + (cm0n3 ? cm0nx down ) } t tm0n ? t dnm ? active width of negative ph ase (to0n1, to0n3, to0n5 pins) = (cm0nx down + cm0nx up ) t tm0n ? t dnm f clk : base clock t tm0n : tm0n count clock cm0nx up : set value of cm0n0 to cm0n2 while tm0n is counting up cm0nx down : set value of cm0n0 to cm0n2 while tm0n is counting down the pin level when the to0n0 to to0n5 pins are reset is the high impedance state. when the control mode is selected thereafter, the fo llowing levels are output unt il the tm0n is started. ? to0n0, to0n2, to0n4? when low active high level when high active low level ? to0n1, to0n3, to0n5? when low active low level when high active high level the active level is set with the alvto bit of t he tomrn register. the default is low active. caution if a value such that the positive phase or negative phase active width is ?0? or a negative value in the above formula, the to0n0 to to0n5 pins out put a waveform fixed to the inactive level waveform wit h active width ?0?. remark m = 0 to 2 n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 255 user?s manual u14492ej4v1ud figure 9-20. operation timing in pwm mode 1 (asymmetric triangular wave) t t t t cm0n3 (f) cm0n3 (g) a b c d cm0nx match cm0nx match cm0nx match cm0nx match bcde g a fh b a gh f intcm0n3 inttm0n intcm0n3 inttm0n cde tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx bfcmn3 cm0n3 dtmnx f/f cm0nx 0000h remarks 1. the above figure shows the timing chart when b fte3 and bften of the tmc0n register are 1, and transfer from bfcmn3 to cm0n3, or from bfcmnx to cm0nx is enabled. transfer is not performed when bfte3 = 0 or bften = 0. 2. n = 0, 1 3. x = 0 to 2 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. to not use dead time, set the tm0cedn bit of the tmc0n register to 1. 6. the above figure shows an active high case. figure 9-21 shows the overall operation image. chapter 9 timer/counter function (real-time pulse unit) 256 user?s manual u14492ej4v1ud figure 9-21. overall operation image of pwm mode 1 (asymmetric triangular wave) cm0n3 tm0n count value to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output 0000h cm0n2 cm0n2 cm0n1 cm0n1 cm0n0 cm0n0 cm0n3 cm0n2 cm0n2 cm0n1 cm0n1 cm0n0 cm0n0 without dead time with dead time remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 257 user?s manual u14492ej4v1ud (a) when bfcmnx cm0n3 is set in software pr ocessing started by intcm0n3 figure 9-22. operation timing in pwm mode 1 (asymmetric triangular wave, bfcmnx cm0n3) t t cm0n3 cm0n3 a b cm0nx match cm0nx match inttm0n inttm0n tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h bccc a b accc intcm0n3 intcm0n3 remarks 1. n = 0, 1 2. x = 0 to 2 3. c cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active high case. when a value greater than cm0n3 is set to bfcm nx, the positive phase si de (to0n0, to0n2, to0n4 pins) outputs a low level, and t he negative phase side (to0n1, to0n3, to0n5 pins) continues to output a high level. this feature is effective for outputti ng a low-level or high-level width exceeding the pwm cycle in an application such as inve rter control. furthermore, if cm0nx = cm0n3 is set, matching of tm0n and cm0nx is detected during down coun ting by tm0n, so that the f/f remains reset as is, and does not get set. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. chapter 9 timer/counter function (real-time pulse unit) 258 user?s manual u14492ej4v1ud (b) when bfcmnx > cm0n3 is set in software processing started by inttm0n figure 9-23. operation timing in pwm mode 1 (a symmetric triangular wave, bfcmnx > cm0n3) t cm0n3 cm0n3 a cm0nx match inttm0n inttm0n tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h bbbb a b abbb intcm0n3 intcm0n3 remarks 1. n = 0, 1 2. x = 0 to 2 3. b > cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active high case. when a value greater than cm0n3 is set to bfcm nx, the positive phase si de (to0n0, to0n2, to0n4 pins) outputs a high level, and the negative phase side (to0n1, to0n3, to0n5 pins) continues to output a low level. this feature is effective for outputti ng a low-level or high-level width exceeding the pwm cycle in an application such as inverter control. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. figure 9-24 shows the change timing from the 100% duty state. chapter 9 timer/counter function (real-time pulse unit) 259 user?s manual u14492ej4v1ud figure 9-24. change timing from 100% duty state (pwm mode 1) cm0n3 tm0n count value bfcm0nx 0000h cm0nx dtmnx f/f interrupt request positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bbbbbcde note cm0n3 cm0n3 a cm0nx match cm0n3 c d cm0nx match cm0nx match abbbbbcde t t t t inttm0n intcm0n3 intcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n inttm0n note f/f is reset upon inttm0n occurrence. remarks 1. n = 0, 1 2. x = 0 to 2 3. b > cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active high case. chapter 9 timer/counter function (real-time pulse unit) 260 user?s manual u14492ej4v1ud (c) when bfcmnx = 0000h is set in softw are processing started by intcm0n3 figure 9-25. operation timing in pwm mode 1 (a symmetric triangular wave, bfcmnx = 0000h) (1) t t t cm0n3 cm0n3 a b cm0nx match cm0nx match inttm0n tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h b 0000h 0000h 0000h a b a 0000h 0000h 0000h intcm0n3 intcm0n3 inttm0n remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active high case. since tm0n = cm0nx = 0000h match is detected during up counting by tm0n, the f/f is just set and does not get reset. moreover, the f/f gets set upon match detection in the cycle when 0000h is transferred to cm0nx by inttm0n interrupt. figure 9-26 shows the change timing from the 100% duty state. chapter 9 timer/counter function (real-time pulse unit) 261 user?s manual u14492ej4v1ud figure 9-26. change timing from 100% duty state (1) (pwm mode 1) cm0n3 tm0n count value bfcm0nx 0000h cm0nx dtmnx f/f interrupt request positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bcde note cm0n3 cm0n3 a c cm0nx match cm0n3 d b cm0nx match cm0nx match 0000h 0000h 0000h 0000h d e t t t t t t inttm0n intcm0n3 intcm0n3 inttm0n inttm0n inttm0n cm0nx match cm0nx match 0000h 0000h 0000h 0000h bc a intcm0n3 intcm0n3 note f/f is reset upon inttm0n occurrence. remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active high case. chapter 9 timer/counter function (real-time pulse unit) 262 user?s manual u14492ej4v1ud (d) when bfcmnx = 0000h is set in so ftware processing started by inttm0n figure 9-27. operation timing in pwm mode 1 (a symmetric triangular wave, bfcmnx = 0000h) (2) t cm0n3 cm0n3 a cm0nx match inttm0n inttm0n tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h 0000h 0000h 0000h 0000h a 0000h a 0000h 0000h 0000h intcm0n3 intcm0n3 remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active high case. since tm0n = cm0nx = 0000h match is detected dur ing up counting by tm0n, the f/f is just set and does not get reset. therefore, the positive phase side (to 0n0, to0n2, to0n4 pins) outputs a high level, and the negative phase side (to0n1, to0n3, to0n5 pi ns) continues to output a low level. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. figure 9-28 shows the change timing from the 100% duty state. chapter 9 timer/counter function (real-time pulse unit) 263 user?s manual u14492ej4v1ud figure 9-28. change timing from 100% duty state (2) (pwm mode 1) cm0n3 tm0n count value bfcm0nx 0000h cm0nx dtmnx f/f interrupt request positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bcd note cm0n3 cm0n3 a cm0nx match cm0n3 b c cm0nx match cm0nx match a 0000h 0000h 0000h 0000h 0000h b d t t t t inttm0n intcm0n3 i ntcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n inttm0n 0000h 0000h 0000h 0000h 0000h c note f/f is reset upon inttm0n occurrence. remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active high case. chapter 9 timer/counter function (real-time pulse unit) 264 user?s manual u14492ej4v1ud (e) when bfcmnx = cm0n3 is set in software processing started by inttm0n figure 9-29. operation timing in pwm mode 1 (a symmetric triangular wave, bfcmnx = cm0n3) t t cm0n3 cm0n3 a cm0nx match cm0nx match inttm0n inttm0n tm0 count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h bbbb a b abbb intcm0n3 intcm0n3 remarks 1. n = 0, 1 2. x = 0 to 2 3. b = cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active high case. since tm0n and cm0nx match is detected during count down of tm0n when bfcmnx = cm0n3 has been set, the f/f remains reset as is and does not get set. therefore, the pos itive phase side (to0n0, to0n2, to0n4 pins) outputs a low level, and the negative phase side (to 0n1, to0n3, to0n5 pins) continues to output a high level. moreover, the timing of matching with tm0n with cm0nx = cm0n3 is the cycle when transfer is performed from bfcmnx to cm0nx by intcm0n3. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. chapter 9 timer/counter function (real-time pulse unit) 265 user?s manual u14492ej4v1ud (4) pwm mode 2: sawtooth wave modulation [setting procedure] (a) set pwm mode 2 (sawtooth wave) with bits mod 01 and mod00 of the tmc0n register. also set the active level of pins to0n0 to to0n5 with the alvto bit of the tomrn register. (b) set the count clock of tm0n with bits prm02 to prm00 of the tmc0n regist er. the transfer operation from bfcmn3 to cm0n3 is set with bit bfte3, and t he transfer operation from bfcmn0 to bfcmn2 to cm0n0 to cm0n2 is set with bit bften. (c) set the initial values. (i) specify the interrupt culling ratio with bi ts cul02 to cul00 of the tmc0n register. (ii) set the cycle width of the pwm cycle in bfcmn3. ? pwm cycle = (bfcmn3 value + 1) tm0n count clock (the tm0n count clock is set with the tmc0n register.) (iii) set the dead-time width in dtrrn. ? dead-time width = (dtrrn + 1)/f clk f clk : base clock (iv) set the set/reset timing of the f/f us ed in the pwm cycle in bfcm0n0 to bfcm0n2. (d) clear (0) the tm0cedn bit of the tmc0n register to enable dead-time timer operation. set tm0cedn = 1 when not using dead time. (e) setting (1) the tm0cen bit of the tmc0n register starts tm0n counting, and a 6-channel pwm signal is output from pins to0n0 to to0n5. caution setting cm0n3 to 0000h is prohibited. chapter 9 timer/counter function (real-time pulse unit) 266 user?s manual u14492ej4v1ud [operation] in pwm mode 2, tm0n performs up-count operation, and when it matches the value of cm0n3, match interrupt intcm0n3 is generated and tm0n is cleared (n = 0, 1). the pwm cycle in this mode is ((bfcmn3 value + 1) tm0n count clock). concerning setting of data to cm0n3, the next pwm cycle width is set to bfcmn3. the data of bfcmn3 is automatically transferred by hardware to cm0n3 upon generation of the intcm0n3 interrupt. furthermore, calculation is performed by so ftware processing started by intcm0n3, and the data for the next cycle is set to bfcmn3. data setting to cm0n0 to cm0n2, which control the pwm duty, is explained next. setting of data to cm0n0 to cm0n2 consists in se tting the duty output from bfcmn0 to bfcmn2. the values of bfcmn0 to bfcmn2 are automatically transferred by hardware to cm0n0 to cm0n2 upon generation of the intcm0n3 interrupt. furthermore, software processing is started up and calculation performed, and reset timing of the f/f for t he next cycle is set to bfcmn0 to bfcmn2. the pwm cycle and the pwm duty are se t in the above procedure. the f/f set/reset conditions upon match of cm0n0 to cm0n2 are as follows. ? set: tm0n and cm0n3 match detection and rising edge of tm0cen bit of tmc0n register ? reset: tm0n and cm0n0 to cm0n2 match detection the values of dtrrn are transferred to the corres ponding dead-time timers (dtmn0 to dtmn2) in synchronization with the set/reset timing of the f/f, and down counting is start ed. dtmn0 to dtmn2 count down to 000h, and stop when they count down further to fffh. dtmn0 to dtmn2 can automatically ge nerate a width (dead time) at which th e active levels of the positive phase (to0n0, to0n2, to0n4) and negative phase (to0n1, to0n3, to0n5) do not overlap. in this way, software processing is started by an in terrupt (intcm0n3) that o ccurs once during every pwm cycle after initial setting has been performed, and by se tting the pwm cycle and pwm duty to be used in the next cycle, it is possible to autom atically output a pwm waveform to to0n0 to to0n5 pins taking into consideration the dead-time width (in case of interrupt culling ratio of 1/1). chapter 9 timer/counter function (real-time pulse unit) 267 user?s manual u14492ej4v1ud [output waveform width in respect to set value] ? pwm cycle = (bfcmn3 + 1) t tm0n ? dead-time width t dnm = (dtrrn + 1)/f clk ? active width of positive phas e (to0n0, to0n2, to0n4 pins) = (cm0nx + 1) t tm0n ? t dnm ? active width of negative ph ase (to0n1, to0n3, to0n5 pins) = (cm0n3 ? cm0nx) t tm0n ? t dnm f clk : base clock t tm0n : tm0n count clock cm0nx: set value of cm0n0 to cm0n2 the pin level when the to0n0 to to0n5 pins are reset is the high impedance state. when the control mode is selected thereafter, the fo llowing levels are output unt il the tm0n is started. ? to0n0, to0n2, to0n4? when low active high level when high active low level ? to0n1, to0n3, to0n5? when low active low level when high active high level the active level is set with the alvto bit of t he tomrn register. the default is low active. caution if a value such that the positive phase or negative phase active width is ?0? or a negative value in the above formula, the to0n0 to to0n5 pins out put a waveform fixed to the inactive level waveform wit h active width ?0?. remark m = 0 to 2 n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 268 user?s manual u14492ej4v1ud figure 9-30. operation timing in pwm mode 2 (sawtooth wave) t t t t t cm0n3 (d) cm0n3 (e) a b cm0nx match cm0nx match bc ef bc a ef d tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx bfcmn3 cm0n3 dtmnx f/f cm0nx 0000h intcm0n3 intcm0n3 set by rising edge of tm0cen bit remarks 1. the above figure shows the timing chart when b fte3 and bften of the tmc0n register are 1, and transfer from bfcmn3 to cm0n3, or from bfcmnx to cm0nx is enabled. transfer is not performed when bfte3 = 0 or bften = 0. 2. n = 0, 1 3. x = 0 to 2 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active high case. figure 9-31 shows the overall operation image. chapter 9 timer/counter function (real-time pulse unit) 269 user?s manual u14492ej4v1ud figure 9-31. overall operation image of pwm mode 2 (sawtooth wave) cm0n3 tm0n count value to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output 0000h cm0n2 cm0n1 cm0n0 cm0n3 cm0n2 cm0n1 cm0n0 without dead time with dead time remarks 1. n = 0, 1 2. the above figure shows an active low case. since the f/f is set at the rising edge of the tm0cen bit of the tmc 0n register in the first cycle, the pwm signal can be output. chapter 9 timer/counter function (real-time pulse unit) 270 user?s manual u14492ej4v1ud (a) when bfcmnx > cm0n3 is set figure 9-32. operation timing in pwm mode 2 (sawtooth wave, bfcmnx > cm0n3) t t t cm0n3 cm0n3 cm0n3 a cm0nx match bb b bb a tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx dtmnx f/f cm0nx 0000h intcm0n3 intcm0n3 intcm0n3 set by rising edge of tm0cen bit remarks 1. n = 0, 1 2. x = 0 to 2 3. b > cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active high case. when a value greater than cm0n3 is set to bfcm nx, the positive phase si de (to0n0, to0n2, to0n4 pins) outputs a high level, and the negative phase side (to0n1, to0n3, to0n5 pins) continues to output a low level. since tm0n and cm0nx match does not oc cur, the f/f does not get reset. this feature is effective for outputting a low-level or high-level width exceeding the pw m cycle in an application such as inverter control. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. figure 9-33 shows the change timing from the 100% duty state. chapter 9 timer/counter function (real-time pulse unit) 271 user?s manual u14492ej4v1ud figure 9-33. change timing from 100% duty state (pwm mode 2) cm0n3 tm0n count value bfcm0nx 0000h cm0nx dtmnx f/f interrupt request positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) ab b c d ab b c note cm0n3 cm0n3 a c cm0nx match cm0nx match cm0n3 t t t t t intcm0n3 intcm0n3 intcm0n3 intcm0n3 note f/f is reset upon occurrence of match with cm0nx. remarks 1. n = 0, 1 2. x = 0 to 2 3. b > cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active high case. the timing at which the f/f is reset is upo n occurrence of match with cm0nx as normal. chapter 9 timer/counter function (real-time pulse unit) 272 user?s manual u14492ej4v1ud (b) when bfcmnx = cm0n3 is set figure 9-34. operation timing in pwm mode 2 (sawtooth wave, bfcmnx = cm0n3) t t t t cm0n3 cm0n3 cm0n3 a cm0nx match bb b bb a tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx dtmnx f/f cm0nx 0000h intcm0n3 intcm0n3 intcm0n3 set by rising edge of tm0cen bit a remarks 1. n = 0, 1 2. x = 0 to 2 3. b = cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active high case. if match signal intcm0n3 for tm0n and cm0n3 and the match signal for tm0n and cm0nx conflict, reset of the f/f takes precedence, so that the f/f do es not get set following match of cm0nx (= cm0n3) with tm0n. chapter 9 timer/counter function (real-time pulse unit) 273 user?s manual u14492ej4v1ud (c) when bfcmnx = 0000h is set figure 9-35. operation timing in pwm m ode 2 (sawtooth wave, bfcmnx = 0000h) t t w w w cm0n3 cm0n3 cm0n3 a cm0nx match cm0nx match cm0nx match cm0nx match bbb bb a tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx dtmnx f/f cm0nx 0000h note intcm0n3 intcm0n3 intcm0n3 a note set by rising edge of tm0cen bit remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active high case. 5. w: width between cm0n3 match and cm0n x match (timer count clock) if cm0nx = 0000h has been set, the output waveform re sulting from the tm0n count clock rate and the dtrrn set value differ. chapter 9 timer/counter function (real-time pulse unit) 274 user?s manual u14492ej4v1ud 9.1.6 operation timing (1) tm0cen bit write and tm0n timer operation timing figure 9-36 shows the timing from write of the tm0cen bi t of the tmc0n register until the tm0n timer starts operating. figure 9-36. tm0cen bit write and tm0n timer operation timing register write timing 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h f clk tm0cen bit write timing tm0n caution the operation of tm0n starts 2f clk after the register write timing. remark f clk : base clock chapter 9 timer/counter function (real-time pulse unit) 275 user?s manual u14492ej4v1ud (2) interrupt generation timing the interrupt generation timing with the count clock setti ng (prm02 to prm00 bits of the tmc0n register) to tm0n in the various modes is described below. figure 9-37. interrupt generation timing in pwm mode 0 (symmetr ic triangular wave), pwm mode 1 (asymmetric triangular wave) (a) when count clock = f clk 0002h 0001h 0002h 0001h 0000h 0001h 0002h 0001h 0000h 0001h 0002h 0001h 0000h 0001h 0002h 0001h 0000h 0001h 0002h 0001h 0000h cm0n3 tm0n intcm0n3 inttm0n f clk (b) when count clock = f clk /4 0002h 0000h 0001h 0002h 0001h 0000h cm0n3 tm0n intcm0n3 inttm0n f clk cautions 1. intcm0n3 is generated at the next f clk after detection of tm0n and cm0n3 match. 2. inttm0n is generated at the next f clk after detection of tm 0n and 0000h match. 3. inttm0n is generated at the next f clk after detection of tm0n and 0000h match, even if the count clock is 1/2, 1/8, 1/16, or 1/32. remarks 1. n = 0, 1 2. f clk : base clock chapter 9 timer/counter function (real-time pulse unit) 276 user?s manual u14492ej4v1ud figure 9-38. interrupt generation ti ming in pwm mode 2 (sawtooth wave) (a) when count clock = f clk 0002h 0001h 0002h 0000h 0001h 0002h 0000h 0001h 0002h 0000h 0001h 0002h 0000h 0001h 0002h 0000h 0001h 0002h 0000h 0001h 0002h cm0n3 tm0n intcm0n3 f clk (b) when count clock = f clk /4 0002h 0000h 0001h 0002h 0000h 0001h cm0n3 tm0n intcm0n3 f clk cautions 1. intcm0n3 is generated at the next f clk after detection of tm0n and cm0n3 match. 2. intcm0n3 is gene rated at the next f clk after detection of tm0n and cm0n3 match even if the count clock is 1/2, 1/8, 1/16, or 1/32. remarks 1. n = 0, 1 2. f clk : base clock chapter 9 timer/counter function (real-time pulse unit) 277 user?s manual u14492ej4v1ud (3) relationship between inte rrupt generation and stintn bit of tmc0n register the interrupt generation timing for the setting of the st intn bit of the tmc0n register and the interrupt culling ratio setting (bits cul02 to cul00) in the various modes is described below. if, to realize the inttm0n and intcm0n3 interrupt culling function for tm 0n, bits cul02 to cul00 of the tmc0n register are set for a culling ratio other than 1/ 1, and count operation is st arted, the interrupt output order differs according to the setting of the stintn bit when counting starts. figure 9-39. interrupt generation timing in pwm mode 0 (symmetr ic triangular wave), pwm mode 1 (asymmetric triangular wave): in case of interrupt culling ratio of 1/1 (a) when stintn bit = 0 0004h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h cm0n3 tm0cen bit tm0n intcm0n3 inttm0n f clk (b) when stintn bit = 1 0004h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h cm0n3 tm0cen bit tm0n intcm0n3 inttm0n f clk remarks 1. n = 0, 1 2. f clk : base clock chapter 9 timer/counter function (real-time pulse unit) 278 user?s manual u14492ej4v1ud figure 9-40. interrupt generation timing in pwm mode 0 (symmetr ic triangular wave), pwm mode 1 (asymmetric triangular wave): in case of interrupt culling ratio of 1/2 (a) when stintn bit = 0 0004h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 inttm0n f clk (b) when stintn bit = 1 0004h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 inttm0n f clk remarks 1. n = 0, 1 2. f clk : base clock chapter 9 timer/counter function (real-time pulse unit) 279 user?s manual u14492ej4v1ud figure 9-41. interrupt generation timi ng in pwm mode 2 (sawtooth wave): in case of interrupt culling ratio of 1/1 (a) when stintn bit = 0 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 f clk (b) when stintn bit = 1 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 f clk remarks 1. n = 0, 1 2. f clk : base clock chapter 9 timer/counter function (real-time pulse unit) 280 user?s manual u14492ej4v1ud figure 9-42. interrupt generation timi ng in pwm mode 2 (sawtooth wave ): in case of interrupt culling ratio of 1/2 (a) when stintn bit = 0 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 f clk (b) when stintn bit = 1 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 f clk remarks 1. n = 0, 1 2. f clk : base clock chapter 9 timer/counter function (real-time pulse unit) 281 user?s manual u14492ej4v1ud (4) to0n0 to to0n5 output timing figure 9-43. to0n0 to to0n5 outp ut timing in pwm mode 0 (symmetr ic triangular wave), pwm mode 1 (asymmetric triangular wave) 0003h 0002h 0008h 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0002h ffffh ffffh ffffh 0001h 0000h 0002h 0001h 0000h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h cm0nx tm0n dtmnx match signal f/f to0n0, to0n2, to0n4 to0n1, to0n3, to0n5 dtrrn f clk cm0n3 tm0cen bit remarks 1. the above figure shows the timing until the compare register and the tm0n timer match and the to0n0 to to0n5 outputs change. 2. x = 0 to 2 3. n = 0, 1 4. f clk : base clock chapter 9 timer/counter function (real-time pulse unit) 282 user?s manual u14492ej4v1ud figure 9-44. to0n0 to to0n5 output timing in pwm mode 2 (sawtooth wave) 0005h 0002h 000ah 0001h 0002h 0003h 0004h 0005h 0002h ffffh 0000h ffffh ffffh 0001h 0000h 0002h 0001h 0000h 0002h ffffh 0001h 0000h 0006h 0007h 0008h 0009h 000ah 0000h 0001h 0002h 0003h 0004h 0005h 0006h cm0nx tm0n dtmnx match signal f/f to0n0, to0n2, to0n4 to0n1, to0n3, to0n5 dtrrn f clk cm0n3 tm0cen bit remarks 1. the above figure shows the timing until the co mpare register and the tm0n timer match and the to0n0 to to0n5 outputs change. 2. x = 0 to 2 3. n = 0, 1 4. f clk : base clock chapter 9 timer/counter function (real-time pulse unit) 283 user?s manual u14492ej4v1ud 9.2 timer 1 9.2.1 features (timer 1) timers 10, 11 (tm10, tm11) are 16-bit up/down counters that perform the following operations. ? general-purpose timer mode free-running timer pwm output ? up/down counter mode udc mode a udc mode b 9.2.2 function overview (timer 1) ? 16-bit 2-phase encoder input up/down counter & general-purpose timer (tm1n): 2 channels ? compare register: 2 2 channels ? capture/compare register: 2 2 channels ? interrupt request source ? capture/compare match interrupt: 2 types 2 channels ? compare match interrupt request: 2 types 2 channels ? capture request signal: 2 types 2 channels ? the tm1n value can be latched using the valid edge of the intp1n0, intp1n1 pins corresponding to the capture/compare register as the capture trigger. ? count clocks selectable through division by prescaler (s et the frequency of the count clock to 8 mhz or less) ? base clock (f clk ): 2 types (set f clk to 16 mhz or less) f xx /2 and f xx /4 can be selected ? prescaler division ratio the following division ratios can be selected according to the base clock (f clk ). base clock (f clk ) division ratio f xx /2 selected f xx /4 selected 1/2 f xx /4 f xx /8 1/4 f xx /8 f xx /16 1/8 f xx /16 f xx /32 1/16 f xx /32 f xx /64 1/32 f xx /64 f xx /128 1/64 f xx /128 f xx /256 1/128 f xx /256 f xx /512 chapter 9 timer/counter function (real-time pulse unit) 284 user?s manual u14492ej4v1ud ? 2-phase encoder input the 2-phase encoder signal from external is used as the count clock of the time r counter with the external clock input pins (tiud1n, tcud1n). the counter mode can be selected from among the four following modes. ? mode 1: counts the input pulses of the count pulse input pin. up/down is specified by the level of one more input pin. ? mode 2: counts up/down using the respective input pulses of the up-count pulse input pin and down count pulse input pin. ? mode 3: counts up/down using the phase rela tionship of the pulses input to 2 pins. ? mode 4: counts up/down using the phase relationship of the pulses input to 2 pins. counting is done using the respective rising edges and the falling edges of the pulses. ? pwm output function in the general-purpose timer mode, 16-bit resoluti on pwm output can be output from the to1n pin. ? timer clear the following timer clear operations are perfo rmed according to the mode that is used. (a) general-purpose timer mode: timer clear operatio n is possible upon occurrence of match with cm1n0 set value. (b) up/down counter mode: the timer clear operation can be selected from among the following four conditions. (i) timer clear performed upon occurrence of match with cm1n0 set value during tm1n up-count operation, and timer clear performed upon occurr ence of match with cm1n1 set value during tm1n down-count operation. (ii) timer clear performed only by external input. (iii) timer clear performed upon occurrence of matc h between tm1n count value and cm1n0 set value. (iv) timer clear performed upon occurrence of external input and match between tm1n count value and cm1n0 set value. ? external pulse output (to1n): 1 2 channels remark f xx : internal system clock n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 285 user?s manual u14492ej4v1ud 9.2.3 basic configuration the basic configuration is shown below. table 9-4. timer 1 configuration list count clock timer note 1 note 2 register read/write generated interrupt signal capture trigger tm10 read/write ? ? cm100 read/write intcm100 ? cm101 read/write intcm101 ? cc100 read/write intcc100 intp100 cc101 read/write intcc101 intp100 or intp101 tm11 read/write ? ? cm110 read/write intcm110 ? cm111 read/write intcm111 ? cc110 read/write intcc110 intp110 timer 1 f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256 f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512 cc111 read/write intcc111 intp110 or intp111 notes 1. when f xx /2 is selected as the base clock to tm1n. 2. when f xx /4 is selected as the base clock to tm1n. remark f xx : internal system clock figure 9-45 shows the block diagram of timer 1. chapter 9 timer/counter function (real-time pulse unit) 286 user?s manual u14492ej4v1ud figure 9-45. block di agram of timer 1 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 edge detector output control selector selector edge detector clock control edge detector edge detector edge detector clr1, clr0 cm1n1 cm1n0 tm1n tm10 clear controller cc1n1 cc1n0 msel cmd tm1ubdn enmd alvt10 rlen tm1udfn tm1ovfn clear tclr selclk f clk internal bus internal bus tclr1n/ intp1n1 tcud1n/ intp1n0 tiud1n f xx /4 f xx /2 intp1n0/ intcc1n0 intp1n1 note / intcc1n1 to1n intcm1n0 intcm1n1 selector note the intp1n1 interrupt is the signal of the interrupt from the intp1n1 pin or the interrupt from the intp1n0 pin, selected by the csln bit of the csl1n register. remarks 1. n = 0, 1 2. f xx : internal system clock 3. f clk : base clock (16 mhz (max.)) chapter 9 timer/counter function (real-time pulse unit) 287 user?s manual u14492ej4v1ud (1) timers 10, 11 (tm10, tm11) tm1n is a 2-phase encoder input up/down counter and general-purpose timer. tm1n can be read/written in 16-bit units. cautions 1. write to tm1n is enabled only when the tm1cen bit of the tmc1n register is ?0? (count operation disabled). 2. it is prohibited to set the cmd bit (gen eral-purpose timer mode) and the msel bit (udc mode b) of the tumn register to ?0? and ?1?, respectively. 3. continuous reading of tm1n is prohibited. if tm1n is continuously read, the second read value may differ from the actual value. if tm 1n must be read twice, be sure to read another register between the firs t and the second read operation. correct usage example in correct usage example tm10 read tm10 read tm11 read tm10 read tm10 read tm11 read tm11 read tm11 read 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 tm10 address fffff5e0h initial value 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 tm11 address fffff600h initial value 0000h tm1n start and stop is controlled by the tm1cen bit of timer control register 1n (tmc1n). the tm1n operation consists of the following two modes. (a) general-purpose timer mode in the general-purpose timer mode, tm1n operates as a 16-bit interval timer, free-running timer, or for pwm output. counting is performed based on the clock selected by software. division by the prescaler can be selected for the count clock from among f clk /2, f clk /4, f clk /8, f clk /16, f clk /32, f clk /64, or f clk /128 with bits prm12 to prm10 of pre scaler mode register 1n (prm1n). (f clk : base clock, refer to 9.2.4 (1) timer 1/timer 2 cl ock selection register (prm02) ). chapter 9 timer/counter function (real-time pulse unit) 288 user?s manual u14492ej4v1ud (b) up/down counter mode (udc mode) in the udc mode, tm1n functions as a 16-bit up/down counter, counting based on the tcud1n and tiud1n input signals. two operation modes can be set with the msel bi t of the tumn register for this mode. (i) udc mode a (when cmd bit = 1, msel bit = 0) tm1n can be cleared by setting the clr1 an d clr0 bits of the tmc1n register. (ii) udc mode b (when cmd bit = 1, msel bit = 1) tm1n is cleared upon match with cm1n 0 during tm1n up-count operation. tm1n is cleared upon match with cm1n1 during tm1n down-count operation. when the tm1cen bit of the tmc1n register is ?1?, tm1n counts up when the operation mode is the general- purpose mode, and it counts up/down when the operation mode is the udc mode. the conditions for clearing the tm1n are classi fied as follows depending on the operation mode. table 9-5. timer 1 (tm1n) clear conditions tumn register tmc1n register operation mode cmd bit msel bit enmd bit clr1 bit clr0 bit tm1n clear 0 clearing not performed general-purpose timer mode 0 0 1 cleared upon match with cm1n0 set value 0 0 cleared only by tclr1n input 0 1 cleared upon match with cm1n0 set value during up- count operation 1 0 cleared by tclr1n input or upon match with cm1n0 set value during up-count operation udc mode a 1 0 1 1 clearing not performed udc mode b 1 1 cleared upon match with cm1n0 set value during up- count operation or upon match with cm1n1 set value during down-count operation settings other than the above setting prohibited remarks 1. n = 0, 1 2. : indicates that the set value of that bit is ignored. chapter 9 timer/counter function (real-time pulse unit) 289 user?s manual u14492ej4v1ud (2) compare registers 100, 110 (cm100, cm110) cm1n0 is a 16-bit register that al ways compares its value with the va lue of tm1n. when the value of a compare register matches the value of tm1n, an interrupt signal is generated. the interrupt generation timing in the various modes is described below. ? in the general-purpose timer mode (cmd bit of tumn register = 0) and udc mode a (msel bit of tumn register = 0), an interrupt signal (intcm1n0) is always generated upon occurrence of a match. ? in udc mode b (msel bit of tumn register = 1), an interrupt signal (intcm1n0) is generated only upon occurrence of a match during up-count operation. cm1n0 can be read/written in 16-bit units. caution when the tm1cen bit of the tmc1n register is ?1?, it is prohibited to overwrite the value of the cm1n0 register. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cm100 address fffff5e2h initial value 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cm110 address fffff602h initial value 0000h (3) compare registers 101, 111 (cm101, cm111) cm1n1 is a 16-bit register that al ways compares its value with the va lue of tm1n. when the value of a compare register matches the value of tm1n, an interrupt signal is generated. the interrupt generation timing in the various modes is described below. ? in the general-purpose timer mode (cmd bit of tumn register = 0) and udc mode a (msel bit of tumn register = 0), an interrupt signal (intcm1n1) is always generated upon occurrence of a match. ? in udc mode b (msel bit of tumn register = 1), an interrupt signal (intcm1n1) is generated only upon occurrence of a match during down count operation. cm1n1 can be read/written in 16-bit units. caution when the tm1cen bit of the tmc1n register is ?1?, it is prohibited to overwrite the value of the cm1n1 register. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cm101 address fffff5e4h initial value 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cm111 address fffff604h initial value 0000h chapter 9 timer/counter function (real-time pulse unit) 290 user?s manual u14492ej4v1ud (4) capture/compare register s 100, 110 (cc100, cc110) cc1n0 is a 16-bit register. it can be used as a capture r egister or as a compare register through specification with capture/compare control r egister n (ccrn). cc1n0 can be read/written in 16-bit units. cautions 1. when used as a capture register (cms 0 bit of ccrn register = 0), write access from the cpu is prohibited. 2. when used as a compare register (cms0 bi t of ccrn register = 1) and the tm1cen bit of the tmc1n register is ?1?, overwriting th e cc1n0 register values is prohibited. 3. when the tm1cen bit of the tmc1n register is ?0?, the capture trigger is disabled. 4. when the operation mode is changed from capture register to compare register, newly set a compare value. 5. continuous reading of cc1 n0 is prohibited. if cc1n0 is continuously read, the second read value may differ from the actual value. if cc1 n0 must be read twice, be sure to read another register between the firs t and the second read operation. correct usage example in correct usage example cc100 read cc100 read cc110 read cc100 read cc100 read cc110 read cc110 read cc110 read remark n = 0, 1 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cc100 address fffff5e6h initial value 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cc110 address fffff606h initial value 0000h (a) when set as a capture register when cc1n0 is set as a ca pture register, the valid edge of the corresponding external interrupt intp1n0 signal is detected as the capture trigger. tm1n latches the count value in synchronization with the capture trigger (capture operation). the latched value is held in the capture regist er until the next capture operation. the valid edge of external interr upts (rising edge, falling edge, both edges) is se lected with signal edge selection register 1n (sesa1n). when the cc1n0 register is specif ied as a capture register, inte rrupts are generated upon detection of the valid edge of the intp1n0 signal. (b) when set as a compare register when cc1n0 is set as a compare register, it always compares its own value with the value of tm1n. if the value of cc1n0 matches the valu e of the tm1n, cc1n0 generates an interrupt signal (intcc1n0). chapter 9 timer/counter function (real-time pulse unit) 291 user?s manual u14492ej4v1ud (5) capture/compare register s 101, 111 (cc101, cc111) cc1n1 is a 16-bit register. it can be used as a capture r egister or as a compare register through specification with capture/compare control r egister n (ccrn). cc1n1 can be read/written in 16-bit units. cautions 1. when used as a capture register (cms 1 bit of ccrn register = 0), write access from the cpu is prohibited. 2. when used as a compare register (cms1 bi t of ccrn register = 1) and the tm1cen bit of the tmc1n register is ?1?, overwriting th e cc1n1 register values is prohibited. 3. when the tm1cen bit of the tmc1n register is ?0?, the capture trigger is disabled. 4. when the operation mode is changed from capture register to compare register, newly set a compare value. 5. continuous reading of cc1 n1 is prohibited. if cc1n1 is continuously read, the second read value may differ from the actual value. if cc1 n1 must be read twice, be sure to read another register between the firs t and the second read operation. correct usage example in correct usage example cc101 read cc101 read cc111 read cc101 read cc101 read cc111 read cc111 read cc111 read remark n = 0, 1 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cc101 address fffff5e8h initial value 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cc111 address fffff608h initial value 0000h (a) when set as a capture register when cc1n1 is set as a capture register, the valid edge of either corresponding external interrupt signal intp1n0 or intp1n1 is selected with the selector, and the valid edge of the selected external interrupt signal is detected as the capture trigger. tm1n latches the count value in synchronization with the capture trigger (capture operation). the latched value is held in the capture regist er until the next capture operation. the valid edge of external interr upts (rising edge, falling edge, both edges) is se lected with signal edge selection register 1n (sesa1n). when the cc1n1 register is specif ied as a capture register, inte rrupts are generated upon detection of the valid edge of either the intp1n0 or intp1n1 signal. (b) when set as a compare register when cc1n1 is set as a compare register, it always compares its own value with the value of tm1n. if the value of cc1n1 matches the valu e of the tm1n, cc1n1 generates an interrupt signal (intcc1n1). chapter 9 timer/counter function (real-time pulse unit) 292 user?s manual u14492ej4v1ud 9.2.4 control registers (1) timer 1/timer 2 clock sel ection register (prm02) the prm02 register is used to select the base clock (f clk ) of timer 1 (tm1n) and timer 2 (tm2n). this register can be read/written in 8-bit or 1-bit units. caution always set this register be fore using the timers 1 and 2. 7 0 prm02 6 0 5 0 4 0 3 0 2 0 1 0 0 prm2 address fffff5d8h initial value 00h bit position bit name function 0 prm2 specifies the base clock (f clk ) of timer 1 (tm1n) and timer 2 (tm2n) notes 1, 2 . 0: f clk = f xx /4 1: f clk = f xx /2 notes 1. setting the tesne1 and tesne0 bits of timer 2 c ount clock/control edge select register 0 (cse0) to 11b (both rising/falling edges) is prohibited when the prm2 bit of the timer 1/timer 2 clock selection register (prm02) is 1b (f clk = f xx /2) 2. set the vswc register to 15h when the prm2 bit of the timer 1/timer 2 clock selection register (prm02) = 0b (f clk = f xx /4). remark f xx : internal system clock n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 293 user?s manual u14492ej4v1ud (2) timer unit mode registers 0, 1 (tum0, tum1) the tumn register is an 8-bit register used to spec ify the tm1n operation mode or to control the operation of the pwm output pin. tumn can be read/written in 8-bit or 1-bit units. cautions 1. changing the value of the tumn regi ster during tm1n operation (tm1cen bit of tmcn register = 1) is prohibited. 2. when the cmd bit = 0 (gen eral-purpose timer mode), setting msel bit = 1 (udc mode b) is prohibited. 7 cmd tum0 6 0 5 0 4 0 3 toe10 2 alvt10 1 0 0 msel address fffff5ebh initial value 00h 7 cmd tum1 6 0 5 0 4 0 3 toe10 2 alvt10 1 0 0 msel address fffff60bh initial value 00h bit position bit name function 7 cmd specifies tm1n operation mode. 0: general-purpose timer mode (up count) 1: udc mode (up/down count) 3 toe10 specifies timer output (to1n) enable. 0: timer output disabled 1: timer output enabled caution when cmd bit = 1 (udc mode), timer output is not performed regardless of the setting of the toe10 bit. at this time, timer output consists of the negative phase level of the level set by the alvt10 bit. 2 alvt10 specifies active level of timer output (to1n). 0: active level is high level 1: active level is low level caution when cmd bit = 1 (udc mode), timer output is not performed regardless of the setting of the toe10 bit. at this time, timer output consists of the negative phase level of the level set by the alvt10 bit. 0 msel specifies operation in udc mode (up/down count). 0: udc mode a tm1n can be cleared by setting the clr1, clr0 bits of the tmc1n register. 1: udc mode b tm1n is cleared in the following cases. ? upon match with cm1n0 during tm1n up-count operation ? upon match with cm1n1 during tm1n down-count operation when udc mode b is set, the enmd, clr1, and clr0 bits of the tmc1n register becomes invalid. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 294 user?s manual u14492ej4v1ud (3) timer control registers 10, 11 (tmc10, tmc11) the tmc1n register is used to enable/disable tm1n operat ion and to set transfer and timer clear operations. tmc1n can be read/written in 8-bit or 1-bit units. caution changing the value of bits of the tmc1n register other than the tm1cen bit during tm1n operation (tm1cen bit = 1) is prohibited. (1/2) 7 0 tmc10 <6> tm1ce0 5 0 4 0 3 rlen 2 enmd 1 clr1 0 clr0 address fffff5ech initial value 00h 7 0 tmc11 <6> tm1ce1 5 0 4 0 3 rlen 2 enmd 1 clr1 0 clr0 address fffff60ch initial value 00h bit position bit name function 6 tm1cen enables/disables tm1n operation. 0: disable tm1n count operation 1: enable tm1n count operation 3 rlen enables/disables transfer from cm1n0 to tm1n. 0: disable transfer 1: enable transfer cautions 1. when rlen = 1, the value set to cm1n0 is transferred to tm1n upon occurrence of tm1n underflow. 2. when the cmd bit of the tumn register = 0 (general-purpose timer mode), the rlen bit setting becomes invalid. 3. the rlen bit is valid only in udc mode a (cmd bit of tumn register = 1 and msel bit = 0). in the general-purpose timer mode (cmd bit = 0) and udc mode b (cmd bit = 1, msel bit = 1), a transfer operation is not executed even if the rlen bit is set to 1. 2 enmd enables/disables clearing of tm1n in general-purpose timer mode (cmd bit of tumn register = 0). 0: disable clear (free-running mode) clearing is not performed even when tm1n and cm1n0 values match. 1: enable clear clearing is performed when tm1n and cm1n0 values match. caution when the cmd bit of the tumn register = 1 (udc mode), the enmd bit setting becomes invalid. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 295 user?s manual u14492ej4v1ud (2/2) bit position bit name function controls tm1n clear operation in udc mode a. clr1 clr0 specify tm1n clear source 0 0 clear only by external input (tclr1n) 0 1 clear upon match of tm1n count value and cm1n0 set value 1 0 clear by tclr1n input or upon match of tm1n count value and cm1n0 set value 1 1 don?t clear 1, 0 clr1, clr0 cautions 1. clearing by match of the tm1n count value and cm1n0 set value is valid only during tm1n up-count operation (tm1n is not cleared during tm1n down-count operation). 2. when the cmd bit of the tumn register = 0 (general-purpose timer mode), the clr1 and clr0 bit settings are invalid. 3. when the msel bit of the tumn register = 1 (udc mode b), the clr1 and clr0 bit settings are invalid. 4. when clearing by tclr1n has been enabled with bits clr1 and clr0, clearing is performed whether the value of the tm1cen bit is 1 or 0. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 296 user?s manual u14492ej4v1ud (4) capture/compare control re gisters 0, 1 (ccr0, ccr1) the ccrn register specifies the operation mode of the capture/compare registers (cc1n0, cc1n1). ccrn can be read/written in 8-bit or 1-bit units. caution overwriting the ccrn register during tm1n operation (tm1cen bit = 1) is prohibited. 7 0 ccr0 6 0 5 0 4 0 3 0 2 0 1 cms1 0 cms0 address fffff5eah initial value 00h 7 0 ccr1 6 0 5 0 4 0 3 0 2 0 1 cms1 0 cms0 address fffff60ah initial value 00h bit position bit name function 1 cms1 specifies operation mode of cc1n1. 0: capture register 1: compare register 0 cms0 specifies operation mode of cc1n0. 0: capture register 1: compare register remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 297 user?s manual u14492ej4v1ud (5) signal edge selection regist ers 10, 11 (sesa10, sesa11) the sesa1n register is used to specif y the valid edge of exte rnal interrupt requests from external pins (intp100, intp101, intp110, intp111, tiud10, ti ud11, tcud10, tcud11, tclr10, tclr11). the correspondences between each register and the external interrupt requests it controls are as follows. ? sesa10: tiud10, tcud10, tclr10, intp100, intp101 ? sesa11: tiud11, tcud11, tclr11, intp110, intp111 the valid edge (rising edge, falling edge, or both edges ) can be specified independently for each pin. sesa1n can be read/written in 8-bit or 1-bit units. cautions 1. changing the values of the sesa1n register bits durin g tm1n operation (tm1cen bit = 1) is prohibited. 2. be sure to set (to 1) the tm1cen bit of timer control registers 10, 11 (tmc10, tmc11) even when timer 1 is not used and the tcud10/intp100, tclr10/intp101, tcud11/intp110, and tclr11/intp111 pins are used as intp100, intp101, intp110, and intp111. (1/2) 7 tesud01 sesa10 6 tesud00 5 cesud01 4 cesud00 3 ies1011 2 ies1010 1 ies1001 0 ies1000 address fffff5edh initial value 00h tiud10, tcud10 tclr10 intp101 intp100 7 tesud11 sesa11 6 tesud10 5 cesud11 4 cesud10 3 ies1111 2 ies1110 1 ies1101 0 ies1100 address fffff60dh initial value 00h tclr11 tiud11, tcud11 intp111 intp110 bit position bit name function specifies valid edge of pins tiud10, tiud11, tcud10, tcud11. tesudn1 tesudn0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 7, 6 tesudn1, tesudn0 cautions 1. the set values of the tesudn1 and tesudn0 bits are only valid in udc mode a and udc mode b. 2. if mode 4 is specified as the operation mode of tm1n (specified with prm12 to prm10 bits of prm1n register), the valid edge specifications for pins tiud1n and tcud1n (bits tesudn1 and tesudn0) are not valid. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 298 user?s manual u14492ej4v1ud (2/2) bit position bit name function specifies valid edge of pins tclr10, tclr11. cesudn1 cesudn0 valid edge 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level 5, 4 cesudn1, cesudn0 the set values of bits cesudn1 and cesudn0 and the tm1n operation are related as follows. 00: tm1n cleared after detection of falling edge of tclr1n 01: tm1n cleared after detection of rising edge of tclr1n 10: tm1n cleared status held while tclr1n input is low level 11: tm1n cleared status held while tclr1n input is high level caution the set values of the cesudn1 and cesudn0 bits are valid only in udc mode a. specifies valid edge of the pin (intp1n1/intp1n0) selected by the csln bit of the csl1n register. ies1n11 ies1n10 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 3, 2 ies1n11, ies1n10 specifies valid edge of pins intp100, intp110. ies1n01 ies1n00 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 1, 0 ies1n01, ies1n00 remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 299 user?s manual u14492ej4v1ud (6) prescaler mode registers 10, 11 (prm10, prm11) the prm1n register is used to perform the following selections. ? selection of count clock in the general-purpose timer mode (cmd bit of tumn register = 0) ? selection of count operation mode in the udc mode (cmd bit = 1) prm1n can be read/written in 8-bit or 1-bit units. cautions 1. overwriting the prm1n register during tm1n operation (t m1cen bit = 1) is prohibited. 2. when the cmd bit of the tumn register = 1 (udc mode), setting the values of bits prm12 to prm10 to 000, 001, 010, and 011 is prohibited. 3. when tm1n is in mode 4, specification of the valid edge for the tiud1n and tcud1n pins is invalid. 7 0 prm10 6 0 5 0 4 0 3 0 2 prm12 1 prm11 0 prm10 address fffff5eeh initial value 07h 7 0 prm11 6 0 5 0 4 0 3 0 2 prm12 1 prm11 0 prm10 address fffff60eh initial value 07h bit position bit name function specifies the up/down count operation mode during input of the clock rate when the internal clock of the tm1n is used, or during external clock (tiud1n) input. cmd = 0 cmd = 1 prm12 prm11 prm10 count clock count clock udc mode 0 0 0 setting prohibited 0 0 1 f clk /2 0 1 0 f clk /4 0 1 1 f clk /8 setting prohibited 1 0 0 f clk /16 mode 1 1 0 1 f clk /32 mode 2 1 1 0 f clk /64 mode 3 1 1 1 f clk /128 tiud1n mode 4 2 to 0 prm12 to prm10 remarks 1. f clk : base clock 2. n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 300 user?s manual u14492ej4v1ud (a) in general-purpose timer mode (c md bit of tumn register = 0) the count clock is fixed to the inte rnal clock. the clock rate of tm 1n is specified with bits prm12 to prm10. (b) udc mode (cmd bit of tumn register = 1) the tm1n count sources in the udc mode are as follows. operation mode tm1n operation mode 1 down count when tcud1n = high level up count when tcud1n = low level mode 2 up count upon detection of valid edge of tiud1n input down count upon detection of valid edge of tcud1n input mode 3 automatic judgment with tcud1n input level upon detection of valid edge of tiud1n input mode 4 automatic judgment upon detection of both edges of tiud1n input and both edges of tcud1n input chapter 9 timer/counter function (real-time pulse unit) 301 user?s manual u14492ej4v1ud (7) status registers 0, 1 (status0, status1) the statusn register indicates the operating status of tm1n. statusn is read-only, in 8-bit or 1-bit units. caution overwriting the statusn register during tm 1n operation (tm1cen bit = 1) is prohibited. 7 0 status0 6 0 5 0 4 0 3 0 <2> tm1udf0 <1> tm1ovf0 <0> tm1ubd0 address fffff5efh initial value 00h 7 0 status1 6 0 5 0 4 0 3 0 <2> tm1udf1 <1> tm1ovf1 <0> tm1ubd1 address fffff60fh initial value 00h bit position bit name function 2 tm1udfn tm1n underflow flag 0: no tm1n count underflow 1: tm1n count underflow caution the tm1udfn bit is cleared (to ?0?) upon completion of read access to the statusn register from the cpu. 1 tm1ovfn tm1n overflow flag 0: no tm1n count overflow 1: tm1n count overflow caution the tm1ovfn bit is cleared (to ?0?) upon completion of read access to the statusn register from the cpu. 0 tm1ubdn indicates the operating status of tm1n up/down count. 0: tm1n up count in progress 1: tm1n down count in progress caution the state of the tm1ubdn bit differs according to the mode as follows. ? the tm1ubdn bit is fixed to ?0? by hardware when the cmd bit of the tumn register = 0 (general-purpose timer mode). ? the tm1ubdn bit indicates the tm1n up/down count status when the cmd bit of the tumn register = 1 (udc mode). remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 302 user?s manual u14492ej4v1ud (8) cc101 capture input selection register (csl10) the csl10 register specifies captur e input that is input to tm10. csl10 can be read/written in 8-bit or 1-bit units. 7 0 csl10 6 0 5 0 4 0 3 0 2 0 1 0 0 csl0 address fffff5f6h initial value 00h bit position bit name function 0 csl0 specifies capture input to cc101. 0: intp101 1: intp100 (9) cc111 capture input selection register (csl11) the csl11 register specif ies capture input that is input to tm11. csl11 can be read/written in 8-bit or 1-bit units. 7 0 csl11 6 0 5 0 4 0 3 0 2 0 1 0 0 csl1 address fffff616h initial value 00h bit position bit name function 0 csl1 specifies capture input to cc111. 0: intp111 1: intp110 chapter 9 timer/counter function (real-time pulse unit) 303 user?s manual u14492ej4v1ud 9.2.5 operation (1) basic operation the following two operation modes can be selected for tm1n (n = 0, 1). (a) general-purpose timer mode (cmd bit of tumn register = 0) in the general-purpose timer mode, the tm1n operates either as a 16- bit interval timer or as a pwm output timer (count operation is up count only). the base clock (f clk ) to tm1n is selected with the timer 1/timer 2 clock selection register (prm02), and the count clock is selected with t he prescaler mode register (prm1n). (b) up/down counter mode (udc mode) (c md bit of tumn register = 1) in the udc mode, tm1n operates as a 16-bit up/down counter. external clock input (tiud1n, tcud1n pins) by prm1n register setting is used as the tm1n count clock. the udc mode is further divided into two modes according to the tm1n clear conditions. ? udc mode a (tumn register?s cmd bit = 1, msel bit = 0) the tm1n clear source can be selected as only ex ternal clear input (tclr1n), a match signal between the tm1n count value and the cm1n0 set valu e during up-count operation, or logical sum (or) of the two signals, using bits cl r1 and clr0 of the tmc1n register. tm1n can reload the value of cm1n0 upon occurrence of tm1n underflow. ? udc mode b (tumn register?s cmd bit = 1, msel bit = 1) the status of tm1n after match of the tm1n count value and cm1n0 set value is as follows. <1> in the case of up-count operation, tm1n is cleared (0000h), and the intcm1n0 interrupt is generated. <2> in the case of down-count operatio n, the tm1n count value is decremented ( ? 1). the status of tm1n after match of the tm1n count value and cm1n1 set value is as follows. <1> in the case of up-count operation, t he tm1n count value is incremented (+1). <2> in the case of down-count operation, tm1n is cleared (0000h), and the intcm1n1 interrupt is generated. chapter 9 timer/counter function (real-time pulse unit) 304 user?s manual u14492ej4v1ud (2) operation in genera l-purpose timer mode tm1n can perform the following operations in the general-purpose timer mode. (a) interval operation tm1n and cm1n0 always compare their values an d the intcm1n0 interrupt is generated upon occurrence of a match. tm1n is cleared (0000h ) at the count clock following the match. furthermore, when one more count clock is input, tm 1n counts up to 0001h. the interval time can be calculated with the following formula. interval time = (cm1n0 value + 1) tm1n count clock rate caution interval operation can be achieved by setting the enmd bit of the tmc1n register to ?1?. (b) free-running operation tm1n performs full count operation from 0000h to ffffh, and after t he tm1ovfn bit of the statusn register is set (to ?1?), tm1n is cleared and resu mes counting. the free-running cycle can be calculated with the following formula. free-running cycle = 65536 tm1n count clock rate caution the free-running operation can be achieved by setting the enmd bit of the tmc1n register to ?0?. (c) compare function tm1n connects two compare register (cm1n0, cm1n 1) channels and two capture/compare register (cc1n0, cc1n1) channels. when the tm1n count value and the set value of one of the compare registers match, a match interrupt (intcm1n0, intcm1n1, intcc1n0 note , intcc1n1 note ) is output. particularly in the case of interval operation, tm 1n is cleared upon generation of the intcm1n0 interrupt. note this match interrupt is generated when cc1n0 and cc1n1 are set to the compare register mode. chapter 9 timer/counter function (real-time pulse unit) 305 user?s manual u14492ej4v1ud (d) capture function tm1n connects two capture/compare r egister (cc1n0, cc1n1) channels. when cc1n0 and cc1n1 are set to the capture regist er mode, the value of tm1n is captured in synchronization with the corresponding capture trigger signal. furthermore, an interrupt request (intcc1n0, intcc1 n1) is generated by the intp1n0, intp1n1 input signals. table 9-6. capture trigger signal (t m1n) to 16-bit capture register capture register capture trigger signal cc1n0 intp1n0 cc1n1 intp1n0 or intp1n1 remarks 1. cc1n0 and cc1n1 are capture/compare register s. which of these registers is used is specified with capture/compare control register n (ccrn). 2. n = 0, 1 the valid edge of the capture tri gger is specified by signal edge se lection register 1n (sesa1n). if both the rising edge and the falling edge are selected as t he capture triggers, it is possible to measure the input pulse width from external. if a single edge is selected as the capture tr igger, the input pulse cycle can be measured. (e) pwm output operation pwm output operation is performed from the to1n pin by setting tm1n to the general-purpose timer mode (cmd bit = 0) using timer unit mode register n (tumn). the resolution is 16 bits , and the count clock c an be selected from among seven internal clocks (f clk /2, f clk /4, f clk /8, f clk /16, f clk /32, f clk /64, f clk /128). chapter 9 timer/counter function (real-time pulse unit) 306 user?s manual u14492ej4v1ud figure 9-46. tm1n blo ck diagram (during pwm output operation) tm1n (16 bits) compare register (cm1n0) compare register (cm1n1) s intcm1n0 intcm1n1 alvt10 tumn register clear 16 16 to1n q r f clk /2 f clk /4 f clk /8 f clk /16 f clk /32 f clk /64 f clk /128 caution be sure to set the count cl ock of tm1n to 8 mhz or lower. remarks 1. f clk : base clock 2. n = 0, 1 (i) description of operation the cm1n0 register is a compare register used to set the pwm output cycle. when the value of this register matches the value of tm1n, the intcm1n0 interrupt is generated. compare match is saved by hardware, and tm1n is cleared at t he next count clock after the match. the cm1n1 register is a compare register used to set the pwm output duty. set the duty required for the pwm cycle. figure 9-47. pwm signal output e xample (when alvt10 bit = 0 is set) cm1n0 set value cm1n1 set value tm1n to1n intcm1n0 intcm1n1 cautions 1. changing the values of the cm1n0 and cm1n1 registers is prohibited during tm1n operation (tm1cen bit of tmc1n register = 1). 2. changing the value of the alvt10 bit of the tumn register is prohibited during tm1n operation. 3. pwm signal output is performed from the se cond pwm cycle after the tm1cen bit is set (to ?1?). chapter 9 timer/counter function (real-time pulse unit) 307 user?s manual u14492ej4v1ud (3) operation in udc mode (a) overview of operation in udc mode the count clock input to tm1n in the udc mode (cmd bit of tumn register = 1) can only be external input from the tiud1n and tcud1n pins. up/down count judgment in the udc mode is determined based on the phase difference of the tiud1n and tcud 1n pin inputs according to the prm1n register setting (there is a total of four choices). table 9-7. list of count operations in udc mode prm1n register prm12 prm11 prm10 operation mode tm1n operation 1 0 0 mode 1 down count when tcud1n = high level up count when tcud1n = low level 1 0 1 mode 2 up count upon detection of valid edge of tiud1n input down count upon detection of valid edge of tcud1n input 1 1 0 mode 3 automatic judgment in tcud1n input level upon detection of valid edge of tiud1n input 1 1 1 mode 4 automatic judgment upon detection of both edges of tiud1n input and both edges of tcud1n input the udc mode is further divided into two modes acco rding to the tm1n clear conditions (count operation is performed only with tiud1n, tcud1n input in both modes). ? udc mode a (tumn register?s cmd bit = 1, msel bit = 0) the tm1n clear source can be selected as only ex ternal clear input (tclr1n), a match signal between the tm1n count value and the cm1n0 set valu e during up-count operation, or logical sum (or) of the two signals, using bits cl r1 and clr0 of the tmc1n register. tm1n can transfer the value of cm1n0 upon occurrence of tm1n underflow. ? udc mode b (tumn register?s cmd bit = 1, msel bit = 1) the status of tm1n after match of the tm1n count value and cm1n0 set value is as follows. <1> in the case of up-count operation, tm1n is cleared (0000h), and the intcm1n0 interrupt is generated. <2> in the case of down-count operation, the tm1n count value is decremented ( ? 1). the status of tm1n after match of the tm1n count value and cm1n1 set value is as follows. <1> in the case of up-count operation, t he tm1n count value is incremented (+1). <2> in the case of down-count operation, tm1n is cleared (0000h), and the intcm1n1 interrupt is generated. chapter 9 timer/counter function (real-time pulse unit) 308 user?s manual u14492ej4v1ud (b) up/down count operation in udc mode tm1n up/down count judgment in the udc mode is determined based on the phase difference of the tiud1n and tcud1n pin inputs according to the prm1n register setting. (i) mode 1 (prm12 bit = 1, prm11 bit = 0, prm10 bit = 0) in mode 1, the following count operations are performed based on t he level of the tcud1n pin upon detection of the valid edge of the tiud1n pin. ? tm1n down-count operation when tcud1n pin = high level ? tm1n up-count operation when tcud1n pin = low level figure 9-48. mode 1 (when rising edge is specified as valid edge of tiud1n pin) tiud1n tcud1n tm1n 0006h 0007h down count up count 0005h 0004h 0005h 0006h 0007h remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 309 user?s manual u14492ej4v1ud figure 9-49. mode 1 (when rising edge is specified as valid edge of tiud1n pin): in case of simultaneous ti ud1n, tcud1n pin edge timing 0007h tiud1n tcud1n tm1n 0006h down count up count 0005h 0004h 0005h 0006h 0007h remark n = 0, 1 (ii) mode 2 (prm12 bit = 1, prm11 bit = 0, prm10 bit = 1) the count conditions in mode 2 are as follows. ? tm1n up-count upon detection of valid edge of tiud1n pin ? tm1n down-count upon detection of valid edge of tcud1n pin caution if the count clock is simultaneously input to the tiud1n pi n and the tcud1n pin, count operation is not performed and th e immediately preceding value is held. figure 9-50. mode 2 (when rising edge is speci fied as valid edge of tiud1n, tcud1n pins) 0006h tiud1n tcud1n tm1n 0007h 0008h up count hold value down count 0007h 0006h 0005h remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 310 user?s manual u14492ej4v1ud (iii) mode 3 (prm12 = 1, prm11 = 1, prm10 = 0) in mode 3, when two signals 90 degrees out of phas e are input to the tiud1n and tcud1n pins, the level of the tcud1n pin is sampled at the input of the valid edge of the tiud1n pin (refer to figure 9-51 ). if the tcud1n pin level sampled at the valid edge input to the tiud1n pin is low, tm1n counts down when the valid edge is input to the tiud1n pin. if the tcud1n pin level sampled at the valid edge in put to the tiud1n pin is high, tm1n counts up when the valid edge is input to the tiud1n pin. figure 9-51. mode 3 (when rising edge is specified as valid edge of tiud1n pin) 0007h tiud1n tcud1n tm1n 0008h up count down count 0009h 000ah 0009h 0008h 0007h remark n = 0, 1 figure 9-52. mode 3 (when rising edge is specified as valid edge of tiud1n pin): in case of simultaneous ti ud1n, tcud1n pin edge timing 0007h tiud1n tcud1n tm1n 0008h up count down count 0009h 000ah 0009h 0008h 0007h remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 311 user?s manual u14492ej4v1ud (iv) mode 4 (prm12 = 1, prm11 = 1, prm10 = 1) in mode 4, when two signals out of phase are input to the tiud1n and tcud1n pins, up/down operation is automatically judged and counting is performed according to the timing shown in figure 9-53 . in mode 4, counting is executed at both the rising and falling edges of the two signals input to the tiud1n and tcud1n pins. therefor e, tm1n counts four times per cycle of an input signal ( 4 count). figure 9-53. mode 4 tiud1n tcud1n tm1n 0004h 0003h 0006h 0005h 0008h 0007h 000ah 0009h 0008h 0009h 0006h 0007h 0005h up count down count cautions 1. when mode 4 is specifi ed as the operation mode of tm1n , the valid edge specifications for pins tiud1n and tcud1n are not valid. 2. if the tiud1n pin edge an d tcud1n pin edge are input simu ltaneously in mode 4, tm1n continues the same count operation (up or down) it was performing immediately before the input. chapter 9 timer/counter function (real-time pulse unit) 312 user?s manual u14492ej4v1ud (c) operation in udc mode a (i) interval operation the operations at the count clock following matc h of the tm1n count value and the cm1n0 set value are as follows. ? in case of up-count operation: tm1n is cleared (0000h) and the intcm1n0 interrupt is generated. ? in case of down-count operation: the tm1n count value is decremented ( ? 1) and the intcm1n0 interrupt is generated. remark the interval operation can be comb ined with the transfer operation. (ii) transfer operation the operations at the next count clock after the count value of tm1n becomes 0000h during tm1n count down operation are as follows. ? in case of down-count operation: the data held in cm1n0 is transferred. ? in case of up-count operation: the tm1n count value is incremented (+1). remarks 1. transfer enable/disable can be set with the rlen bit of the tmc1n register. 2. the transfer operation can be combin ed with the interval operation. figure 9-54. example of tm1n operation when inter val operation and transfer operation are combined tm1n and cm1n0 match & timer clear tm1n underflow & cm1n0 data transfer tm1n count value cm1n0 set value up count down count 0000h remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 313 user?s manual u14492ej4v1ud (iii) compare function tm1n connects two compare register (cm1n0, cm1 n1) channels and two capture/compare register (cc1n0, cc1n1) channels. when the tm1n count value and the set value of o ne of the compare registers match, a match interrupt (intcm1n0, intcm1n1, intcc1n0 note , intcc1n1 note ) is output. note this match interrupt is generated when cc1n0 and cc1n1 are set to the compare register mode. (iv) capture function tm1n connects two capture/compare r egister (cc1n0, cc1n1) channels. when cc1n0 and cc1n1 are set to the capture register mode, the value of tm1n is captured in synchronization with the corresponding capture trigger signal. when the tm1n is set to the capture register m ode, a capture interrupt (intcc1n0, intcc1n1) is generated upon detection of the valid edge. chapter 9 timer/counter function (real-time pulse unit) 314 user?s manual u14492ej4v1ud (d) operation in udc mode b (i) basic operation the operations at the nex t count clock after the count value of tm1n and the cm1n0 set value match when tm1n is in udc mode b are as follows. ? in case of up-count operation: tm1n is cleared (0000h) and the intcm1n0 interrupt is generated. ? in case of down-count operation: the tm1n count value is decremented ( ? 1). the operations at the nex t count clock after the count value of tm1n and the cm1n1 set value match when tm1n is in udc mode b are as follows. ? in case of up-count operation: the tm1n count value is incremented (+1). ? in case of down-count operation: tm1n is cleared (0000h) and the intcm1n1 interrupt is generated. figure 9-55. example of tm1n operation in udc mode cm1n0 set value cm1n1 set value tm1n count value clear tm1n not cleared if count clock counts down following match clear tm1n not cleared if count clock counts up following match remark n = 0, 1 (ii) compare function tm1n connects two compare register (cm1n0, cm1 n1) channels and two capture/compare register (cc1n0, cc1n1) channels. when the tm1n count value and the set value of o ne of the compare registers match, a match interrupt (intcm1n0 (only during up-count oper ation), intcm1n1 (only during down-count operation), intcc1n0 note , intcc1n1 note ) is output. note this match interrupt is generated when cc1n0 and cc1n1 are set to the compare register mode. (iii) capture function tm1n connects two capture/compare r egister (cc1n0, cc1n1) channels. when cc1n0 and cc1n1 are set to the capture register mode, the value of tm1n is captured in synchronization with the corresponding capture trigger signal. when the tm1n is set to the capture register m ode, a capture interrupt (intcc1n0, intcc1n1) is generated upon detection of the valid edge. chapter 9 timer/counter function (real-time pulse unit) 315 user?s manual u14492ej4v1ud 9.2.6 supplementary descriptio n of internal operation (1) clearing of count value in udc mode b when tm1n is in udc mode b, the count value clear operation is as follows. ? in case of tm1n up-count operation: tm1n is cleared upon match with cm1n0 ? in case of tm1n down-count operation: tm1n is cleared upon match with cm1n1 figure 9-56. clear operation upon match with cm1n0 during tm1n up-count operation count clock (rising edge set as valid edge) cm1n0 fffeh clear tm1n (not clear tm1n) tm1n ffffh 0000h (fffeh) 0001h (fffdh) ffffh up count up count (down count) remarks 1. n = 0, 1 2. items between parentheses in the above fi gure apply to down-count operation. figure 9-57. clear operation upon match with cm1n1 during tm1n down-count operation count clock (rising edge set as valid edge) cm1n1 00ffh tm1n 00feh 0000h (00ffh) ffffh (0100h) 00feh up count down count (up count) clear tm1n (not clear tm1n) remarks 1. n = 0, 1 2. items between parentheses in the above fi gure apply to up-count operation. chapter 9 timer/counter function (real-time pulse unit) 316 user?s manual u14492ej4v1ud (2) clearing of count value upon occurrence of compare match the internal operation during tm1n clear operation upo n occurrence of a compare match is as follows. figure 9-58. count value clear operation upon compare match count clock (rising edge set as valid edge) cm1n0 fffeh tm1n ffffh 0000h (fffeh) 0001h (fffdh) ffffh up count up count (down count) clear tm1n (not clear tm1n) caution the operations at the next count clock afte r the count value of tm1n and the cm1n0 set value match are as follows. ? in case of count: clear operation is performed. ? in case of down count: clear operation is not performed. remarks 1. n = 0, 1 2. items between parentheses in the above fi gure apply to down-count operation. chapter 9 timer/counter function (real-time pulse unit) 317 user?s manual u14492ej4v1ud (3) transfer operation the internal operation during tm1n transfer operation is as follows. figure 9-59. internal operat ion during transfer operation count clock (rising edge set as valid edge) cm1n0 0001h transfer operation is performed. (transfer operation is not performed.) tm1n 0000h ffffh (0001h) fffeh (0002h) ffffh down count down count (up count) caution the count operations after the tm1n count value becomes 0000h are as follows. ? in case of down count: transf er operation is performed. ? in case of up count: transfer operation is not performed. remarks 1. n = 0, 1 2. items between parentheses in the above fi gure apply to up-count operation. chapter 9 timer/counter function (real-time pulse unit) 318 user?s manual u14492ej4v1ud (4) interrupt signal outpu t upon compare match an interrupt signal is output when the count value of tm1n matches the set value of the cm1n0, cm1n1, cc1n0 note , or cc1n1 note register. the interrupt generation timing is as follows. note when cc1n0 and cc1n1 are set to the compare register mode. figure 9-60. interrupt output upon compare match (cm1n1 with operation mode se t to general-purpose timer m ode and count clock set to f clk /2) count clock f clk cm1n1 0007h tm1n internal match signal intcm1n1 0008h 000bh 0009h 0009h 000ah remarks 1. n = 0, 1 2. f clk : base clock an interrupt signal such as illustrated in figure 9-60 is output at the next count following match of the tm1n count value and the set value of a corresponding compare register. (5) tm1ubdn flag (bit 0 of statusn register) operation in the udc mode (cmd bit of tumn register = 1), the tm1ubdn flag changes as follows during tm1n up/down count operation at every internal operation clock. figure 9-61. tm1ubdn flag operation count clock tm1ubdn 0001h 0000h tm1n 0000h 0001h 0001h 0000h remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 319 user?s manual u14492ej4v1ud 9.3 timer 2 9.3.1 features (timer 2) timers 20, 21 (tm20, tm21) are 16-bit general-purpose timer units that perform the following operations. ? pulse interval or frequency measurement and programmable pulse output ? interval timer ? pwm output timer ? 32-bit capture timer when 2 timer/count er channels are connected in cascade (in this case, four 32-bit captur e register channels can be used.) 9.3.2 function overview (timer 2) ? 16-bit timer/counter (tm20, tm21): 2 channels ? bit length timer 2 registers (tm20, tm21): 16 bits during cascade operation: 32 bits (higher 16 bits: tm21, lower 16 bits: tm20) ? capture/compare register in 16-bit mode: 6 in 32-bit mode: 4 (capture mode only) ? count clock division selectable by prescaler (set the frequency of the count clock to 8 mhz or less) ? base clock (f clk ): 2 types (set f clk to 16 mhz or less) f xx /2 and f xx /4 can be selected ? prescaler division ratio the following division ratios can be selected according to the base clock (f clk ). base clock (f clk ) division ratio f xx /2 selected f xx /4 selected 1/2 f xx /4 f xx /8 1/4 f xx /8 f xx /16 1/8 f xx /16 f xx /32 1/16 f xx /32 f xx /64 1/32 f xx /64 f xx /128 1/64 f xx /128 f xx /256 1/128 f xx /256 f xx /512 chapter 9 timer/counter function (real-time pulse unit) 320 user?s manual u14492ej4v1ud ? interrupt request sources ? compare-match interrupt request: 6 types perform comparison with sub-channel n capture/compar e register and generate the intcc2n interrupt upon compare match. ? timer/counter overflow interrupt request: 2 types the inttm20 (inttm21) interrupt is generated when t he count value of tm20 (tm21) becomes ffffh. ? capture request the count values of tm20, tm21 can be latched using external pin (intp2n) notes 1, 2 , tm10, tm11 interrupt signals (intcm100, intcm101) and interrupt r equests by software as capture triggers. ? pwm output function control of the outputs of pins to21 to to24 in the compare mode and pwm output can be performed using the compare match timing of sub-channels 1 to 4 and the zero count signal of the timer/counter. ? timer count operation with external clock input note 2 timer count operation can be performed wit h the pin ti2 clock input signal. ? timer count enable operation note 3 with external pin input note 2 timer count enable operation can be perfor med with the tclr2 pin input signal. ? timer/counter clear operation notes 3, 4 with external pin input note 2 timer/counter clear operation can be per formed with the tclr2 pin input signal. ? up/down count control notes 3, 5 with external pin input note 2 up/down count operation in the compare mode can be controlled with the tclr2 pin input signal. ? output delay operation a clock-synchronized output delay can be added to the output signal of pins to21 to to24. this is effective as an emi countermeasure. ? input filter an input filter can be inserted at the input stage of external pins (t i2, intp20 to intp25, tclr2) and the tm10, tm11 interrupt signals (refer to 14.4.3 (1) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) ). notes 1. for the registers used to specify the valid edge for external interrupt requests (intp20 to intp25) to timer 2, refer to 7.3.8 (4) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) . 2. the pairs ti2 and intp20, to21 and intp21, to22 and intp22, to23 and intp23, to24 and intp24, tclr2 and intp25 are each alternate function pins. 3. the count enable operation for t he timer/counter through external pin input, timer/counter clear operation, and up/down count control cannot be performed combined all at the same time. 4. in the case of 32-bit cascade connection, clear operation by external pin input (tclr2) cannot be performed. 5. up/down count control using 32-bit ca scade connection cannot be performed. remark f xx : internal system clock n = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) 321 user?s manual u14492ej4v1ud 9.3.3 basic configuration the basic configuration is shown below. table 9-8. timer 2 configuration list count clock timer note 1 note 2 register read/write generated interrupt signal capture trigger other functions tm20 ? inttm20 ? note 3 tm21 ? inttm21 ? note 3 cvse00 read/write intcc20 intp20/intp25 ? cvse10 read/write intcc21 intp21/intp24 buffer/ note 4 cvse20 read/write intcc22 intp22/intp23 buffer/ note 4 cvse30 read/write intcc23 intp23/intp22 buffer/ note 4 cvse40 read/write intcc24 intp24/intp21 buffer/ note 4 cvse50 read/write intcc25 intp25/intp20 ? cvpe40 read intcc24 intp24/intp21 note 4 cvpe30 read intcc23 intp23/intp22 note 4 cvpe20 read intcc22 intp22/intp23 note 4 timer 2 f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256 f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512 cvpe10 read intcc21 intp21/intp24 note 4 notes 1. when f xx /2 is selected as the base clock input to tm2n 2. when f xx /4 is selected as the base clock input to tm2n 3. cascade operation with tm20 and tm21 is enabled. 4. cascade operation using the cvsen0 register and cvpen0 register is enabled (n = 1 to 4). remark f xx : internal system clock chapter 9 timer/counter function (real-time pulse unit) 322 user?s manual u14492ej4v1ud the following shows the capture/ compare operation sources. table 9-9. capture/comp are operation sources register sub-channel no. timer to be captured timer to be compared timer captured in 32-bit cascade connection cvse00 0 tm20 tm20 ? cvpen0 n tm21 when bfeey bit of cmsem0 register = 0 tm20 when tb1ey, tb0ey bits of cmsem0 register = 01 tm21 cvsen0 n tm20 when bfeey bit of cmsem0 register = 0 used as buffer tm20 cvse50 5 tm21 tm21 ? remark n = 1 to 4 m: m = 12 when n = 1, 2, m = 34 when n = 3, 4 y: y = 1, 2 when m = 12, y = 3, 4 when m = 34 the following shows the output level sources during timer output. table 9-10. output level s ources during timer output to2n toggle mode 0 (otmen1, otmen0 = 00) toggle mode 1 (otmen1, otmen0 = 01) toggle mode 2 (otmen1, otmen0 = 10) toggle mode 3 (otmen1, otmen0 = 11) trigger compare match of sub- channel n compare match of sub- channel n tm20 = 0 compare match of sub- channel n tm21 = 0 compare match of sub- channel n compare match of sub- channel n + 1 output level active output inactive output active output inactive output active output inactive output active output inactive output remarks 1. n = 1 to 4 2. otmen1, otmen0: bits 13, 12, 9, 8, 5, 4, 1, and 0 of timer 2 out put control register 0 (octle0) figure 9-62 shows the block diagram of timer 2. chapter 9 timer/counter function (real-time pulse unit) 323 user?s manual u14492ej4v1ud figure 9-62. block di agram of timer 2 ed1 eclr cnt = max. cnt = 0 r cnt = max. cnt = 0 r ct ed2 s/t ra rb rn output circuit 1 s/t ra rb rn output circuit 2 s/t ra rb rn output circuit 3 ed1 reload2a reload2b ed2 ed1 eclr ct ctc casc ed2 sub-channel 4 cvse40 (16-bit) cvpe40 (16-bit) ed1 reload2a reload2b ed2 sub-channel 1 cvse10 (16-bit) cvpe10 (16-bit) ed1 reload2a reload2b ed2 sub-channel 2 cvse20 (16-bit) cvpe20 (16-bit) ed1 reload2a reload2b ed2 sub-channel 3 cvse30 (16-bit) cvpe30 (16-bit) s/t ra rb rn output circuit 4 cvse00 (16-bit) tm20 (16-bit) intcc20 intcc21 intcc22 intcc23 intcc24 intcc25 inttm20 to21 to22 to23 to24 inttm21 cvse50 (16-bit) tm21 (16-bit) tine5 edge selection tine4 edge selection tine3 edge selection tine2 edge selection tine1 edge selection tine0 edge selection input filter input filter input filter input filter input filter input filter timer connection selector tcounte1 edge selection tcounte0 f clk edge selection tclr2/ intp25 ti2/ intp20 f xx /2 f xx /4 intp24 intp23 intp22 intp21 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 sub-channel 5 sub-channel 0 selector selector selector remark f xx : internal system clock f clk : base clock (16 mhz (max.)) chapter 9 timer/counter function (real-time pulse unit) 324 user?s manual u14492ej4v1ud table 9-11. meaning of si gnals in block diagram signal name meaning casc note 1 tm21 count signal input in 32-bit mode cnt count value of timer 2 (cnt = max.: maximu m value count signal output of timer 2 (generated when tm2n = ffffh), cnt = 0: zero count signal output of timer 2 (generated when tm2n = 0000h)) ct tm2n count signal input in 16-bit mode ctc tm21 count signal input in 32-bit mode eclr external control signal input from tclr2 input ed1, ed2 capture event signal input from edge selector r note 2 compare match signal input (sub-channel 0/5) ra tm20 zero count signal input (reset signal of output circuit) rb tm21 zero count signal input (reset signal of output circuit) reload2a tm20 zero count signal input (generated when tm20 = 0000h) reload2b tm21 zero count signal input (generated when tm21 = 0000h) rn sub-channel x interrupt signal inpu t (reset signal of output circuit) s/t sub-channel x interrupt signal inpu t (set signal of output circuit) tcounte0, tcounte1 timer 2 count enable signal input tinem timer 2 sub-channel m capture event signal input notes 1. tm21 performs count operation when casc (cnt = max. for tm20) is generated and the rising edge of ctc is detected in the 32-bit mode. 2. tm20/tm21 clear by sub-channel 0/5 compare ma tch or count direction can be controlled. remark m = 0 to 5 n = 0, 1 x = 1 to 4 chapter 9 timer/counter function (real-time pulse unit) 325 user?s manual u14492ej4v1ud (1) timers 20, 21 (tm20, tm21) the features of tm2n are listed below. ? free-running counter that enables counter clearing by compare match of sub-channel 0 and sub-channel 5 ? can be used as a 32-bit capture timer when tm20 and tm21 are connected in cascade. ? up/down control, counter clear, and count operation enable/disable can be controlled with external pin (tclr2). ? counter up/down and clear operation c ontrol method can be set by software. ? stop upon occurrence of count value 0 and count op eration start/stop can be c ontrolled by software. (2) timer 2 sub-channel 0 capture /compare register (cvse00) the cvse00 register is a 16-bit capture/ compare register of sub-channel 0. in the capture register mode, it captures the tm20 count value. in the compare register mode, it detects match with tm20. this register can be read/written in 16-bit units. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse00 address fffff660h initial value 0000h chapter 9 timer/counter function (real-time pulse unit) 326 user?s manual u14492ej4v1ud (3) timer 2 sub-channel n main capture/com pare register (cvpen0) (n = 1 to 4) the cvpen0 register is a sub-channel n 16 -bit main capture/compare register. in the capture register mode, this register captures the value of tm21 when the bfeen bit of the cmsem0 register = 0 (m = 12, 34). when the bfeen bit = 1, th is register holds the value of tm20 or tm21. in the compare register mode, a match between this register and tm2x is detected (tm2x = timer/counter selected by tb1en and tb0en bits). if the capture register mode is selected in the 32-bit mode (value of tb1en, tb0en bits of cmsem0 register = 11b), this register captures the c ontents of tm21 (higher 16 bits). this register is read-only, in 16-bit units. caution when the bfeen bit = 1, a compare match occurs on star ting the timer in the compare register mode because the values of both th e tm2x and cvpen0 registers are 0 after reset (tm2x = timer/counter selected by tb1en and tb0e n bits, n = 1 to 4). after that, the value of the sub register (cvsen0) is wri tten to the main register (cvpen0). 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvpe10 address fffff652h initial value 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvpe20 address fffff656h initial value 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvpe30 address fffff65ah initial value 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvpe40 address fffff65eh initial value 0000h chapter 9 timer/counter function (real-time pulse unit) 327 user?s manual u14492ej4v1ud (4) timer 2 sub-channel n s ub capture/compare register (cvsen0) (n = 1 to 4) the cvsen0 register is a sub-channel n 16-bit sub capture/compare register. in the compare register mode, this r egister can be used as a buffer. in the capture register mode, this register captures the value of tm20 when the bfeen bi t of the cmsem0 register = 0 (m = 12, 34). if the capture register mode is sele cted in the 32-bit mode (value of tb1en and tb0en bits of cmsem0 register = 11b), this register captures the contents of tm20 (lower 16 bits). the cvsen0 register can be written on ly in the compare register mode. if this register is written in the capture register mode, the contents wr itten to cvsen0 register will be lost. this register can be read/written in 16-bit units. caution when the bfeen bit = 1, a compare match occurs on star ting the timer in the compare register mode because the values of both th e tm2x and cvpen0 registers are 0 after reset (tm2x = timer/counter selected by tb1en and tb0e n bits, n = 1 to 4). after that, the value of the sub register (cvsen0) is wri tten to the main register (cvpen0). 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse10 address fffff650h initial value 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse20 address fffff654h initial value 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse30 address fffff658h initial value 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse40 address fffff65ch initial value 0000h (5) timer 2 sub-channel 5 capture /compare register (cvse50) the cvse50 register is a sub-channel 5 16-bit capture/compare register. in the capture register mode, it c aptures the count value of tm21. in the compare register mode, it detects match with tm21. this register can be read/written in 16-bit units. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse50 address fffff662h initial value 0000h chapter 9 timer/counter function (real-time pulse unit) 328 user?s manual u14492ej4v1ud 9.3.4 control registers (1) timer 1/timer 2 clock sel ection register (prm02) the prm02 register is used to select the base clock (f clk ) of timer 1 and timer 2. this register can be read/written in 8-bit or 1-bit units. caution always set this register be fore using timer 1 and timer 2. 7 0 prm02 6 0 5 0 4 0 3 0 2 0 1 0 0 prm2 address fffff5d8h initial value 00h bit position bit name function 0 prm2 specifies the base clock (f clk ) of timer 1 and timer 2 notes 1, 2 . 0: f clk = f xx /4 1: f clk = f xx /2 notes 1. setting the tesne1 and tesne0 bits of timer 2 c ount clock/control edge select register 0 (cse0) to 11b (both rising/falling edges) is prohibited when the prm2 bit of the timer 1/timer 2 clock selection register (prm02) is 1b (f clk = f xx /2) 2. set the vswc register to 15h when the prm2 bit of the timer 1/timer 2 clock selection register (prm02) = 0b (f clk = f xx /4). remark f xx : internal system clock n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 329 user?s manual u14492ej4v1ud (2) timer 2 clock stop register 0 (stopte0) the stopte0 register is used to stop t he operation clock input to timer 2. this register can be read/written in 16-bit units. when the higher 8 bits of the stop te0 register are used as the stopte 0h register, and the lower 8 bits are used as the stopte0l register, the stopte0h regist er can be read/written in 8-bit or 1-bit units, and the stopte0l register is read-only, in 8-bit units. cautions 1. initialize timer 2 when the stfte bit = 0. timer 2 cannot be initialized when the stfte bit = 1. 2. if, following initialization, the value of the stfte bit is made ?1?, the initialized state is maintained. 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 <15> stfte 1 0 0 0 stopte0 address fffff640h initial value 0000h bit position bit name function 15 stfte stops the operation clock to timer 2. 0: normal operation 1: stop operation clock to timer 2 chapter 9 timer/counter function (real-time pulse unit) 330 user?s manual u14492ej4v1ud (3) timer 2 count clock/control e dge selection register 0 (cse0) the cse0 register is used to specify the tm2n co unt clock and the control valid edge (n = 0, 1). this register can be read/written in 16-bit units. when the higher 8 bits of the cse0 register are used as the cse0h register, and the lower 8 bits are used as the cse0l register, they can be read/written in 8-bit or 1-bit units. (1/2) 14 0 13 0 12 0 2 cse02 3 cse10 4 cse11 5 cse12 6 cese0 7 cese1 8 tes0e0 9 tes0e1 10 tes1e0 11 tes1e1 15 0 1 cse01 0 cse00 cse0 address fffff642h initial value 0000h bit position bit name function specifies the valid edge of the tm2n inte rnal count clock (tcounten) signal. tesne1 tesne0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges notes 1, 2 11, 10, 9, 8 tesne1, tesne0 specifies the valid edge of the tm2n external clear input (tclr2). cese1 cese0 valid edge 0 0 falling edge 0 1 rising edge 1 0 through input (no clear operation) 1 1 both rising and falling edges 7, 6 cese1, cese0 selects internal count clock (tcounten) of tm2n. csen2 csen1 csen0 count clock 0 0 0 f clk /2 note 1 0 0 1 f clk /4 0 1 0 f clk /8 0 1 1 f clk /16 1 0 0 f clk /32 1 0 1 f clk /64 1 1 0 f clk /128 1 1 1 selects input signal from external clock input pin (ti2) as clock. 5 to 3, 2 to 0 csen2, csen1, csen0 chapter 9 timer/counter function (real-time pulse unit) 331 user?s manual u14492ej4v1ud (2/2) notes 1. setting the tesne1 and tesne0 bits of timer 2 c ount clock/control edge select register 0 (cse0) to 11b (both rising/falling edges) is prohibited when the prm2 bit of the timer 1/timer 2 clock selection register (prm02) is 1b (f clk = f xx /2) 2. set the vswc register to 15h when the prm2 bit of the timer 1/timer 2 clock selection register (prm02) = 0b (f clk = f xx /4). remark n = 0, 1 f clk : base clock (4) timer 2 sub-channel input event edge selection register 0 (sese0) the sese0 register specifies the valid edge of the external capture signal input (tinen) for the sub-channel n capture/compare register performing capture (n = 0 to 5). this register can be read/written in 16-bit units. when the higher 8 bits of the sese0 register are used as the sese0h register, and the lower 8 bits are used as the sese0l register, they can be read/ written in 8-bit or 1-bit units. 14 0 13 0 12 0 2 iese10 3 iese11 4 iese20 5 iese21 6 iese30 7 iese31 8 iese40 9 iese41 10 iese50 11 iese51 15 0 1 iese01 0 iese00 sese0 address fffff644h initial value 0000h bit position bit name function specifies the valid edge of external captur e signal input (tinen) for sub-channel n capture/compare register performing capture. iesen1 iesen0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 11 to 0 iesen1, iesen0 remark n = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) 332 user?s manual u14492ej4v1ud (5) timer 2 time base control register 0 (tcre0) the tcre0 register controls the op eration of tm2n (n = 0, 1). this register can be read/written in 16-bit units. when the higher 8 bits of the tcre0 re gister are used as the tcre0h regi ster, and the lower 8 bits are used as the tcre0l register, they can be read/written in 8-bit or 1-bit units. cautions 1. if ecren = 1 and eceen = 1 have been set, it is not possible to input an external clear signal (tclr2) for tm2n. in this case, first set clren = 1, and then clear tm2n by software (n = 0, 1). 2. when clearing is performed using the ec lr signal, the tm2n counter is cleared with a delay of (1 internal count clock set with bits csen2 to csen0 of the cse0 register) + 2 base clocks. therefore, if ext ernal clock input is selected as the internal count clock, the counter is not cleared until the external clock (ti2) is input. 3. the ecren bit and the eceen bit cannot be set to 1. 4. if the eceen bit is set to 1 and the ecre n bit is set to 0, a down count operation cannot be performed. 5. when udsen1, udsen0 = 01 and osten = 1, the counter does not count up when the counter value is 0. therefore , when the counter value is 0, set osten = 0, and after the value of the counter ceases to be 0, set osten = 1. also, on the ap plication, change the value of osten from 0 to 1 using the su b-channels 0 and 5 in terrupt signals. 6. when the tm2n count value is cleared (0) by setting clren to 1, the clren = 1 setting must be held for at least one of the intern al count clocks set by the csen2 to csen0 bits of the cse0 register. example when timer 20 (tm20) is cleared (0) <1> select f clk /2 as tm20 internal count clock 14 0 13 0 12 0 2 0 3 4 5 6 7 8 9 10 11 15 0 1 0 0 0 cse0 <2> clear (0) the tm20 count value 6 1 5 0 4 0 0 1 2 3 0 7 0 tcre0l <3> set the conditions required for the tm20 count clock 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 cse0 <4> start the tm20 count operation 6 0 5 1 4 0 0 1 2 3 0 7 0 tcre0l chapter 9 timer/counter function (real-time pulse unit) 333 user?s manual u14492ej4v1ud (1/2) <14> clre1 <13> cee1 12 ecre1 2 oste0 3 ecee0 4 ecre0 <5> cee0 <6> clre0 7 0 8 udse10 9 udse11 10 oste1 11 ecee1 15 case1 1 udse01 0 udse00 tcre0 address fffff646h initial value 0000h bit position bit name function 15 case1 specifies 32-bit cascade operation mode for tm21 (tm21 counts upon overflow of tm20 (carry count)). 0: not connected in cascade note 1 1: 32-bit cascade operation mode notes 2, 3 notes 1. tm21 counts at ct signal input in the count enabled state. 2. tm21 counts at ctc and casc signal inputs in the count enabled state. 3. only the capture register mode can be used for the capture/compare register. cautions 1. when case1 = 1, set the tbye1 and tbye0 bits of the cmsex0 register to 11 (x = 12, 34, y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4). 2. when case1 = 0, tcounte1 is selected as the count of tm21. when case1 = 1, tcounte0 and the tm20 overflow signal are selected as the count of tm21. 14, 6 clren specifies software clear for tm2n. 0: tm2n operation continued 1: tm2n count value cleared (0) caution do not perform the software clear and hardware clear operations simultaneously. 13, 5 ceen specifies tm2n count operation enable/disable. 0: count operation stopped 1: count operation enabled 12, 4 ecren specifies tm2n external clear (t clr2) operation enable/disable via eclr signal input. 0: tm2n external clear (tclr2) operation not enabled 1: tm2n external clear (tclr2) operation enabled cautions 1. in the 32-bit cascade operation mode (case1 = 1), the tm2n external clear operation is not performed. 2. when the count value is cleared by inputting the eclr signal while ecren = 1, the ecren = 1 setting must be held for at least one of the internal count clocks set by the csen2 to csen0 bits of the cse0 register. 3. in the 32-bit cascade operation mode (case1 = 1), only tm21 is affected by the ecren bit setting. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 334 user?s manual u14492ej4v1ud (2/2) bit position bit name function 11, 3 eceen specifies tm2n count operation enable/disable through eclr signal input. 0: tm2n count operation not enabled 1: tm2n count operation enabled cautions 1. in the 32-bit cascade operation mode (case1 = 1), the tm2n count operation using eclr signal input is not performed. 2. when the eceen bit = 1, always set the cese1 and cese0 bits of the cse0 register to 10 (through input). 3. in the 32-bit cascade operation mode (case1 = 1), only tm21 is affected by the eceen bit setting. 10, 2 osten specifies stop mode. 0: tm2n count stopped when count value is 0. 1: tm2n count not stopped when count value is 0. caution when the tm2n count stop is cancelled when the oste1n bit = 1 (tm2n count is stopped when the count value is 0), tm2n counts up except when the udsen1, udsen0 bits = 10. the count direction when the udsen1 and udsen0 bits = 10 is determined by the value of eclr . specifies tm2n up/down count. udsen1 udsen0 count 0 0 perform only up count. clear tm2n with compare match signal. 0 1 count up after tm2n has become 0, and count down after a compare match occurs for sub-channels 0, 5 (triangular wave up/down count). 1 0 selects up/down count according to the eclr signal input. up count when eclr = 1 down count when eclr = 0 1 1 setting prohibited 9, 8, 1, 0 udsen1, udsen0 cautions 1. in the 32-bit cascade operation mode (case1 bit = 1), set the udsen1 and udsen0 bits to 00. 2. when the udsen1 and udsen0 bits = 10, be sure to set the cese1 and cese0 bits of the cse0 register to 10 (through input). 3. when the udsen1 and udsen0 bits = 10, compare match between tm2n and cvsex0 has no effect on the tm2n count operation (x: 0 when n = 0, 5 when n = 1). remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 335 user?s manual u14492ej4v1ud (6) timer 2 output control register 0 (octle0) the octle0 register controls timer out put from the to2n pin (n = 1 to 4). this register can be read/written in 16-bit units. when the higher 8 bits of the octle0 register are us ed as the octle0h register, and the lower 8 bits are used as the octle0l register, they can be read/written in 8-bit or 1-bit units. 14 alve 4 13 otme 41 12 otme 40 2 alve 1 3 swfe 1 4 otme 20 5 otme 21 6 alve 2 7 swfe 2 8 otme 30 9 otme 31 10 alve 3 11 swfe 3 15 swfe 4 1 otme 11 0 otme 10 octle0 address fffff648h initial value 0000h bit position bit name function 15, 11, 7, 3 swfen fixes the to2n pin output le vel according to the setting of alven bit. 0: don?t fix output level. 1: when alven = 0, fix output level to low level. when alven = 1, fix output level to high level. 14, 10, 6, 2 alven specifies the active level of the to2n pin output. 0: active level is high level 1: active level is low level specifies toggle mode. otmen1 otmen0 toggle mode 0 0 toggle mode 0: reverse output level of to2n output every time a sub- channel n compare match occurs. 0 1 toggle mode 1: upon sub-channel n compare match, set to2n output to active level, and when tm20 is ?0?, set to2n output to inactive level. 1 0 toggle mode 2: upon sub-channel n compare match, set to2n output to active level, and when tm21 is ?0?, set to2n output to inactive level. 1 1 toggle mode 3: upon sub-channel n compare match, set to2n output to active level, and upon sub-channel n + 1 compare match, set to2n output to inactive level (when n = ?4?, n + 1 becomes ?1?). 13, 12, 9, 8, 5, 4, 1, 0 otmen1, otmen0 cautions 1. when the otmen1, otmen0 bits = 11 (toggle mode 3), if the same output delay operation settings are made when setting bits odlen2 to odlen0 of the odele0 register, two outputs change simultaneously upon 1 sub-channel n compare match. 2. if two or more signals are input simultaneously to the same output circuit, s/t signal input has a higher priority than ra, rb, and rn signal inputs. remark n = 1 to 4 chapter 9 timer/counter function (real-time pulse unit) 336 user?s manual u14492ej4v1ud (7) timer 2 sub-channel 0, 5 capture/c ompare control regi ster (cmse050) the cmse050 register controls timer 2 sub-channel 0 capture/compare register (cvse00) and timer 2 sub- channel 5 capture/compar e register (cvse50). this register can be read/written in 16-bit units. 14 0 13 eeve5 12 0 2 ccse0 3 lnke0 4 0 5 eeve0 6 0 7 0 8 0 9 0 10 ccse5 11 lnke5 15 0 1 0 0 0 cmse050 address fffff64ah initial value 0000h bit position bit name function 13, 5 eeven enables/disables event detection by sub-channel n capture/compare register. 0: ed1 and ed2 signal inputs ignored (not hing is done even if these signals are input). 1: operation caused by ed1 and ed2 signal inputs enabled. 11, 3 lnken specifies capture event signal i nput from edge selection to ed1 or ed2. 0: in capture register mode, select ed1 signal input. in compare register mode, lnken bit has no influence. 1: in capture register mode, select ed2 signal input. in compare register mode, lnken bit has no influence. 10, 2 ccsen selects capture/compare register operation mode. 0: operate in capture register mode . the tm20 and tm21 count statuses can be read with sub-channel 0 and s ub-channel 5, respectively. 1: operate in compare register mode. tm2m is cleared upon detection of match between sub-channel n and tm2m. remark m = 0, 1 n = 0, 5 chapter 9 timer/counter function (real-time pulse unit) 337 user?s manual u14492ej4v1ud (8) timer 2 sub-channel 1, 2 capture/c ompare control regi ster (cmse120) the cmse120 register controls the timer 2 sub-chan nel n sub capture/compare register (cvsen0) and the timer 2 sub-channel n main capture/com pare register (cvpen0) (n = 1, 2). this register can be read/written in 16-bit units. (1/2) 14 0 13 eeve2 12 bfee2 2 ccse1 3 lnke1 4 bfee1 5 eeve1 6 0 7 0 8 tb0e2 9 tb1e2 10 ccse2 11 lnke2 15 0 1 tb1e1 0 tb0e1 cmse120 address fffff64ch initial value 0000h bit position bit name function 13, 5 eeven enables/disables event detection for cmse120 register. 0: ed1 and ed2 signal inputs ignored (not hing is done even if these signals are input). 1: operation caused by ed1 and ed2 signal inputs enabled. 12, 4 bfeen specifies the buffer operation of sub-channel n sub capture/compare register (cvsen0). 0: don?t use sub-channel n sub capture/compare register (cvsen0) as buffer. 1: use sub-channel n sub capture/com pare register (cvsen0) as buffer. caution when the bfeen bit = 1, a compare match occurs on starting the timer in the compare register mode because the values of both the tm2x and cvpen0 registers are 0 after reset (tm2x = timer/counter selected by tb1en and tb0en bits, n = 1 to 4). after that, the value of the sub register (cvsen0) is writ ten to the main register (cvpen0). remarks 1. the operations in the capture register mode and compare register mode when the sub-channel n sub capt ure/compare register (cvsen0) is not used as a buffer are shown below. ? in capture register mode: the cpu can read both the master register (cvpen0) and slave register (cvsen0) . the next event is ignored until the cpu finishes reading the master register. tm20 capture is performed by th e slave register, and tm21 capture is performed by the master register. ? in compare register mode: the cp u writes to the slave register (cvsen0), and immediately after, the same contents as those of the slave register are written to the master register (cvpen0). 2. the operations in the capture register mode and compare register mode when the sub-channel n sub capt ure/compare register (cvsen0) is used as a buffer are shown below. ? in capture register mode: when t he cpu reads the master register (cvpen0), the master register updates the value held by the slave register (cvsen0) immediately before the cpu read operation. when a capture event occurs, the timer/counter value at that time is always saved in the slave register. ? in compare register mode: the cp u writes to the slave register (cvsen0) and these contents are tran sferred to the master register (cvpen0) set with the lnken bits. remark n = 1, 2 chapter 9 timer/counter function (real-time pulse unit) 338 user?s manual u14492ej4v1ud (2/2) bit position bit name function 11, 3 lnken selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: select ed1 signal input in capture register mode. in the compare register mode, the data of the cvsen0 register is transferred to the cvpen0 register upon occurrence of tm2x compare match (tm2x = timer/ counter selected with bits tb1en, tb0en). 1: select ed2 signal input in capture register mode. in the compare register mode, the data of the cvsen0 register is transferred to the cvpen0 register when the tm2x count value becomes ?0? (tm2x = timer/ counter selected with bits tb1en, tb0en). 10, 2 ccsen selects capture/compare register operation mode. 0: capture register mode 1: compare register mode sets sub-channel n timer/counter. tb1en tb0en sub-channel n timer/counter 0 0 don?t use sub-channel n. 0 1 set tm20 to sub-channel n. 1 0 set tm21 to sub-channel n. 1 1 32-bit mode note (select both tm20 and tm21.) 9, 8, 1, 0 tb1en, tb0en note in the 32-bit mode, influence of the bfeen bit is ignored. also, the cvsen0 register cannot be used as a buffer in this mode. caution when the tb1en, tb0en bits are set to ?11?, set the case1 bit of the tcre0 register to ?1?. remark n = 1, 2 chapter 9 timer/counter function (real-time pulse unit) 339 user?s manual u14492ej4v1ud (9) timer 2 sub-channel 3, 4 capture/c ompare control regi ster (cmse340) the cmse340 register controls the timer 2 sub-chan nel n sub capture/compare register (cvsen0) and the timer 2 sub-channel n main capture/com pare register (cvpen0) (n = 3, 4). this register can be read/written in 16-bit units. (1/2) 14 0 13 eeve4 12 bfee4 2 ccse3 3 lnke3 4 bfee3 5 eeve3 6 0 7 0 8 tb0e4 9 tb1e4 10 ccse4 11 lnke4 15 0 1 tb1e3 0 tb0e3 cmse340 address fffff64eh initial value 0000h bit position bit name function 13, 5 eeven enables/disables event detection by cmse340 register. 0: ed1 and ed2 signal inputs ignored (not hing is done even if these signals are input). 1: operation caused by ed1 and ed2 signal inputs enabled. 12, 4 bfeen specifies the sub-channel n sub capture/compare register (cvsen0) buffer operation. 0: don?t use sub-channel n sub capture/compare register (cvsen0) as buffer. 1: use sub-channel n sub capture/co mpare register (cvsen0) as buffer. caution when the bfeen bit = 1, a compare match occurs on starting the timer in the compare register mode because the values of both the tm2x and cvpen0 registers are 0 after reset (tm2x = timer/counter selected by tb1en and tb0en bits, n = 1 to 4). after that, the value of the sub register (cvsen0) is writ ten to the main register (cvpen0). remarks 1. the operations in the capture register mode and compare register mode when the sub-channel n sub capt ure/compare register (cvsen0) is not used as a buffer are shown below. ? in capture register mode: the cpu can read both the master register (cvpen0) and slave register (cvsen0) . the next event is ignored until the cpu finishes reading the master register. tm20 capture is performed by th e slave register, and tm21 capture is performed by the master register. ? in compare register mode: the cp u writes to the slave register (cvsen0), and immediately after, the same contents as those of the slave register are written to the master register (cvpen0). 2. the operations in the capture register mode and compare register mode when the sub-channel n sub capt ure/compare register (cvsen0) is used as a buffer are shown below. ? in capture register mode: when t he cpu reads the master register (cvpen0), the master register updates the value held by the slave register (cvsen0) immediately before the cpu read operation. when a capture event occurs, the timer/counter value at that time is always saved in the slave register. ? in compare register mode: the cp u writes to the slave register (cvsen0) and these contents are tran sferred to the master register (cvpen0) set with the lnken bits. remark n = 3, 4 chapter 9 timer/counter function (real-time pulse unit) 340 user?s manual u14492ej4v1ud (2/2) bit position bit name function 11, 3 lnken selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: select ed1 signal input in capture register mode. in the compare register mode, the data of the cvsen0 register is transferred to the cvpen0 register upon occurrence of tm2x compare match (tm2x = timer/ counter selected with bits tb1en, tb0en). 1: select ed2 signal input in capture register mode. in the compare register mode, the data of the cvsen0 register is transferred to the cvpen0 register when the tm2x count value becomes ?0? (tm2x = timer/ counter selected with bits tb1en, tb0en). 10, 2 ccsen selects capture/compare register operation mode. 0: capture register mode 1: compare register mode sets sub-channel n timer/counter. tb1en tb0en sub-channel n timer/counter 0 0 don?t use sub-channel n. 0 1 set tm20 to sub-channel n. 1 0 set tm21 to sub-channel n. 1 1 32-bit mode note (select both tm20 and tm21.) 9, 8, 1, 0 tb1en, tb0en note in the 32-bit mode, influence of the bfeen bit is ignored. also, the cvsen0 register cannot be used as a buffer in this mode. caution when the tb1en, tb0en bits are set to ?11?, set the case1 bit of the tcre0 register to ?1?. remark n = 3, 4 chapter 9 timer/counter function (real-time pulse unit) 341 user?s manual u14492ej4v1ud (10) timer 2 time base status register 0 (tbstate0) the tbstate0 register indicates t he status of tm2n (n = 0, 1). this register can be read/written in 16-bit units. when the higher 8 bits of the tbstat e0 register are used as the tbstat e0h register, and the lower 8 bits are used as the tbstate0l r egister, they can be read/written in 8-bit or 1-bit units. caution the ecfen, rsfen, and udfen bits are read-only bits. 14 0 13 0 12 0 <2> ecfe0 <3> ovfe0 4 0 5 0 6 0 7 0 <8> udfe1 <9> rsfe1 <10> ecfe1 <11> ovfe1 15 0 <1> rsfe0 <0> udfe0 tbstate0 address fffff664h initial value 0101h bit position bit name function 11, 3 ovfen indicates tm2n overflow status. 0: no overflow 1: overflow caution if write access to the tbstate0 register is performed while overflow is not detected, the ovfen bit is cleared (0). 10, 2 ecfen indicates the eclr signal input status. 0: low level 1: high level 9, 1 rsfen indicates the tm2n count status. 0: tm2n is not counting. 1: tm2n is counting (either up or down) 8, 0 udfen indicates the tm2n up/down count status. 0: tm2n is in the down-count mode. 1: tm2n is in the up-count mode. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 342 user?s manual u14492ej4v1ud (11) timer 2 capture/compare 1 to 4 status register 0 (ccstate0) the ccstate0 register indicates the status of the timer 2 sub-channel sub capture/compare register (cvsen0) and the timer 2 sub-channel main captur e/compare register (cvpen0) (n = 1 to 4). this register can be read/written in 16-bit units. when the higher 8 bits of the ccstate0 register are used as the ccstate0h register, and the lower 8 bits are used as the ccstate0l register, they c an be read/written in 8-bit or 1-bit units. caution the bffen1 and bffen0 bits are read-only bits. <14> cefe4 13 bffe41 12 bffe40 <2> cefe1 3 0 4 bffe20 5 bffe21 <6> cefe2 7 0 8 bffe30 9 bffe31 <10> cefe3 11 0 15 0 1 bffe11 0 bffe10 ccstate0 address fffff666h initial value 0000h bit position bit name function 14, 10, 6, 2 cefen indicates the capt ure/compare event occurrence status. 0: in capture register mode: no capture operation has occurred. in compare register mode: no compare match has occurred. 1: in capture register mode: at least one capture operation has occurred. in compare register mode: at least one compare match has occurred. caution the cefen bit can be cleared (0) by performing write access to the ccstate0 register while no capture operation or compare match occurs. when bit manipulation is performed for the cefe1 (cefe3) bit and the cefe2 (cefe4) bit, both bits are cleared. indicates the capture buffer status. bffen1 bffen0 capture buffer status 0 0 no value in buffer 0 1 sub-channel n master register (cvpen0) contains a capture value. slave regi ster (cvsen0) does not contain a value. 1 0 both sub-channel n master register (cvpen0) and slave register (cvsen0) contain a capture value. 1 1 unused 13, 12, 9, 8, 5, 4, 1, 0 bffen1, bffen0 caution the bffen1 and bffen0 bits return a value only when sub-channel n sub capture/compare register (cvsen0) buffer operation (bit bfeen of cmsem0 register = 1) is selected or when capture register mode (bit ccsen of cmsem0 register = 0) is selected. ?0? is read when the compare register mode (ccsen bit = 1) is selected. remark m = 12, 34 n = 1 to 4 chapter 9 timer/counter function (real-time pulse unit) 343 user?s manual u14492ej4v1ud (12) timer 2 output delay register 0 (odele0) the odele0 register sets the output delay operation synchronized with the clock to the to2n pin?s output delay circuit (n = 1 to 4). this register can be read/written in 16-bit units. when the higher 8 bits of the odele0 register are used as the odele0h register, and the lower 8 bits are used as the odele0l register, they can be read/written in 8-bit or 1-bit units. 14 odle42 13 odle41 12 odle40 2 odle12 3 0 4 odle20 5 odle21 6 odle22 7 0 8 odle30 9 odle31 10 odle32 11 0 15 0 1 odle11 0 odle10 odele0 address fffff668h initial value 0000h bit position bit name function specifies output delay operation. odlen2 odlen1 odlen0 set output delay operation 0 0 0 don?t perform output delay operation. 0 0 1 set output delay of 1 system clock. 0 1 0 set output delay of 2 system clocks. 0 1 1 set output delay of 3 system clocks. 1 0 0 set output delay of 4 system clocks. 1 0 1 set output delay of 5 system clocks. 1 1 0 set output delay of 6 system clocks. 1 1 1 set output delay of 7 system clocks. 14 to 12, 10 to 8, 6 to 4, 2 to 0 odlen2, odlen1, odlen0 remark the odlen2, odlen1, and odlen0 bits are used for emi countermeasures. remark n = 1 to 4 chapter 9 timer/counter function (real-time pulse unit) 344 user?s manual u14492ej4v1ud (13) timer 2 software event capture register (csce0) the csce0 register sets capture operation by software in the capture register mode. this register can be read/written in 16-bit units. 14 0 13 0 12 0 2 seve2 3 seve3 4 seve4 5 seve5 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1 seve1 0 seve0 csce0 address fffff66ah initial value 0000h bit position bit name function 5 to 0 seven specifies capture operation by software in capture register mode. 0: continue normal operation. 1: perform capture operation. cautions 1. the seven bit ignores the settings of the eeven and the lnken bits of the cmsem0 register. 2. the seven bit is automatically cleared (0) at the end of an event. 3. the seven bit ignores all the internal limitation statuses of the timer 2 unit. remark m = 12, 34, 05 n = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) 345 user?s manual u14492ej4v1ud 9.3.5 operation (1) edge detection the edge detection timing is shown below. figure 9-63. edge detection timing f clk 00b 01b 10b 11b muxtb0 ct ed1, ed2 eclr note tinex, tclr2, tcounten note set values of tesne1, tesne0 bits and cese1, cese0 bits of cse0 register, and iesex1, iesex0 bits of sese0 register. remarks 1. f clk : base clock 2. ct: tm2n count signal input in the 16-bit mode eclr: external control signal input from tclr2 input ed1, ed2: capture event signal input from edge selector muxtb0: tm20 multiplex signal tcounten: timer 2 count enable signal input tinex: timer 2 sub-channel x capture event signal input 3. n = 0, 1 x = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) 346 user?s manual u14492ej4v1ud (2) basic operation of timer 2 figures 9-64 to 9-67 show the basic operation of timer 2. figure 9-64. timer 2 up-count timing (when tcre0 register?s udsen1, udsen0 bits = 00b, eceen bit = 0, ecren bit = 0, clren bit = 0, case1 bit = 0) f clk fffdh (stop) fffeh ffffh 0000h 1234h 1235h 0000h (stop) ct cnt r note 2 inttm2n (output) cnt = 0 osten bit note 1 ceen bit note 1 notes 1. bits oste, cee of tcre0 register 2. can control tm20/tm21 clear by sub-channel 0/5 compare match or count direction. remarks 1. f clk : base clock 2. cnt: count value of timer 2 ct: tm2n count signal input in 16-bit mode r: compare match signal input (sub-channel 0/5) 3. n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 347 user?s manual u14492ej4v1ud figure 9-65. external control timing of timer 2 (when tcre0 register?s udsen1, udsen0 bits = 00b, osten bit = 0, ceen bit = 1, case1 bit = 0) f clk ecren bit note clren bit note eclr cnt ct eceen bit note 1234h 1235h 0000h 0001h 0000h note bits eceen, ecren, clren of tcre0 register remarks 1. f clk : base clock 2. cnt: count value of timer 2 ct: tm2n count signal input in 16-bit mode eclr: external control signal input from tclr2 pin input 3. n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 348 user?s manual u14492ej4v1ud figure 9-66. operation in ti mer 2 up-/down-count mode (when tcre0 register?s eceen bit = 0, ecren bit = 0, clren bit = 0, osten bit = 0, ceen bit = 1, case1 bit = 0) f clk eclr r note 2 cnt inttm2n (output) cnt = 0 ct udsen1, udsen0 bits note 1 ffffh 0000h 0001h don't care 01b 10b 0002h 0001h 0000h 0001h 0002h 0003h 0002h fffeh notes 1. udsen1, udsen0 bits of tcre0 register 2. can control tm20/tm21 clear by sub-channel 0/5 compare match or count direction. remarks 1. f clk : base clock 2. cnt: count value of timer 2 ct: tm2n count signal input in 16-bit mode eclr: external control signal input from tclr2 pin input r: compare match signal input (sub-channel 0/5) 3. n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 349 user?s manual u14492ej4v1ud figure 9-67. timing in 32-bi t cascade operation mode (when tcre0 register?s udsen1, udsen0 bits = 00b, eceen bit = 0, ecren bit = 0, clren bit = 0, osten bit = 0, ceen bit = 1, case1 bit = 1) f clk cnt[tb0] cnt[tb1] ctc casc note [tb1] fffbh fffch fffdh fffeh ffffh 0000h 0001h 0002h 0003h 0004h 1234h 1235h note if, in the 32-bit mode, casc (cnt = max. for tm 20) is input to tm21 and the ctc rising edge is detected, tm21 performs count operation. remarks 1. f clk : base clock 2. casc: tm21 count signal input in 32-bit mode cnt: count value of timer 2 ctc: tm21 count signal input in 32-bit mode tb0: count value of tm20 tb1: count value of tm21 3. n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 350 user?s manual u14492ej4v1ud (3) operation of capture/compare re gister (sub-channels 1 to 4) sub-channels 1 to 4 receive the count value of the timer 2 multiplex count generator. the multiplex count generator is an internal unit of tm 2n that supplies the multiplex count value muxcnt to sub-channels 1 to 4. the count value of tm20 is output to sub-channels 1 to 4 at the rising edge of muxtb0, and the count value of tm21 is output to sub-c hannels 1 to 4 at the rising edge of muxtb1. figure 9-68 shows the block diagram of the timer 2 multiplex count generator, and figure 9-69 shows the multiplex count timing. figure 9-68. block diagram of ti mer 2 multiplex count generator muxtb0 (to sub-channel m capture/compare register) muxtb1 (to sub-channel m capture/compare register) muxcnt (to sub-channel m capture/compare register) f clk cnt (from tm20) cnt (from tm21) multiplex control timer 2 multiplex count generator remarks 1. f clk : base clock 2. cnt: count value of timer 2 muxtb0, muxtb1: multiplex signal of tm20, tm21 muxcnt: count value to sub-channel m 3. m = 1 to 4 chapter 9 timer/counter function (real-time pulse unit) 351 user?s manual u14492ej4v1ud figure 9-69. multiplex count timing f clk muxtb0 muxtb1 muxcnt cnt (0) cnt (1) fffeh ffffh 0000h 1235h 1234h tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 0001h fffeh 1234h ffffh ffffh ffffh 1234h 1234h 0000h 1234h 1235h 0000h 1235h 0000h 0001h 0001h 0001h 1235h 1235h 1235h remarks 1. f clk : base clock 2. cnt: count value of timer 2 muxtb0, muxtb1: multiplex signal of tm20, tm21 muxcnt: count value to sub-channel m (m = 1 to 4) tb0: count value of tm20 tb1: count value of tm21 figures 9-70 to 9-75 show the operation of the c apture/compare register (sub-channels 1 to 4). chapter 9 timer/counter function (real-time pulse unit) 352 user?s manual u14492ej4v1ud figure 9-70. capture operati on: 16-bit buffer-less mode (when operation is delayed throu gh setting of lnkey bit of cmsex0 register, and cmsex0 register?s ccsey bit = 0, bfeey bit = 0, eevey bit = 1, and csce0 register?s sevey bit = 0) cvpem0 register f clk muxtb0 muxtb1 ed1 ed2 capture_p capture_s read_enable_p cvsem0 register muxcnt tb0ey bit note 1 tb1ey bit note 1 lnkey bit note 1 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 1 5 62 3 4 78 5 9 10 6 11 7 8 9 10 12 13 14 note 2 note 2 undefined undefined 24 13 11 notes 1. bits tb0ey, tb1ey of cmsex register 2. if an event occurs in this timing, it is ignored. remarks 1. f clk : base clock 2. capture_p: capture trigger signal of main capture register capture_s: capture trigger si gnal of sub capture register ed1, ed2: capture event signal input from edge selector muxcnt: count value to sub-channel m muxtb0, muxtb1: multiplex signal of tm20, tm21 read_enable_p: read timing for cvpem0 register tb0: count value of tm20 tb1: count value of tm21 3. m = 1 to 4, x = 12, 34 y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4 chapter 9 timer/counter function (real-time pulse unit) 353 user?s manual u14492ej4v1ud figure 9-71. capture operati on: mode with 16-bit buffer note 1 (when cmsex0 register?s tbye1 bit = 0, tbye0 bit = 1, ccsey bit = 0, lnkey bit = 0, bfeey bit = 1, eevey bit = 1, and csce0 register?s sevey bit = 0) f clk muxtb0 muxtb1 buffer read_enable_p cvpem0 register cvsem0 register muxcnt ed1 capture_p capture_s tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 1 5 62 3 4 78 5 9 10 6 11 7 8 9 10 12 13 new event 14 note 2 note 3 undefined undefined 2 4 capture 23 4 8 shift l event notes 1. to operate tm2n in the mode with 16-bit buffer, perfo rm capture at least twice at the start of operation and read the cvpem0 register. also, read the cvpem 0 register after performing capture at least once. 2. write operation to the cvpen0 register is not per formed at these signal inputs because the cvsem0 register operates as a buffer. 3. after this timing, write operation from the cvsem 0 register to the cvpem0 register is enabled. remarks 1. f clk : base clock 2. buffer: timing of write operation from cvsem0 register to cvpem0 register capture_p: capture trigger signal of main capture register capture_s: capture trigger si gnal of sub capture register ed1: capture event signal input from edge selector muxcnt: count value to sub-channel m muxtb0, muxtb1: multiplex signal of tm20, tm21 read_enable_p: read timing of cvpem0 register tb0: count value of tm20; tb1: count value of tm21 3. m = 1 to 4, x = 12, 34 y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4 chapter 9 timer/counter function (real-time pulse unit) 354 user?s manual u14492ej4v1ud figure 9-72. capture operation: 32-bit cascade operation mode (when cmsex register?s tbye1 bit = 1, tbye0 bit = 1, ccsey bit = 0, lnkey bit = 0, bfeey bit = arbitr ary, eevey bit = 1, and csce0 register?s sevey bit = 0) f clk casc note 1 muxtb0 muxtb1 muxcnt ed1 capture_s capture_p read_enable_p cvsem0 register cvpem0 register tcounte0 = tcounte1 cnt (0) cnt (1) fffeh ffffh 0000h 1235h 1234h tb0 tb1 tb0 tb1 tb0 undefined undefined 0000h 1235h 0001h 1235h tb1 tb0 tb1 tb0 tb1 tb0 tb1 note 2 note 3 tb0 tb1 enable the next capture tb0 tb1 tb0 tb1 tb0 tb1 0001h fffeh 1234h ffffh ffffh ffffh 1234h 1234h 0000h 1234h 1235h 0000h 1235h 0000h 0001h 0001h 0001h 1235h 1235h 1235h note 2 note 3 notes 1. tm21 performs count operation when, in the 32-bit m ode, casc (cnt = max. for tm20) is input to tm21 and the rising edge of ctc is detected. 2. if an event occurs during this timing, it is ignored. 3. cpu read access is not performed in this timing (wait status). remarks 1. f clk : base clock 2. capture_p: capture trigger signal of main capture register capture_s: capture trigger si gnal of sub capture register casc: tm21 count signal in 32-bit mode cnt: count value of timer 2 ed1: capture event signal input from edge selector muxcnt: count value to sub-channel m muxtb0, muxtb1: multiplex signal of tm20, tm21 read_enable_p: read timing of cvpem0 register tb0: count value of tm20 tb1: count value of tm21 tcounte0, tcounte1: count enable signal input of timer 2 3. m = 1 to 4, x = 12, 34 y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4 chapter 9 timer/counter function (real-time pulse unit) 355 user?s manual u14492ej4v1ud figure 9-73. capture operation: capture c ontrol by software and trigger timing (when cmsex0 register?s tbye1 bit = 0, tb ye0 bit = 1, ccsey bit = 0, lnkey bit = 0, bfeey bit = 1) f clk eevey bit note 1 sevey bit note 2 muxtb0 muxtb1 muxcnt ed1 capture_p capture_s buffer cvsem0 register cvpem0 register undefined undefined 4 4 9 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 51 62 3 4 78 5 9 10 6 11 7 8 9 10 12 13 14 cleared by timer set by software event detection by eevey bit prohibited l notes 1. eevey bit of cmsex0 register 2. sevey bit of csce0 register remarks 1. f clk : base clock 2. buffer: timing of write operation from cvsem0 register to cvpem0 register capture_p: capture trigger si gnal of main capture register capture_s: capture trigger si gnal of sub capture register ed1: capture event sig nal input from edge selector muxcnt: count value to sub-channel m muxtb0, muxtb1: multiplex signal of tm20, tm21 tb0: count value of tm20 tb1: count value of tm21 3. m = 1 to 4, x = 12, 34 y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4 chapter 9 timer/counter function (real-time pulse unit) 356 user?s manual u14492ej4v1ud figure 9-74. compare operat ion: buffer-less mode (when cmsex0 register?s ccsey bi t = 1, lnkey bit = arbitrary, bfeey bit = 0) f clk tb0ey bit note 1 tb1ey bit note 1 muxtb0 muxtb1 muxcnt write_enable_s reload_primary cvsem0 register cvpem0 register reload1 intccm tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb0 tb1 tb0 tb1 tb1 tb0 tb1 tb0 tb1 tb0 tb1 51 62 3 7 78 9 10 9 11 8 9 10 67 8 2 2 9 9 8 8 note 3 note 3 note 3 note 3 note 2 notes 1. tb1ey, tb0ey bits of cmsex0 register 2. no interrupt is generated due to compare matc h with counter differing from tb1ey, tb0ey bit settings. 3. intcc2m is generated to match the cycle from rising edge to falling edge of muxtb0. remarks 1. f clk : base clock 2. muxcnt: count value to sub-channel m muxtb0, muxtb1: multiplex signal of tm20, tm21 reload1: compare match signal reload_primary: timing of write operation fr om cvsem0 register to cvpem0 register write_enable_s: timing of c vsem0 register write operation tb0: count value of tm20 tb1: count value of tm21 3. m = 1 to 4, x = 12, 34 chapter 9 timer/counter function (real-time pulse unit) 357 user?s manual u14492ej4v1ud figure 9-75. compare operation: mode with buffer (when operation is delayed throu gh setting of lnkey bit of cmsex0 register, cmsex0 register?s ccsey bit = 1, bfeey bit = 1) f clk lnkey bit note write_enable_s muxtb0 muxtb1 muxcnt reload2a reload1 reload_primary cvsem0 register cvpem0 register intcc2m (output) tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 51 62 3 4 78 5 9106117012 12 13 14 4 471 71 note lnkey bit of cmsex0 register remarks 1. f clk : base clock 2. muxcnt: count value to sub-channel m muxtb0, muxtb1: multiplex signal of tm20, tm21 reload1: compare match signal reload2a: zero count signal input of tm20 (occurs when tm20 = 0000h) reload_primary: timing of write operation from cvsem0 register to cvpem0 register write_enable_s: timing of cvsem0 register write operation tb0: count value of tm20 (in this figure, the maximum count value is 7.) tb1: count value of tm21 3. m = 1 to 4, x = 12, 34 y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4 chapter 9 timer/counter function (real-time pulse unit) 358 user?s manual u14492ej4v1ud (4) operation of capture/compare register (sub-channels 0, 5) figures 9-76 and 9-77 show the operation of the capture/compare register (sub-channels 0, 5). figure 9-76. capture operation: timer 2 count value read timing (when cmse050 register?s ccsey bit = 0, eevey bit = 1, and csce0 register?s sevey bit = 0) f clk ed1 ed2 capture_s read_enable_s cvsey0 register cnt lnkey note 1 123456 78910 0 note 2 note 2 undefined 2 6 9 notes 1. lnkey bit of cmse050 register 2. if an event occurs in this timing, it is ignored. remarks 1. f clk : base clock 2. cnt: count value of timer 2 capture_s: capture trigger si gnal of sub capture register ed1, ed2: capture event signal inputs from edge selector read_enable_s: read timing for cvsey0 register 3. y = 0, 5 chapter 9 timer/counter function (real-time pulse unit) 359 user?s manual u14492ej4v1ud figure 9-77. compare operation: timing of co mpare match and write operation to register (when cmse050 register?s ccsey bit = 1, eevey bit = arbitrary, and csce0 register?s sevey bit = arbitrary) f clk cvsey0 register match r note 1 intcc20, intcc25 (output) cnt cpu write c/c 12 2 34 4 56 78 8 910 0 note 2 note 3 note 2 note 2 note 3 note 3 notes 1. can control tm20/tm21 clear by sub-channel 0/5 compare match or count direction. 2. when match signal occurs, the same wave form as the match signal is generated. 3. the pulse width is always 1 clock. remarks 1. f clk : base clock 2. cnt: count value of timer 2 match: cvsey0 regist er compare match timing r: compare match input (sub-channel 0/5) chapter 9 timer/counter function (real-time pulse unit) 360 user?s manual u14492ej4v1ud (5) operation of output circuit figures 9-78 to 9-81 show the output circuit operation. figure 9-78. signal output operation: toggle mode 0 and toggle mode 1 (when octle0 register?s swfen bit = 0, and odele0 register?s odlen2 to odlen0 bits = 0) f clk ra rb rn to2n timer output (alven bit = 0 note 2 ) to2n timer output (alven bit = 1 note 2 ) otmen1, otmen0 bits note 1 s/t 00b 01b notes 1. otmen1, otmen0 bits of octle0 register 2. alven bit of octle0 register remarks 1. f clk : base clock 2. ra: zero count signal input of tm20 (output circuit reset signal) rb: zero count signal input of tm21 (output circuit reset signal) rn: interrupt signal input of sub-channel n (output circuit reset signal) s/t: interrupt signal input of sub- channel n (output circuit set signal) 3. n = 1 to 4 chapter 9 timer/counter function (real-time pulse unit) 361 user?s manual u14492ej4v1ud figure 9-79. signal output operation: toggle mode 2 and toggle mode 3 (when octle0 register?s swfen bit = 0, and odele0 register?s odlen2 to odlen0 bits = 0) f clk ra rb rn to2n timer output (alven bit = 0 note 2 ) to2n timer output (alven bit = 1 note 2 ) otmen1, otmen0 bits note 1 s/t 10b 11b notes 1. otmen1, otmen0 bits of octle0 register 2. alven bit of octle0 register remarks 1. f clk : base clock 2. ra: zero count signal input of tm20 (output circuit reset signal) rb: zero count signal input of tm21 (output circuit reset signal) rn: interrupt signal input of sub-channel n (output circuit reset signal) s/t: interrupt signal input of sub- channel n (output circuit set signal) 3. n = 1 to 4 figure 9-80. signal output operation: during software control (when octle0 register?s otmen1, ot men0 bits = arbitrary, swfen bit = 1, and odele0 register?s od len2 to odlen0 bits = 0) f clk alven bit note to2n timer output note alven bit of octle0 register remarks 1. f clk : base clock 2. n = 1 to 4 chapter 9 timer/counter function (real-time pulse unit) 362 user?s manual u14492ej4v1ud figure 9-81. signal output operation: during delay output operation (when octle0 register?s ot men1, otmen0 bits = 0, alven = 0, swfen bit = 0) f clk to2n timer output odelen2 to odelen0 bits note s/t 5 2 note odelen2 to odelen0 bits of octle0 register remarks 1. f clk : base clock 2. n = 1 to 4 chapter 9 timer/counter function (real-time pulse unit) 363 user?s manual u14492ej4v1ud 9.3.6 pwm output operation when timer 2 operates in compare mode (1) operation when to2n pin performs pwm output operation in toggle mode 1 in toggle mode 1, the to2n output (i nternal) becomes inactive triggered by a signal when tm20 = 0, and becomes active triggered by a sub- channel 1 (cvpen0 re gister) compare match sign al. in accordance with the state of this to2n (internal), the to2n pin outputs a high or lo w level depending on the octle0.alven bit setting. figure 9-82. normal output operation (when octle0 register?s otmen1, ot men0 bits = 01, odele0 register?s odlen2 to odlen0 bits = 000) f clk cvsen0 register match signal to2n (internal) to2n output (alven bit = 0) to2n output (alven bit = 1) tm20 cvse00 register cvsen0 register tm20 = 0 06 05 07 00 02 inactive state inactive state active state active state 04 01 03 06 0008h 0005h 05 07 00 01 02 04 06 00 01 03 05 07 remark n = 1 to 4 chapter 9 timer/counter function (real-time pulse unit) 364 user?s manual u14492ej4v1ud (2) operation when to2n pin output is controlled by manipulating octle0.swfen bit in toggle mode 1 (a) when a sub-channel n compare match signal is output immediately after the swfen bit is cleared to 0 figures 9-83 and 9-84 show the waveforms when output from the to2n output pin is started or ended by manipulating the swfen bit in toggle mode 1. in the v850e/ia1, timer 2 outputs a level according to the alven bit setting (low level when alven bit = 0, and high level when alven bit = 1) by fixing the to 2n output to the inactive state when the swfen bit is 1. when the swfen bit is 0, to2n (internal) sync hronizes with a trigger signal and an active or inactive level is output from the to2n output pin. however, to2n output is forcibly fixed to the acti ve state when the swfen bit is cleared to 0, and inactive state when the swfen bit is set to 1. therefore, if the sub-ch annel n compare match signal is output immediately after the swfen bit is cleared to 0, the active period from when the sw fen bit is cleared to 0 to when the compare match signal is output will be added to the ordinary to2n ou tput active period, so the first active period becomes long (refer to figure 9-83 ). figure 9-83. when output operat ion is started/ended normally (when octle0 register?s otmen1, ot men0 bits = 01, odeld0 register?s odlen2 to odlen0 bits = 000) f clk cvsen0 register match signal to2n (internal) to2n output (alven bit = 0) to2n output (alven bit = 1) tm20 cvse00 register cvsen0 register tm20 = 0 06 05 07 00 02 inactive state (fixed) inactive state active state inactive state inactive state (fixed) 04 01 03 06 0008h 0005h 05 07 00 01 02 04 06 03 05 07 swfen bit 00 01 02 04 03 05 active state remark n = 1 to 4 chapter 9 timer/counter function (real-time pulse unit) 365 user?s manual u14492ej4v1ud (b) when the trigger signal of tm20 = 0 is output immediately after the swfe n bit is cleared to 0 when the trigger signal of tm20 = 0 is output immediately after the swfen bit is cleared to 0, from when the swfen bit is cleared to 0 to when the trigger signal of tm20 = 0 is output is the first active period, so a pulse shorter than the active period of the ordinary to2n output is output. in addition, since to2n output is forcibly fixed to the inactive level when the swfen bit is set to 1, the active level output period also becomes shorter if the swfen bit is set to 1 while an active level is being output (refer to figure 9-84 ). figure 9-84. when output operat ion is started/ended normally (when octle0 register?s otmen1, ot men0 bits = 01, odeld0 register?s odlen2 to odlen0 bits = 000) f clk cvsen0 register match signal to2n (internal) to2n output (alven bit = 0) to2n output (alven bit = 1) tm20 cvse00 register cvsen0 register tm20 = 0 02 inactive state (fixed) inactive state active state active state inactive state inactive state (fixed) 04 03 06 0008h 0005h 05 07 00 01 02 04 06 03 05 07 swfen bit 00 01 02 04 03 05 06 07 00 active state remark n = 1 to 4 chapter 9 timer/counter function (real-time pulse unit) 366 user?s manual u14492ej4v1ud 9.4 timer 3 9.4.1 features (timer 3) timer 3 (tm3) is a 16-bit timer/counter that can perform the following operations. ? interval timer function ? pwm output ? external signal cycle measurement 9.4.2 function overview (timer 3) ? 16-bit timer/counter (tm3): 1 channel ? capture/compare registers: 2 ? count clock division selectable by prescaler (set the frequency of the count clock to 16 mhz or less) ? base clock (f clk ): 2 types (set f clk to 32 mhz or less) f xx and f xx /2 can be selected ? prescaler division ratio the following division ratios can be selected according to the base clock (f clk ). base clock (f clk ) division ratio f xx selected f xx /2 selected 1/2 f xx /2 f xx /4 1/4 f xx /4 f xx /8 1/8 f xx /8 f xx /16 1/16 f xx /16 f xx /32 1/32 f xx /32 f xx /64 1/64 f xx /64 f xx /128 1/128 f xx /128 f xx /256 1/256 f xx /256 f xx /512 ? interrupt request sources ? capture/compare match interrupt requests: 2 sources in case of capture register: intcc3n generated by intp3n input in case of compare register: intcc3n generated by cc3n match signal ? overflow interrupt request: 1 source inttm3 generated upon overflow of tm3 register ? timer/counter count clock sources: 2 types (selection of external pulse in put, internal system clock cycle) ? one of two operation modes when the timer/counter overflows can be selected: free-running mode or overflow stop mode ? the timer/counter can be cleared by matc h of timer/counter and compare register ? external pulse output (to3): 1 remarks 1. f xx : internal system clock 2. n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 367 user?s manual u14492ej4v1ud 9.4.3 basic configuration table 9-12. timer 3 configuration list count clock timer note 1 note 2 register read/write generated interrupt signal capture trigger timer output s/r tm3 read inttm3 ? ? cc30 read/write intcc30 intp30 to3 (s) timer 3 f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256 f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512 cc31 read/write intc31 intp31 to3 (r) notes 1. when f xx is selected as the base clock (f clk ) of tm3 2. when f xx /2 is selected as the base clock (f clk ) of tm3 remark f xx : internal system clock s/r: set/reset figure 9-85 shows the block diagram of timer 3. figure 9-85. block di agram of timer 3 r note q sq tm3 (16-bit) cc30 cc31 inttm3 intcc30 intp31 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 f xx /2 ti3/tclr3/intp30 intcc31 to3 f clk selector selector selector clear & start clear & start f xx note reset priority remarks 1. ti3 input and tclr3 input connected to port immediately before edge detection 2. f clk : base clock (32 mhz (max.)) f xx : internal system clock chapter 9 timer/counter function (real-time pulse unit) 368 user?s manual u14492ej4v1ud (1) timer 3 (tm3) tm3 functions as a 16-bit free-running timer or as an event counter for an external signal. besides being mainly used for cycle measurement, tm3 can be used as pulse output. tm3 is read-only, in 16-bit units. cautions 1. the tm3 register can only be read. if writing is performed to the tm3 register, the subsequent operation is undefined. 2. if the tm3cae bit of the tmc30 regist er is cleared (0), a reset is performed asynchronously. 3. continuous reading of tm3 is prohibited . if tm3 is continuously read, the second read value may differ from the actual value. figure 9-86. timer 3 (tm3) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tm3 fffff680h 0000h address initial value 0 tm3 performs the count-up operat ions of an internal count clock or exte rnal count clock. timer starting and stopping are controlled by the tm3ce bit of timer control register 30 (tmc30). the internal or external count clock is selected by the eti bit of timer control register 31 (tmc31). (a) selection of the external count clock tm3 operates as an event counter. when the eti bit of timer control register 31 (tmc31) is set (1), tm3 counts the valid edges of the external clock input (ti3), synchronized with the internal count clock. the valid edge is specified by valid edge selection r egister (sesc). caution if the intp30, ti3, an d tclr3 pins are used as the ti 3 and tclr3, either mask the intp30 interrupt or set cc3n in compare mode (n = 0, 1). chapter 9 timer/counter function (real-time pulse unit) 369 user?s manual u14492ej4v1ud (b) selection of the internal count clock tm3 operates as a free-running timer. when an internal clock is specified as a count clock by timer control register 31 (tmc31), tm3 is counted up for each input clock cycle specified by the cs2 to cs0 bits of the tmc30 register. a division by the prescaler can be selected for the count clock from among f clk /2, f clk /4, f clk /8, f clk /16, f clk /32, f clk /64, f clk /128 and f clk /256 by the tmc30 register (f clk : base clock). an overflow interrupt can be generat ed if the timer overflows. also, the timer can be stopped following an overflow by setting the ost bit of the tmc31 register to 1. caution the count clock cannot be ch anged while the timer is operating. the conditions when the tm3 regist er becomes 0000h are shown below. (i) asynchronous reset ? tm3cae bit of tmc30 register = 0 ? reset input (ii) synchronous reset ? tm3ce bit of tmc30 register = 0 ? the cc30 register is used as a compare regi ster, and the tm3 and cc30 registers match when clearing the tm3 register is enabled ( cclr bit of the tmc31 register = 1) chapter 9 timer/counter function (real-time pulse unit) 370 user?s manual u14492ej4v1ud (2) capture/compare registers 30 and 31 (cc30 and cc31) these capture/compare registers 30 and 31 are 16-bit registers. they can be used as capture regi sters or compare registers according to the cms1 and cms0 bit specifications of timer control register 31 (tmc31). these registers can be read/written in 16-bit unit s (however, write operations can only be performed in compare mode). caution continuous reading of cc3 n is prohibited. if cc3n is cont inuously read, the second read value may differ from the actual value. if cc3n mu st be read twice, be sure to read another register between the first and the second read operation. correct usage example in correct usage example cc30 read cc30 read cc31 read cc30 read cc30 read cc31 read cc31 read cc31 read cc31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cc30 fffff682h fffff684h 0000h 0000h address initial value 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 address initial value 0 (a) setting these registers to capture regi sters (cms1 and cms0 of tmc31 = 0) when these registers are set to capt ure registers, the valid edges of the corresponding external interrupt signals intp30 and intp31 are detected as capture triggers. the timer tm3 is synchronized with the capture trigger, and the value of tm3 is latched in the cc30 and cc 31 registers (capture operation). the valid edge of the intp30 pin is specified (rising, falling, or both edges) according to the ies301 and ies300 bits of the sesc register, and the valid edge of the intp31 pin is specified according to the ies311 and ies310 bits of the sesc register. the capture operation is performed asynchronously relati ve to the count clock. the latched value is held in the capture register until the next capture operation is performed. when the tm3cae bit of timer control regi ster 30 (tmc30) is 0, 0000h is read. if these registers are specified as c apture registers, an interrupt is generated by detecting the valid edge of signals intp30 and intp31. caution if the capture operation and the tm3 re gister count prohibit setting (tm3ce bit of tmc30 register = 0) timings conflict, th e captured data becomes undefined, and no intcc3n interrupt is ge nerated (n = 0, 1). chapter 9 timer/counter function (real-time pulse unit) 371 user?s manual u14492ej4v1ud (b) setting these registers to compare regi sters (cms1 and cms0 of tmc31 = 1) when these registers are set to compare registers, t he tm3 and register values are compared for each count clock, and an interrupt is generated by a ma tch. if the cclr bit of timer control register 31 (tmc31) is set (1), the tm3 value is cleared (0) at t he same time as a match with the cc30 register (it is not cleared (0) by a match with the cc31 register). a compare register is equipped with a set/reset output function. the corresponding timer output (to3) is set or reset, synchronized with the generation of a match signal. the interrupt selection source differs accord ing to the function of the selected register. cautions 1. to write to captur e/compare registers 30 and 31 (cc 30, cc31), always set the tm3cae bit to 1 first. when the tm3cae bit is 0, even if writ ing to registers cc30 and cc31, the data that is written wi ll be invalid because th e reset is asynchronous. 2. perform a write operation to capture/compa re registers 30 and 31 after setting them to compare registers according to the tmc30, tmc31 register setting. if they are set to capture registers (cms1 and cms0 bits of tmc 31 register = 0), no data is written even if a write operation is performed to cc30 and cc31. 3. when these registers are set to compare registers, intp30 and intp31 cannot be used as external interrupt input pins. chapter 9 timer/counter function (real-time pulse unit) 372 user?s manual u14492ej4v1ud 9.4.4 control registers (1) timer 3 clock selection register (prm03) the prm03 register is used to select the base clock (f clk ) of timer 3 (tm3). this register can be read/written in 8-bit or 1-bit units. cautions 1. always set this regi ster before using the timer. 2. set f clk to 32 mhz or less. 7 0 prm03 6 0 5 0 4 0 3 0 2 0 1 0 0 prm3 address fffff690h initial value 00h bit position bit name function 0 prm3 specifies the base clock (f clk ) of timer 3 (tm3). 0: f xx /2 (when f xx > 32 mhz) 1: f xx (when f xx 32 mhz) remark f xx : internal system clock chapter 9 timer/counter function (real-time pulse unit) 373 user?s manual u14492ej4v1ud (2) timer control register 30 (tmc30) the tmc30 register controls the operation of tm3. this register can be read/written in 8-bit or 1-bit units. cautions 1. the tm3cae bit and other bits cannot be set at the same time. be sure to set the tm3cae bit and then set the other bits a nd the other registers of tm3. to use an external pin related to the timer function when using timer 3, be sure to set (1) the tm3cae bit after setting the exter nal pin to the control mode. 2. if occurrence of an overflow conflicts with writing to the tmc30 register, the value of the tm3ovf bit is the value writ ten to the tmc30 register. (1/2) <7> tm3ovf tmc30 6 cs2 5 cs1 4 cs0 3 0 2 0 <1> tm3ce <0> tm3cae address fffff686h initial value 00h bit position bit name function 7 tm3ovf flag that indicates tm3 overflow. 0: no overflow 1: overflow the tm3ovf bit becomes ?1? when tm3 changes from ffffh to 0000h. an overflow interrupt request (inttm3) is generated at the same time. however, if cc30 is set to the compare mode (cms0 bit of the tmc31 register = 1) and match clear during comparison of tm3 and cc30 is enabled (cclr bit of tmc31 register = 1), and tm3 is cleared to 0000h following match at ffffh, tm3 is considered to have been cleared and the tm3ovf bit does not become ?1?, nor is the inttm3 interrupt generated. the tm3ovf bit holds a ?1? until ?0? is writt en to it or an asynchronous reset is applied while the tm3cae bit = 0. interrupts by overflow and the tm3ovf bit are independent, and even if the tm3ovf bit is manipulated, th is does not affect the interrupt request flag for inttm3 (tm3if0). if an overflow occu rs while the tm3ovf bit is being read, the value of the flag changes and the value is returned at the next read. chapter 9 timer/counter function (real-time pulse unit) 374 user?s manual u14492ej4v1ud (2/2) bit position bit name function selects the internal count clock for tm3. cs2 cs1 cs0 count clock 0 0 0 f clk /2 0 0 1 f clk /4 0 1 0 f clk /8 0 1 1 f clk /16 1 0 0 f clk /32 1 0 1 f clk /64 1 1 0 f clk /128 1 1 1 f clk /256 6 to 4 cs2 to cs0 caution do not change the cs2 to cs0 bits during timer operation. if they are to be changed, they must be changed after setting the tm3ce bit to ?0?. if the cs2 to cs0 bits are overwritten during timer operation, the operation is not guaranteed. remark f clk : base clock 1 tm3ce controls the operation of tm3. 0: disable count (timer stopped at 0000h and does not operate) 1: perform count operation. caution if tm3ce = 0, the external pulse output (to3) becomes inactive level (the active level of to3 output is set with the alv bit of the tmc31 register). 0 tm3cae controls the internal count clock. 0: asynchronously reset entire tm3 unit. stop base clock supply to tm3 unit. 1: supply base clock (f clk ) to tm3 unit. cautions 1. when tm3cae = 0 is set, the tm3 unit can be reset asynchronously. 2. when tm3cae = 0, the tm3 unit is in a reset state. to operate tm3, first set tm3cae = 1. 3. when the tm3cae bit is changed from ?1? to ?0?, all the registers of the tm3 unit are initialized. when again setting tm3cae = 1, be sure to then again set all the registers of the tm3 unit. chapter 9 timer/counter function (real-time pulse unit) 375 user?s manual u14492ej4v1ud (3) timer control register 31 (tmc31) the tmc31 register controls the operation of tm3. this register can be read/written in 8-bit or 1-bit units. cautions 1. do not change the bits of the tmc31 register during timer operation. if they are to be changed, they must be changed after setting the tm3ce bit of the tmc30 register to ?0?. if the tmc31 register is overwritte n during timer operation, the operation is not guaranteed. 2. if the ent1 bit and the alv bit are ch anged simultaneously, a glitch (spike-shaped noise) may be generated in the to3 pin out put. either design the circuit that will not malfunction even if a glitch is generated, or make sure that the ent1 bit and the alv bit do not change at the same time. 3. to3 output remains unchanged by external interrupt signals (intp30, intp31). when using the to3 signal, set the capture/compare register to the compare register (cms1, cms0 bits of tmc31 register = 1). remark a reset takes precedence for t he flip-flop of the to3 output. chapter 9 timer/counter function (real-time pulse unit) 376 user?s manual u14492ej4v1ud 7 ost tmc31 6 ent1 5 alv 4 eti 3 cclr 2 eclr 1 cms1 0 cms0 address fffff688h initial value 20h bit position bit name function 7 ost sets the operation when tm3 overflows. 0: continue count operation afte r overflow (free-running mode) 1: after overflow, timer holds 0000h and stops count operation (overflow stop mode). at this time, the tm3ce bit of tmc30 remains ?1?. the count operation is resumed by again writing ?1? to the tm3ce bit. 6 ent1 enables/disables output of external pulse output (to3). 0: disable external pulse output. output of inactive level of alv bit to to3 pin is fixed. to3 pin level remains unchanged even if match signal from corresponding compare register is generated. 1: enable external pulse output. compare register match causes to3 output to change. however, in capture mode, to3 output does not change. an alv bit inactive level is output from the time when timer output is enabled until a match signal is generated. caution if either cc30 or cc31 is specified as a capture register, the ent1 bit must be set to ?0?. 5 alv specifies active level of external pulse output (to3). 0: active level is low level. 1: active level is high level. caution the initial value of the alv bit is ?1?. 4 eti switches count clock between ex ternal clock and internal clock. 0: specifies input clock (internal). the count clock can be selected with bits cs2 to cs0 of tmc30. 1: specifies external clock (ti3). va lid edge can be selected with bits tes31, tes30 of sesc. 3 cclr enables/disables tm3 clea ring during compare operation. 0: disable clearing. 1: enable clearing (tm3 is cleared when cc30 and tm3 match during compare operation). 2 eclr enables tm3 clearing by external clear input (tclr3). 0: disable clearing by tclr3. 1: enable clearing by tclr3 (cou nting resumes after clearing). 1 cms1 selects operation mode of capture/compare register (cc31). 0: register operates as capture register. 1: register operates as compare register. 0 cms0 selects operation mode of capture/compare register (cc30). 0: register operates as capture register. 1: register operates as compare register. chapter 9 timer/counter function (real-time pulse unit) 377 user?s manual u14492ej4v1ud (4) valid edge select ion register (sesc) this register specifies the valid edge of external inte rrupt requests (ti3, tclr3, intp30, intp31) from an external pin. the rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin. this register can be read/written in 8-bit or 1-bit units. caution do not change the bits of sesc register during timer operati on. if they are to be changed, they must be changed after setting the tm3ce bit of the tmc30 register to ?0?. if the sesc register is overwritten dur ing timer operation, the operation is not guaranteed. 7 tes31 sesc 6 tes30 5 ces31 4 ces30 3 ies311 2 ies310 1 ies301 0 ies300 address fffff689h initial value 00h ti3 tclr3 intp31 intp30 bit position bit name function 7, 6 tes31, tes30 specifies the valid edge of intp30, intp31 pins, tclr3, and ti3 pins. xesn1 xesn0 operation 5, 4 ces31, ces30 0 0 falling edge 0 1 rising edge 3, 2 ies311, ies310 1 0 setting prohibited 1 1 both rising and falling edges 1, 0 ies301, ies300 remark n = 3, 30, 31 chapter 9 timer/counter function (real-time pulse unit) 378 user?s manual u14492ej4v1ud 9.4.5 operation (1) count operation timer 3 can function as a 16-bit free-running timer or as an external signal event counter. the setting for the type of operation is specified by timer c ontrol register 3n (tmc3n) (n = 0, 1). when it operates as a free-running timer, if the cc30 or cc31 register and the tm3 count value match, an interrupt signal is generated and the timer output signal (to3) can be set or reset. also, a capture operation that holds the tm3 count value in the cc30 or cc31 register is performed, synchronized with the valid edge that was detected from the external interrupt request input pin as an external trigger. the capture value is held until the next captur e trigger is generated. caution if the intp30/ti3/tclr3 pin is used as ti3 or tclr3, either mask the intp30 interrupt or set the cc3n register to compare mode (n = 0, 1). figure 9-87. basic operation of timer 3 0001h 0000h 0002h 0003h fbfeh fbffh 0001h 0002h 0000h tm3 count clock ? count disabled tm3ce 0 ? count start tm3ce 1 ? count start tm3ce 1 chapter 9 timer/counter function (real-time pulse unit) 379 user?s manual u14492ej4v1ud (2) overflow when the tm3 register has counted the count clock from ffffh to 0000h, the tm3ovf bit of the tmc30 register is set (1), and an overflow interrupt (inttm3) is generated at the same time. however, if the cc30 register is set to compare mode (cms0 bit = 1) and to the value ffffh when match clearing is enabled (cclr bit = 1), then the tm3 register is considered to be cleared and the tm3ovf bit is not set (1) when the tm3 register changes from ffffh to 0000h. also, t he overflow interrupt (inttm3) is not generated. when the tm3 register is changed from ffffh to 0000h because the tm3ce bit changes from 1 to 0, the tm3 register is considered to be cleared, but the tm3ovf bit is not set (1) and no inttm3 interrupt is generated. also, timer operation can be stopped after an overflow by setting the ost bit of the tmc31 register to 1. when the timer is stopped due to an overflow, the count o peration is not restarted un til the tm3ce bit of the tmc30 register is set (1). operation is not affected even if the tm3c e bit is set (1) during a count operation. figure 9-88. operation after overflow (when ost = 1) overflow count start overflow ffffh ffffh tm3 0 inttm3 ost 1 tm3ce 1 tm3ce 1 chapter 9 timer/counter function (real-time pulse unit) 380 user?s manual u14492ej4v1ud (3) capture operation the tm3 register has two capture/comp are registers. these are the cc30 register an d the cc31 register. a capture operation or a compare oper ation is performed according to the settings of both the cms1 and cms0 bits of the tmc31 register. if the cms1 and cms0 bits of the tmc31 register ar e set to 0, the register operates as a capture register. a capture operation that capt ures and holds the tm3 count value asynchronously relative to the count clock is performed synchronized with an external trigger. the valid edge that is detected from an external interrupt request input pin (intp30 or intp31) is used as an ex ternal trigger (capture trigger). the tm3 count value during counting is captured and held in the capture regist er, synchronized with that capture trigger signal. the capture register value is held until the next capt ure trigger is generated. also, an interrupt request (intcc30 or intcc31) is generated by intp30 or intp31 signal input. the valid edge of the capture trigger is se t by valid edge selection register (sesc). if both the rising and falling edges are set as capture tri ggers, the input pulse width from an external source can be measured. also, if only one of the edges is set as the capture trigger, the input pulse cycle can be measured. figure 9-89. capture operation example tm3 0 tm3ce intp31 cc31 (capture register) n n (capture trigger) (capture trigger) remarks 1. when the tm3ce bit is 0, no capture operat ion is performed even if intp31 is input. 2. valid edge of intp31: rising edge chapter 9 timer/counter function (real-time pulse unit) 381 user?s manual u14492ej4v1ud figure 9-90. tm3 capture operation e xample (when both edges are specified) tm3 ? count start tm3ce 1 ? overflow tm3ovf 1 d0 d1 d2 d0 d1 d2 interrupt request (intp31) (tm3 count values) capture register (cc31) remark d0 to d2: tm3 count values chapter 9 timer/counter function (real-time pulse unit) 382 user?s manual u14492ej4v1ud (4) compare operation the tm3 register has two capture/comp are registers. these are the cc30 register an d the cc31 register. a capture operation or a compare oper ation is performed according to the settings of both the cms1 and cms0 bits of the tmc31 register. if 1 is set in the cms1 and cms0 bits of the tmc31 register, the register operates as a compare register. a compare operation that compares t he value that was set in the compar e register and the tm3 count value is performed. if the tm3 count value matches the value of the com pare register, which had been set in advance, a match signal is sent to the output controlle r. the match signal causes the timer output pin (to3) to change and an interrupt request signal (intcc30, intcc3 1) to be generated at the same time. if the cc30 or cc31 register is set to 0000h, the 0000h after the tm3 register counts up from ffffh to 0000h is judged as a match. in this case, the value of the tm3 register is cleared to 0 at the next count timing, but 0000h is not judged as a match at that time. 0000h when the tm3 register begins counting is not judged as a match either. if match clearing is enabled (cclr bit = 1) for the cc30 register, the tm3 register is cleared when a match with the tm3 register occurs during a compare operation. figure 9-91. compare op eration example (1/2) (a) if cclr bit = 1 and cc30 is value other than 0000h 0001h tm3 count up 0000h n n n ? 1 compare register (cc30) match detection (intcc30) to3 (output) remarks 1. the match is detected immediately after the count up, and the match detection signal is generated. 2. n 0000h chapter 9 timer/counter function (real-time pulse unit) 383 user?s manual u14492ej4v1ud figure 9-91. compare op eration example (2/2) (b) if cclr bit = 1 and cc30 is 0000h 0001h tm3 count up 0000h 0000h 0000h ffffh compare register (cc30) inttm3 match detection (intcc30) to3 (output) remark the match is detected immediately after the count up, and the match detection signal is generated. chapter 9 timer/counter function (real-time pulse unit) 384 user?s manual u14492ej4v1ud (5) external pulse output timer 3 has one timer output pin (to3). an external pulse output (to3) is generated when a match of the two compare registers (cc30 and cc31) and the tm3 register is detected. if a match is detected when the tm3 count value and the cc30 value are compared, the output level of the to3 pin is set. also, if a match is detected when the tm3 count value and the cc31 value are compared, the output level of the to3 pin is reset. the output level of the to 3 pin can be specified by the tmc31 register. table 9-13. to3 output control to3 output ent1 alv external pulse output output level 0 0 disable high level 0 1 disable low level 1 0 enable when the cc30 register is matched: low level when the cc31 register is matched: high level 1 1 enable when the cc30 register is matched: high level when the cc31 register is matched: low level figure 9-92. tm3 compare operation example (set/reset output mode) tm3 count value 0 count start tm3ce1 1 clear & start clear & start cc30 cc30 cc31 cc31 cc31 interrupt request (intcc30) interrupt request (intcc31) to3 pin ent1 1 alv 0 chapter 9 timer/counter function (real-time pulse unit) 385 user?s manual u14492ej4v1ud 9.4.6 application examples (1) interval timer by setting the tmc30 and tmc31 registers as shown in figure 9-93, timer 3 operates as an interval timer that repeatedly generates interrupt requests with the value that was set in advance in the cc30 register as the interval. when the counter value of the tm3 register matches th e setting value of the cc30 register, the tm3 register is cleared (0000h) and an interrupt request signal (intcc 30) is generated at the sa me time that the count operation resumes. figure 9-93. contents of register settings when timer 3 is used as interval timer supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 1 0/1 0/1 1 ost ent1 alv eti cclr cms1 cms0 0/1 0/1 0/1 0/1 0 0 1 1 tm3ovf tmc30 tmc31 cs2 cs1 cs0 tm3ce tm3cae use cc30 register as compare register clear tm3 register due to match with cc30 register continue counting after tm3 register overflows eclr remark 0/1: set to 0 or 1 as necessary chapter 9 timer/counter function (real-time pulse unit) 386 user?s manual u14492ej4v1ud figure 9-94. interval time r operation timing example count start 0001h 0000h 0001h 0000h 0001h p pp pp pp 0000h interval time interval time interval time count clock t tm3 register cc30 register intcc30 interrupt clear clear remark p: setting value of cc30 register (0000h to ffffh) t: count clock cycle interval time = (p + 1) t chapter 9 timer/counter function (real-time pulse unit) 387 user?s manual u14492ej4v1ud (2) pwm output by setting the tmc30 and tmc31 registers as shown in figure 9-95, timer 3 can output a pwm of the frequency determined by the setting of the cs2 to cs0 bits of the tmc30 register with the values that were set in advance in the cc30 and cc31 registers as the intervals. when the counter value of the tm3 register matches t he setting value of the cc30 register, the to3 output becomes active. then, when the count value of the tm3 register matches the setting value of the cc31 register, the to3 output becomes inactive. the tm3 register continues counting, and when an overflow occurs, clears the count value to 0000h and contin ues counting. this enables a pwm of the frequency determined by the setting of the cs2 to cs0 bits of the tmc30 register to be output. when the setting value of the cc30 register and the setting value of the cc31 register are the same, the to3 output remains inactive and does not change. the active level of to3 output can be set by the alv bit of the tmc31 register. figure 9-95. contents of register settings when timer 3 is used for pwm output supply input clocks to internal units enable count operation 0 1 0/1 0/1 0 0/1 1 1 ost ent1 alv eti cclr cms1 cms0 0/1 0/1 0/1 0/1 0 0 1 1 tm3ovf tmc30 tmc31 cs2 cs1 cs0 tm3ce tm3cae use cc30 register as compare register use cc31 register as compare register disable clearing of tm3 register due to match with cc30 register enable external pulse output (to3) continue counting after tm3 register overflows eclr remark 0/1: set to 0 or 1 as necessary chapter 9 timer/counter function (real-time pulse unit) 388 user?s manual u14492ej4v1ud figure 9-96. pwm output operation timing example count start clear 0001h 0000h 0001h 0000h ffffh p ppp p p qqq q q qq p count clock tm3 register cc30 register cc31 register intcc30 interrupt intcc31 interrupt to3 (output) t remarks 1. p: setting value of cc 30 register (0000h to ffffh) q: setting value of cc 31 register (0000h to ffffh) p q t: count clock cycle pwm cycle = 65536 t q ? p 65536 2. in this example, the active level of to3 output is set to high level. duty = chapter 9 timer/counter function (real-time pulse unit) 389 user?s manual u14492ej4v1ud (3) cycle measurement by setting the tmc30 and tmc31 registers as shown in figure 9-97, timer 3 can measure the cycle of signals input to the intp30 pin or intp31 pin. the valid edge of the intp30 pin is selected accordin g to the ies301 and ies300 bi ts of the sesc register, and the valid edge of the intp31 pin is selected a ccording to the ies311 and ies310 bits of the sesc register. either the rising edge, t he falling edge, or both edges can be selected as the valid edges of both pins. if the cc30 register is set to a capture register and tm3 is started, the valid edge input of the intp30 pin is set as the trigger for capturing the tm3 register value in the cc30 register. when this value is captured, an intcc30 interrupt is generated. similarly, if the cc31 register is set to a capture regi ster and tm3 is started, the valid edge input of the intp31 pin is set as the trigger for capturing the tm3 r egister value in the cc31 register. when this value is captured, an intcc31 interrupt is generated. the cycle of signals input to the intp30 pin is calc ulated by obtaining the difference between the tm3 register?s count value (dx) that was captured in the cc30 register accordi ng to the x-th valid edge input of the intp30 pin and the tm3 register?s count value (d(x+1)) th at was captured in the cc30 register according to the (x+1)-th valid edge input of the intp30 pin and multip lying the value of this difference by the cycle of the clock control signal. the cycle of signals input to the intp31 pin is calc ulated by obtaining the difference between the tm3 register?s count value (dx) that was captured in the cc31 register accordi ng to the x-th valid edge input of the intp31 pin and the tm3 register?s count value (d(x+1)) th at was captured in the cc31 register according to the (x+1)-th valid edge input of the intp31 pin and multip lying the value of this difference by the cycle of the clock control signal. figure 9-97. contents of register settings when timer 3 is used for cycle measurement supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 0/1 0/1 0 0 ost ent1 alv eti cclr cms1 cms0 0/1 0/1 0/1 0/1 0 0 1 1 tm3ovf tmc30 tmc31 cs2 cs1 cs0 tm3ce tm3cae use cc30 register as capture register (when measuring the cycle of intp30 input) use cc31 register as capture register (when measuring the cycle of intp31 input) continue counting after tm3 register overflows eclr remark 0/1: set to 0 or 1 as necessary chapter 9 timer/counter function (real-time pulse unit) 390 user?s manual u14492ej4v1ud figure 9-98. cycle measurement operation timing example t 0001h 0000h 0001h 0000h ffffh d0 d1 d2 d3 d3 d2 d1 d0 (d1 ? d0) t (d3 ? d2) t {(10000h ? d1) + d2} t note count clock tm3 register intp30 (input) cc30 register intcc30 interrupt inttm3 interrupt no overflow overflow occurs no overflow clear count start note when an overflow occurs once remarks 1. d0 to d3: tm3 register count values t: count clock cycle 2. in this example, the valid edge of intp30 input has been set to both edges (rising and falling). chapter 9 timer/counter function (real-time pulse unit) 391 user?s manual u14492ej4v1ud 9.4.7 precautions various precautions concerning timer 3 are shown below. (1) if a conflict occurs between the reading of the cc30 register and a capture operati on when the cc30 register is used in capture mode, an external trigger (intp30) valid edge is detec ted and an external interrupt request signal (intcc30) is generated however, the time r value is not stored in the cc30 register. (2) if a conflict occurs between the reading of the cc31 register and a capture operati on when the cc31 register is used in capture mode, an external trigger (intp31) valid edge is detec ted and an external interrupt request signal (intcc31) is generated however, the time r value is not stored in the cc31 register. (3) the following bits and registers must not be rewr itten during operation (tmc30 register tm3ce = 1). ? cs2 to cs0 bits of tmc30 register ? tmc31 register ? sesc register (4) the tm3cae bit of the tmc30 register is a tm3 re set signal. to use tm3, first set (1) the tm3cae bit. (5) the analog noise elimination time + two count clo cks are required to detect a valid edge of the external interrupt input (intp30 or intp31) and external clock input (ti3). t herefore, edge detection will not be performed normally for changes that are less than the anal og noise elimination time + two count clocks. for the analog noise elimination, refer to 14.5 noise eliminator . (6) the operation of an external interr upt output (intcc30 or in tcc31) is automatically determined according to the operating state of t he capture/compare registers 30, 31 (cc3 0, cc31). when the capture/compare register is used for a capture mode, the external trigger (intp30, intp31) is used for valid edge detection. when the capture/compare register is used for a com pare mode, the external inte rrupt output is used for a match interrupt indicating a match with the tm3 register. (7) if the ent1 and alv bits of the tmc31 register are changed at the same time, a glitch (spike shaped noise) may be generated in the to3 pin output. either create a circuit configuration that will not malfunction even if a glitch is generated or make sure that the ent1 and alv bits do not change at the same time. chapter 9 timer/counter function (real-time pulse unit) 392 user?s manual u14492ej4v1ud 9.5 timer 4 9.5.1 features (timer 4) timer 4 (tm4) functions as a 16-bit interval timer. 9.5.2 function overview (timer 4) ? 16-bit interval timer: 1 channel ? compare register: 1 ? count clock selected from divisions of internal system clock (set the frequency of the count clock to 16 mhz or less) ? base clock (f clk ): 1 type (set f clk to 32 mhz or less) f xx /2 ? prescaler division ratio the following division ratios can be selected according to the base clock (f clk ). division ratio base clock (f clk ) 1/2 f xx /4 1/4 f xx /8 1/8 f xx /16 1/16 f xx /32 1/32 f xx /64 1/64 f xx /128 1/128 f xx /256 1/256 f xx /512 ? interrupt request source: 1 ? compare match interrupt intcm4 generated with cm4 match signal ? timer clear tm4 register can be cleared by cm4 register match. remark f xx : internal system clock chapter 9 timer/counter function (real-time pulse unit) 393 user?s manual u14492ej4v1ud 9.5.3 basic configuration table 9-14. timer 4 configuration list timer count clock register read/write generated interrupt signal capture trigger timer output s/r other functions tm4 read ? ? ? ? timer 4 f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512 cm4 read/write intcm4 ? ? ? remark f xx : internal system clock s/r: set/reset figure 9-99 shows the block diagram of timer 4. figure 9-99. block di agram of timer 4 tm4 (16-bit) cm4 intcm4 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 f xx /2 clear & start f clk remark f clk : base clock (32 mhz (max.)) f xx : internal system clock chapter 9 timer/counter function (real-time pulse unit) 394 user?s manual u14492ej4v1ud (1) timer 4 (tm4) tm4 is a 16-bit timer. it is mainly used as an interval timer for software. starting and stopping tm4 is controlled by the tm4ce0 bit of the timer control register 4 (tmc4). a division by the prescaler can be selected for the count clock from among f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, and f xx /512 by the cs2 to cs0 bits of the tmc4 register (f xx : internal system clock). tm4 is read-only, in 16-bit units. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tm4 fffff540h 0000h address initial value 0 the conditions for which the tm4 regi ster becomes 0000h are shown below. ? reset input ? tm4cae0 bit = 0 ? tm4ce0 bit = 0 ? match of tm4 register and cm4 register ? overflow cautions 1. if the tm4cae0 bit of the tmc4 re gister is cleared (0), a reset is performed asynchronously. 2. if the tm4ce0 bit of the tmc4 register is cleared (0), a reset is performed, synchronized with the internal clock. similarly, a sync hronized reset is perfor med after a match with the cm4 register and after an overflow. 3. the count clock must not be changed during a ti mer operation. if it is to be overwritten, it should be overwritten after the tm4ce0 bit is cleared (0). 4. up to 4 internal system clocks are required after a value is set in the tm4ce0 bit until the set value is transferred to internal units. when a co unt operation begins, the count cycle from 0000h to 0001h differs from subsequent count cycles. 5. after a compare match is generated, the timer is cleared at the next count clock. therefore, if the division ratio is large, the timer value may not be zero even if the timer value is read immediately after a match interrupt is generated. chapter 9 timer/counter function (real-time pulse unit) 395 user?s manual u14492ej4v1ud (2) compare register 4 (cm4) cm4 and the tm4 register count value are compared, a nd an interrupt request signal (intcm4) is generated when a match occurs. tm4 is cleared, synchronized with this match. if the tm4cae0 bit of the tmc4 register is set to 0, a reset is performed asynchronously, and the registers are initialized. the cm4 register is confi gured with a master/slave configuration. when a write operation to a cm4 register is performed, data is first written to the master regist er and then the master regist er data is transferred to the slave register. in a compare operation, the slave regi ster value is compared with the count value of the tm4 register. when a read operation to a cm4 register is performed, data in the master side is read out. cm4 can be read/written in 16-bit units. cautions 1. a write operation to a cm4 register requires 4 internal s ystem clocks until the value that was set in the cm4 register is transferred to internal units. when writing continuously to the cm4 register, be sure to reserve a ti me interval of at least 4 internal system clocks. 2. the cm4 register can be overwritten onl y once in a single tm4 register cycle (from 0000h until an intcm4 interrupt is generated due to a matc h of the tm4 register and cm4 register). if this cannot be secured by the application, make sure that the cm4 register is not overwritte n during timer operation. 3. note that an intcm4 interr upt will be generated after an o verflow if a value less than the counter value is written in the cm4 register during tm4 re gister operation (figure 9-100). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cm4 fffff542h 0000h address initial value 0 chapter 9 timer/counter function (real-time pulse unit) 396 user?s manual u14492ej4v1ud figure 9-100. example of ti ming during tm4 operation (a) when tm4 < cm4 tm4 tm4cae0 tm4ce0 cm4 intcm4 mn n n remark m = tm4 value when overwritten n = cm4 value when overwritten m < n (b) when tm4 > cm4 tm4 tm4cae0 tm4ce0 cm4 intcm4 m ffffh n n n remark m = tm4 value when overwritten n = cm4 value when overwritten m > n chapter 9 timer/counter function (real-time pulse unit) 397 user?s manual u14492ej4v1ud 9.5.4 control register (1) timer control register 4 (tmc4) the tmc4 register controls the operation of timer 4. this register can be read/written in 8-bit or 1-bit units. caution the tm4cae0 bit and other bits cannot be set at the same time. be sure to set the tm4cae0 bit and then set the other bi ts and the other registers of tm4. 7 6 5 4 3 2 <1> <0> address initial value tmc4 0 cs2 cs1 cs0 0 0 tm4ce0 tm4cae0 fffff544h 00h bit position bit name function selects the tm4 count clock. cs2 cs1 cs0 count clock 0 0 0 f xx /4 0 0 1 f xx /8 0 1 0 f xx /16 0 1 1 f xx /32 1 0 0 f xx /64 1 0 1 f xx /128 1 1 0 f xx /256 1 1 1 f xx /512 6 to 4 cs2 to cs0 caution do not change the cs2 to cs0 bits during timer operation. if they are to be changed, they must be changed after setting the tm4ce0 bit to 0. if the cs2 to cs0 bits are overwritten during timer operation, the operation is not guaranteed. 1 tm4ce0 controls the operation of tm4. 0: disable count (timer stopped at 0000h and does not operate) 1: perform count operation caution tm4ce0 bit is not cleared even if a match is detected by the compare operation. to stop the count operation, clear the tm4ce0 bit. 0 tm4cae0 controls the internal count clock. 0: asynchronously reset entire tm4 unit. stop base clock (f clk ) supply to tm4 unit. 1: supply base clock (f clk ) to tm4 unit. cautions 1. when tm4cae0 = 0 is set, the tm4 unit can be reset asynchronously. 2. when tm4cae0 = 0, the tm4 unit is in a reset state. to operate tm4, first set tm4cae0 = 1. 3. when the tm4cae0 bit is changed from 1 to 0, all the registers of the tm4 unit are initialized. when again setting tm4cae0 = 1, be sure to then again set all the registers of the tm4 unit. chapter 9 timer/counter function (real-time pulse unit) 398 user?s manual u14492ej4v1ud 9.5.5 operation (1) compare operation tm4 can be used for a compare operation in which the va lue that was set in a compare register (cm4) is compared with the tm4 count value. if a match is detected by the compare operation, an in terrupt (intcm4) is generated. the generation of the interrupt causes tm4 to be cleared (0) at the next coun t timing. this function enables timer 4 to be used as an interval timer. cm4 can also be set to 0. in this case, when an ov erflow occurs and tm4 becomes 0, a match is detected and intcm4 is generated. although the tm4 value is cl eared (0) at the next count timing, intcm4 is not generated according to this match. figure 9-101. tm4 compare operation example (1/2) (a) when cm4 is set to n (non-zero) 1 tm4 count clock 0 n cm4 n tm4 clear match detection (intcm4) count up clear remark interval time = (n + 1) count clock cycle n = 1 to 65536 (ffffh) chapter 9 timer/counter function (real-time pulse unit) 399 user?s manual u14492ej4v1ud figure 9-101. tm4 compare operation example (2/2) (b) when cm4 is set to 0 1 0 0 0 ffffh overflow tm4 count clock cm4 tm4 clear match detection (intcm4) count up clear remark interval time = (ffffh + 2) count clock cycle chapter 9 timer/counter function (real-time pulse unit) 400 user?s manual u14492ej4v1ud 9.5.6 application example (1) interval timer this section explains an example in which timer 4 is used as an interval timer with 16-bit precision. interrupt requests (intcm4) are output at equal intervals (refer to figure 9-101 tm4 compare operation example ). the setup procedure is shown below. <1> set (1) the tm4cae0 bit. <2> set each register. ? select the count clock using the cs2 to cs0 bits of the tmc4 register. ? set the compare value in the cm4 register. <3> start counting by setting (1) the tm4ce0 bit. <4> if the tm4 register and cm4 register val ues match, an intcm4 interrupt is generated. <5> intcm4 interrupts are generated thereafter at equal intervals. 9.5.7 precautions various precautions concerning timer 4 are shown below. (1) to operate tm4, first set (1) the tm4cae0 bit of the tmc4 register. (2) up to 4 internal system clocks are required after a va lue is set in the tm4ce0 bit of the tmc4 register until the set value is transferred to internal units. when a count operation begins, the count cycle from 0000h to 0001h differs from subsequent count cycles. (3) to initialize the tm4 register status and start counti ng again, clear (0) the tm4ce0 bit and then set (1) the tm4ce0 bit after an interval of 4 internal system clocks has elapsed. (4) up to 4 internal system clocks are required until the value that was set in the cm 4 register is transferred to internal units. when writing continuous ly to the cm4 register, be sure to se cure a time interval of at least 4 internal system clocks. (5) the cm4 register can be over written only once during a timer/counter operation (from 0000h until an intcm4 interrupt is generated due to a match of the tm4 register and cm4 regi ster). if this cannot be secured by the application, make sure that the cm 4 register is not overwri tten during a timer/counter operation. (6) the count clock must not be changed during a timer o peration. if it is to be overwritten, it should be overwritten after the tm4ce0 bit is cleared (0). if the count clock is overwritten during a timer operation, operation cannot be guaranteed. (7) an intcm4 interrupt will be generated after an overflow if a value less than the counter value is written in the cm4 register during tm4 register operation. chapter 9 timer/counter function (real-time pulse unit) 401 user?s manual u14492ej4v1ud 9.6 timer connection function 9.6.1 overview the v850e/ia1 provides a function to connect timer 1 and timer 2. figure 9-102. block diagram of timer connection function timer 2 timer 1 cvse10/ cvpe10 cvse20/ cvpe20 capture 0 capture 1 tmic0 tmic1 tmic2 tmic3 tmic0 register intcm1 intcm0 intcm101 intcm100 timer connection selector chapter 9 timer/counter function (real-time pulse unit) 402 user?s manual u14492ej4v1ud 9.6.2 control register (1) timer connection selection register 0 (tmic0) the tmic0 register enables/disable s input of the intcm100, intcm1 01 signals to the cvsen0/cvpen0 registers (n = 1, 2). this register can be read/written in 8-bit or 1-bit units. 7 0 tmic0 6 0 5 0 4 0 3 tmic3 2 tmic2 1 tmic1 0 tmic0 address fffff620h initial value 00h bit position bit name function 3 tmic3 enables/disables input of intc m101 signal to cvse20/cvpe20 registers. 0: don?t input intcm101 signal to cvse20/cvpe20 registers. 1: input intcm101 signal to cvse20/cvpe20 registers. 2 tmic2 enables/disables input of intc m100 signal to cvse20/cvpe20 registers. 0: don?t input intcm100 signal to cvse20/cvpe20 registers. 1: input intcm100 signal to cvse20/cvpe20 registers. 1 tmic1 enables/disables input of intc m101 signal to cvse10/cvpe10 registers. 0: don?t input intcm101 signal to cvse10/cvpe10 registers. 1: input intcm101 signal to cvse10/cvpe10 registers. 0 tmic0 enables/disables input of intc m100 signal to cvse10/cvpe10 registers. 0: don?t input intcm100 signal to cvse10/cvpe10 registers. 1: input intcm100 signal to cvse10/cvpe10 registers. user?s manual u14492ej4v1ud 403 chapter 10 serial interface function 10.1 features the serial interface function provides three types of seri al interfaces combining a total of six transmit/receive channels. all six channels can be used simultaneously. the three interface formats are as follows. (1) asynchronous serial interfaces (uart0 to uart2): 3 channels (2) clocked serial interfaces (csi0, csi1): 2 channels (3) fcan controller: 1 channel remark for details about the fcan controller, refer to chapter 11 fcan controller . uart0 to uart2, whereby one byte of serial data is tr ansmitted/received following a start bit, support full-duplex communication. in the uart1 and uart2 interfaces, one hi gher bit is added to 8 bits of transmit/receive data, enabling communication using 9-bit data. csi0 and csi1 perform data transfer according to three types of signals, namely serial clocks (sck0, sck1), serial inputs (si0, si1), and serial outputs (so0, so1) (3-wire serial i/o). fcan conforms to can specification ver. 2.0 partb active, and provides a 32-message buffer. chapter 10 serial interface function user?s manual u14492ej4v1ud 404 10.2 asynchronous serial interface 0 (uart0) 10.2.1 features ? transfer rate: 300 bps to 1562.5 kb ps (using a dedicated bau d rate generator and an in ternal system clock of 50 mhz) ? full-duplex communications on-chip reception buffer register 0 (rxb0) on-chip transmission buffer register 0 (txb0) ? two-pin configuration note txd0: transmit data output pin rxd0: receive data input pin ? reception error detection functions ? parity error ? framing error ? overrun error ? interrupt sources: 3 types ? reception error interrupt (intser0): interrupt is generated according to the logical or of the three types of reception errors ? reception completion interrupt (intsr0): interrupt is generated when receive data is transferred from the shift register to the recepti on buffer register 0 after serial transfer is completed during a reception enabled state ? transmission completion interrupt (intst0): interr upt is generated when the serial transmission of transmit data (8 or 7 bits) from the shift register is completed ? the character length of transmit/receive data is specified according to the asim0 register ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? on-chip dedicated baud rate generator note the sck and cts pins are not available for uart0. chapter 10 serial interface function user?s manual u14492ej4v1ud 405 10.2.2 configuration uart0 is controlled by the asynchronous serial interface mode register 0 (asim0), asynchronous serial interface status register 0 (asis0), and asynchro nous serial interface transmission status register 0 (asif0). receive data is maintained in the reception buffer register 0 (rxb0), and tr ansmit data is written to the transmission buffer register 0 (txb0). figure 10-1 shows the configuration of the asynchronous serial interface 0 (uart0). (1) asynchronous serial interfa ce mode register 0 (asim0) the asim0 register is an 8-bit register for specifying the operation of the asynch ronous serial interface. (2) asynchronous serial interfa ce status register 0 (asis0) the asis0 register consists of a set of flags that indicate the error contents when a reception error occurs. the various reception error flags are set (1) when a re ception error occurs and are reset (0) when the asis0 register is read. (3) asynchronous serial interface tran smission status register 0 (asif0) the asif0 register is an 8-bit regist er that indicates the status when a transmit operation is performed. this register consists of a transmission buffer data flag, which indicates the hold st atus of txb0 data, and the transmission shift register data flag, which in dicates whether transmission is in progress. (4) reception control parity check the receive operation is controlled according to the c ontents set in the asim0 register. a check for parity errors is also performed during a re ceive operation, and if an error is detected, a value corresponding to the error contents is set in the asis0 register. (5) reception shift register this is a shift register that converts the serial data t hat was input to the rxd0 pin to parallel data. one byte of data is received, and if a stop bit is detected, the re ceive data is transferred to the reception buffer register 0 (rxb0). this register cannot be directly manipulated. (6) reception buffer register 0 (rxb0) rxb0 is an 8-bit buffer register for holding receive data. when 7 characters are received, 0 is stored in the msb. during a reception enabled state, receive data is transf erred from the reception shift register to the rxb0, synchronized with the end of the sh ift-in processing of one frame. also, the reception completion interrupt request (intsr0) is generated by the transfer of data to the rxb0. (7) transmission shift register this is a shift register that converts the parallel data that was transferred from the transmission buffer register 0 (txb0) to serial data. when one byte of data is transferred from the txb0, t he shift register data is out put from the txd0 pin. the transmission completion interrupt request (intst0) is generated synchronized with the completion of transmission of one frame. this register cannot be directly manipulated. chapter 10 serial interface function user?s manual u14492ej4v1ud 406 (8) transmission buffer register 0 (txb0) txb0 is an 8-bit buffer for transmit data. a transmit oper ation is started by writing transmit data to txb0. (9) addition of transmission control parity a transmit operation is controlled by adding a start bit, par ity bit, or stop bit to the dat a that is written to the txb0 register, according to the contents that were set in the asim0 register. figure 10-1. asynchronous seri al interface 0 block diagram parity framing overrun internal bus asynchronous serial interface mode register 0 (asim0) reception buffer register 0 (rxb0) reception shift register reception control parity check transmission buffer register 0 (txb0) transmission shift register addition of transmission control parity brg0 intser0 intsr0 intst0 rxd0 txd0 chapter 10 serial interface function user?s manual u14492ej4v1ud 407 10.2.3 control registers (1) asynchronous serial interfa ce mode register 0 (asim0) the asim0 register is an 8-bit register t hat controls the uart0 transfer operation. this register can be read/written in 8-bit or 1-bit units. cautions 1. when using uart0, be sure to set the external pins related to the uart0 function to the control mode before setting clock selection register 0 (cksr0) a nd baud rate generator control register 0 (brgc0), and then set th e uartcae0 bit to 1. then set the other bits. 2. set the uartcae0 and rxe0 bits to 1 while a high level is input to the rxd0 pin. if these bits are set to 1 while a low high level is input to the rxd0 pin, reception will be started. (1/3) <7> uartcae0 asim0 <6> txe0 <5> rxe0 4 ps1 3 ps0 2 cl 1 sl 0 isrm address fffffa00h initial value 01h bit position bit name function 7 uartcae0 controls the operating clock. 0: stops clock supply to uart0. 1: supplies clock to uart0. cautions 1. when uartcae0 = 0 is set, uart0 is asynchronously reset note . 2. when uartcae0 = 0, uart0 is in a reset state. to operate uart0, first set uartcae0 = 1. 3. when the uartcae0 bit is changed from 1 to 0, all the registers of uart0 are initialized. when setting uartcae0 = 1 again, be sure to re-set the registers of uart0. the output of the txd0 pin goes high when tr ansmission is disabled, regardless of the setting of the uartcae0 bit. 6 txe0 enables/disables transmission. 0: disable transmission 1: enable transmission cautions 1. set the txe0 bit to 1 after setting the uartcae0 bit to 1 at startup. set the uartcae0 bit to 0 after setting the txe0 bit to 0 to stop. 2. to initialize the transmission unit, clear (0) the txe0 bit, and after letting 2 cycles of the base clock elapse, set (1) the txe0 bit again. if the txe0 bit is not set again, initialization may not be successful (for details about the base clock, refer to 10.2.6 (1) (a) base clock). note only the asis0, asif0, and rxb0 registers are reset. chapter 10 serial interface function user?s manual u14492ej4v1ud 408 (2/3) bit position bit name function 5 rxe0 enables/disables reception. 0: disable reception note 1: enable reception cautions 1. set the rxe0 bit to 1 after setting the uartcae0 bit to 1 at startup. set the uartcae0 bit to 0 after setting the rxe0 bit to 0 to stop. 2. to initialize the reception unit status, clear (0) the rxe0 bit, and after letting 2 cycles of the base clock elapse, set (1) the rxe0 bit again. if the rxe0 bit is not set again, initialization may not be successful (for details about the base clock, refer to 10.2.6 (1) (a) base clock). controls parity bit. ps1 ps0 transmit operation receive operation 0 0 don?t output parity bit receive with no parity 0 1 output 0 parity receive as 0 parity 1 0 output odd parity judge as odd parity 1 1 output even parity judge as even parity cautions 1. to overwrite the ps1 and ps0 bits, first clear (0) the txe0 and rxe0 bits. 2. if ?0 parity? is selected for reception, no parity judgment is performed. therefore, no error interrupt is generated because the pe bit of the asis0 register is not set. 4, 3 ps1, ps0 ? even parity if the transmit data contains an odd number of bits with the value ?1?, the parity bit is set (1). if it contains an even number of bits with the value ?1?, the parity bit is cleared (0). this controls the num ber of bits with the value ?1? contained in the transmit data and the parity bit so that it is an even number. during reception, the number of bits wi th the value ?1? contained in the receive data and the parity bit is counted, and if the number is odd, a parity error is generated. ? odd parity in contrast to even parity, odd parity c ontrols the number of bits with the value ?1? contained in the transmit data and the parity bit so that it is an odd number. during reception, the number of bits wi th the value ?1? contained in the receive data and the parity bit is counted, and if the number is even, a parity error is generated. note when reception is disabled, the reception shift r egister does not detect a start bit. no shift-in processing or transfer processing to the recepti on buffer register 0 (rxb0) is performed, and the contents of the rxb0 register are retained. when reception is enabled, the reception shift operat ion starts, synchronized with the detection of the start bit, and when the reception of one frame is comple ted, the contents of the reception shift register are transferred to the rxb0 register. a reception co mpletion interrupt (intsr0) is also generated in synchronization with the transfer to the rxb0 register. chapter 10 serial interface function user?s manual u14492ej4v1ud 409 (3/3) bit position bit name function 4, 3 ps1, ps0 ? 0 parity during transmission, the parity bit is cleared (0) regardless of the transmit data. during reception, no parity error is gener ated because no parity bit is checked. ? no parity no parity bit is added to transmit data. during reception, the receive data is considered to have no parity bit. no parity error is generated because there is no parity bit. 2 cl specifies character length of 1 frame of transmit/receive data. 0: 7 bits 1: 8 bits caution to overwrite the cl bit, first clear (0) the txe0 and rxe0 bits. 1 sl specifies stop bit length of transmit data. 0: 1 bit 1: 2 bits cautions 1. to overwrite the sl bit, first clear (0) the txe0 bit. 2. since reception is always done with a stop bit length of 1, the sl bit setting does not affect receive operations. 0 isrm enables/disables generation of reception completion interrupt requests when an error occurs. 0: generate a reception error interrupt request (intser0) as an interrupt when an error occurs. in this case, no reception completi on interrupt request (intsr0) is generated. 1: generate a reception completion interrupt request (intsr0) as an interrupt when an error occurs. in this case, no reception error inte rrupt request (intser0) is generated. caution to overwrite the isrm bit, first clear (0) the rxe0 bit. chapter 10 serial interface function user?s manual u14492ej4v1ud 410 (2) asynchronous serial interfa ce status register 0 (asis0) the asis0 register, which consists of 3-bit error flag s (pe, fe, and ove), indicates the error status when uart0 reception is completed. the status flag, which indicates a reception error, alwa ys indicates the status of t he error that occurred most recently. that is, if the same error occurred several times before the receive data was read, this flag would hold only the status of the error that occurred last. the asis0 register is cleared to 00h by a read oper ation. when a reception error occurs, the reception buffer register 0 (rxb0) should be read and the error fl ag should be cleared after the asis0 register is read. this register is read-only, in 8-bit units. caution when the uartcae0 bit or r xe0 bit of the asim0 register is set to 0, or when the asis0 register is read, the pe, fe, and ove bits of the asis0 register are cleared (0). 7 6 5 4 3 2 1 0 address initial value asis0 0 0 0 0 0 pe fe ove fffffa03h 00h bit position bit name function 2 pe this is a status flag that indicates a parity error. 0: when the asim0 register?s uartcae0 and rxe0 bits are both set to 0, or when the asis0 register has been read 1: when reception was completed, the receive data parity did not match the parity bit caution the operation of the pe bit differs according to the settings of the ps1 and ps0 bits of the asim0 register. 1 fe this is a status flag that indicates a framing error. 0: when the asim0 register?s uartcae0 and rxe0 bits are both set to 0, or when the asis0 register has been read 1: when reception was completed, no stop bit was detected caution for receive data stop bits, only the first bit is checked regardless of the stop bit length. 0 ove this is a status flag that indicates an overrun error. 0: when the asim0 register?s uartcae0 and rxe0 bits are both set to 0, or when the asis0 register has been read. 1: uart0 completed the next receive operation before reading the rxb0 receive data. caution when an overrun error occurs, the next receive data value is not written to the rxb0 register and the data is discarded. chapter 10 serial interface function user?s manual u14492ej4v1ud 411 (3) asynchronous serial interface tran smission status register 0 (asif0) the asif0 register, which consists of 2-bit stat us flags, indicates the status during transmission. by writing the next data to the txb0 register after data is transferred from the txb0 register to the transmission shift register, transmit operations can be performed continuously without suspension even during an interrupt interval. when transmission is performed continuously, data should be written after referencing the txbf0 bit of the asif0 register to prevent writing to the txb0 register by mistake. this register is read-only, in 8-bit or 1-bit units. 7 6 5 4 3 2 <1> <0> address initial value asif0 0 0 0 0 0 0 txbf0 txsf0 fffffa05h 00h bit position bit name function 1 txbf0 this is a transmission buffer data flag. 0: data to be transferred next to txb0 register does not exist (when the asim0 register?s uartcae0 or txe0 bit is 0, or when data has been transferred to the transmission shift register) 1: data to be transferred next exists in txb0 register (data exists in txb0 register when the txb0 register has been written to) caution when transmission is performed continuously, data should be written to the txb0 register after confirming that this flag is 0. if writing to txb0 register is performed when this flag is 1, transmit data cannot be guaranteed . 0 txsf0 this is a transmission shift register data flag. it indicates the transmission status of uart0. 0: initial status or a waiting trans mission (when the asim0 register?s uartcae0 or txe0 bit is set to 0, or when following transfer completion, the next data transfer from the txb0 register is not performed) 1: transmission in progress (when data has been transferred from the txb0 register) caution when the transmission unit is initialized, initialization should be executed after confirming that this flag is 0 following the occurrence of a transmission completion interrupt. if initialization is performed when this flag is 1, transmit data cannot be guaranteed. chapter 10 serial interface function user?s manual u14492ej4v1ud 412 (4) reception buffer register 0 (rxb0) the rxb0 register is an 8-bit buffer register for storin g parallel data that had been converted by the reception shift register. when reception is enabled (rxe0 bit = 1 in the asim0 register), receive data is transferred from the reception shift register to the rxb0 register, synchroni zed with the completion of the shift-in processing of one frame. also, a reception completion interrupt reques t (intsr0) is generated by the transfer to the rxb0 register. for information about the timing fo r generating this interrupt request, refer to 10.2.5 (4) reception operation . if reception is disabled (rxe0 bit = 0 in the asim0 regi ster), the contents of the r xb0 register are retained, and no processing is performed for transferring data to the rxb0 register even when the shift-in processing of one frame is completed. also, no rec eption completion interrupt is generated. when 7 bits is specified for the data length, bits 6 to 0 of the rxb0 register are transferred for the receive data and the msb (bit 7) is always 0. however, if an overrun error (ove) o ccurs, the receive data at that time is not transferred to the rxb0 register. except when a reset is input, the rxb0 register bec omes ffh even when uartcae0 bit = 0 in the asim0 register. this register is read-only, in 8-bit units. 7 6 5 4 3 2 1 0 address initial value rxb0 rxb7 rxb6 rxb5 rxb4 rxb3 rxb2 rxb1 rxb0 fffffa02h ffh bit position bit name function 7 to 0 rxb7 to rxb0 stores receive data. 0 can be read for rxb7 when 7-bit or character data is received. chapter 10 serial interface function user?s manual u14492ej4v1ud 413 (5) transmission buffer register 0 (txb0) the txb0 register is an 8-bit buffe r register for setting transmit data. when transmission is enabled (txe0 bit = 1 in the asim0 register), the transmit operation is started by writing data to txb0 register. when transmission is disabled (txe0 bit = 0 in the asim0 register), even if data is written to txb0 register, the value is ignored. the txb0 register data is transferred to the trans mission shift register, and a transmission completion interrupt request (intst0) is gener ated, synchronized with the completion of the transmission of one frame from the transmission shift register. for information about the timing for generating this interrupt request, refer to 10.2.5 (2) transmission operation . when txbf0 bit = 1 in the asif0 register, writ ing must not be performed to txb0 register. this register can be read/written in 8-bit units. 7 6 5 4 3 2 1 0 address initial value txb0 txb7 txb6 txb5 txb4 txb3 txb2 txb1 txb0 fffffa04h ffh bit position bit name function 7 to 0 txb7 to txb0 writes transmit data. chapter 10 serial interface function user?s manual u14492ej4v1ud 414 10.2.4 interrupt requests the following three types of interrupt requests are generated from uart0. ? reception completion interrupt (intsr0) ? transmission completion interrupt (intst0) ? reception error interrupt (intser0) the default priorities among these thre e types of interrupt requests is, from high to low, reception completion interrupt, transmission completion inte rrupt, and reception error interrupt. table 10-1. generated inte rrupts and default priorities interrupt priority reception completion 1 transmission completion 2 reception error 3 (1) reception completion interrupt (intsr0) when reception is enabled, a reception completion in terrupt is generated when dat a is shifted in to the reception shift register and transferred to the reception buffer register 0 (rxb0). a reception completion interrupt request can be generated in place of a reception error interrupt according to the isrm bit of the asim0 register ev en when a reception error has occurred. when reception is disabled, no reception completion interrupt is generated. (2) transmission completion interrupt (intst0) a transmission completion interrupt is generated when one frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmission shift register. (3) reception error interrupt (intser0) when reception is enabled, a recepti on error interrupt is generated accordi ng to the logical or of the three types of reception errors explained for the asis0 regist er. whether a reception error interrupt (intser0) or a reception completion interrupt (intsr0) is generated when an error occurs can be specified according to the isrm bit of the asim0 register. when reception is disabled, no rec eption error interrupt is generated. chapter 10 serial interface function user?s manual u14492ej4v1ud 415 10.2.5 operation (1) data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consis ts of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 10-2. the character bit length within one data frame, the ty pe of parity, and the st op bit length are specified according to the asynchronous serial interface mode register 0 (asim0). also, data is transferred with lsb first. figure 10-2. asynchronous serial interface transmit/receive data format 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit 1 bit ? character bits 7 bits or 8 bits ? parity bit even parity, odd parity, 0 parity, or no parity ? stop bits 1 bit or 2 bits chapter 10 serial interface function user?s manual u14492ej4v1ud 416 (2) transmission operation when uartcae0 bit is set to 1 in the asim0 regist er, a high level is output from the txd0 pin. then, when txe0 bit is set to 1 in the asim0 register, transmission is enabled, and the transmit operation is started by writing transmit data to transmission buffer register 0 (txb0). (a) transmission enabled state this state is set by the txe0 bit in the asim0 register. ? txe0 = 1: transmission enabled state ? txe0 = 0: transmission disabled state since uart0 does not have a cts (transmission enab led signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (b) transmission operation start in transmission enabled state, a transmission operatio n is started by writing transmit data to transmission buffer register 0 (txb0). when a transmit operation is started, the data in txb0 is transferred to transmission shift register. then, the transmission shift register outputs data to the txd0 pin (the transmit data is transferred sequentially starting with the start bit). the start bit, parity bit, and stop bits are added automatically. (c) transmission interrupt request when the transmission shift register becomes em pty, a transmission completion interrupt request (intst0) is generated. the timi ng for generating the intst0 interrupt differs according to the specification of the stop bit length. the intst0 interrupt is generated at the same time t hat the last stop bit is output. if the data to be transmitted next has not been written to the txb0 regi ster, the transmit operation is suspended. caution normally, when the transmission shift register becomes empty, a transmission completion interrupt (intst0) is generate d. however, no transmission completion interrupt (intst0) is generate d if the transmission shift re gister becomes empty due to the input of a reset. chapter 10 serial interface function user?s manual u14492ej4v1ud 417 figure 10-3. asynchronous serial interf ace transmission comple tion interrupt timing start stop d0 d1 d2 d6 d7 parity parity txd0 (output) intst0 (output) start d0 d1 d2 d6 d7 txd0 (output) intst0 (output) (a) stop bit length: 1 (b) stop bit length: 2 stop chapter 10 serial interface function user?s manual u14492ej4v1ud 418 (3) continuous transmission operation uart0 can write the next tran smit data to the txb0 register at the ti ming that the transmission shift register starts the shift operation. this enables an efficient transmission rate to be realized by continuously transmitting data even during the intst0 interrupt se rvice after the transmission of one data frame. in addition, reading the txsf0 bit of t he asif0 register after the occurrence of a transmission completion interrupt enables the txb0 register to be efficiently wr itten twice (2 bytes) without waiting for the transmission of 1 data frame. when continuous transmission is performed, data should be written after referencing the asif0 register to confirm the transmission status and whether or not data can be written to the txb0 register. caution the values of the txbf0 and txsf0 bits of the asif0 register change from 10 11 01 in continuous transmission. therefore, do not confirm the status based on the combination of the txbf0 and txsf0 bits. read only the txbf0 bit during continuous transmission. txbf0 whether or not writing to txb0 register is enabled 0 writing is enabled 1 writing is not enabled caution when transmission is perfo rmed continuously, write the first tr ansmit data (first byte) to the txb0 register and confirm that the txbf0 bit is 0, and then write the next transmit data (second byte) to txb0 register. if writing to the txb0 register is performed when the txbf0 bit is 1, transmit data cannot be guaranteed. while transmission is being performed continuously, whet her writing to the txb0 register later is enabled can be judged by confirming the txsf0 bit after the occurrence of a transmission completion interrupt. txsf0 transmission status 0 transmission is completed 1 under transmission cautions 1. when initializing the transmission uni t when continuous tran smission is completed, confirm that the txsf0 bit is 0 after the occurrence of the transmission completion interrupt, and then execute initialization. if initialization is perf ormed when the txsf0 bit is 1, transmit data cannot be guaranteed. 2. while transmission is bein g performed continuously, an o verrun error may occur if the next transmission is comple ted before the intst0 inte rrupt servicing following the transmission of 1 data frame is executed. an overrun error can be detected by embedding a program that can count the num ber of transmit da ta and referencing txsf0 bit. chapter 10 serial interface function user?s manual u14492ej4v1ud 419 figure 10-4. continuous transmission processing flow set registers interrupt occurrence wait for interrupt required number of transfers performed? write transmit data to txb0 register write transmit data to txb0 register when reading asif0 register, txbf0 = 0? when reading asif0 register, txsf0 = 1? when reading asif0 register, txsf0 = 0? no no no no yes yes yes yes end of transmission processing write 2nd byte of the transmit data to txb0 register chapter 10 serial interface function user?s manual u14492ej4v1ud 420 (a) starting procedure the procedure to start continuous transmission is shown below. figure 10-5. continuous tr ansmission starting procedure txd0 (output) data (1) data (2) <5> <1> <2> <4> intst0 (output) txb0 register ffh ffh data (1) data (2) data (3) data (1) data (2) data (3) <3> asif0 register (txbf0, txsf0 bits) 00 11 note 11 01 01 11 01 11 txs0 register start bit stop bit stop bit start bit 10 note refer to 10.2.7 precautions (2) . asif0 register transmission starting procedure internal operation txbf0 txsf0 ? set transmission mode <1> start transmission unit 0 0 ? write data (1) 1 0 <2> generate start bit ? read asif0 register (confirm that txbf0 bit = 0) start data (1) transmission 1 0 0 0 1 note 1 note 1 1 ? write data (2) < chapter 10 serial interface function user?s manual u14492ej4v1ud 421 (b) ending procedure the procedure for ending continuous transmission is shown below. figure 10-6. continuous transmission end procedure txd0 (output) data (m ? 1) data (m) <11> <7> <6> <8> <10> intst0 (output) txb0 register data (m ? 1) data (m ? 1) data (m) ffh data (m) <9> asif0 register (txbf0, txsf0 bits) uartcae0 bit or txe0 bit 11 01 11 01 00 transmit shift register start bit start bit stop bit stop bit asif0 register transmission end procedure internal operation txbf0 txsf0 <6> transmission of data (m ? 2) is in progress 1 1 <7> intst0 interrupt occurs ? read asif0 register (confirm that txbf0 bit = 0) 0 0 1 1 ? write data (m) <8> generate start bit start data (m ? 1) transmission < chapter 10 serial interface function user?s manual u14492ej4v1ud 422 (4) reception operation an awaiting reception state is set by setting uartcae0 bit to 1 in the asim0 register and then setting rxe0 bit to 1 in the asim0 register. to start the receive operation, start sampling at the falling edge when the falling of the rxd0 pin is detected. if the rxd0 pin is low level at a start bit sampling point, the start bit is recognized. when the receive operation begins, serial data is stored sequentially in the reception shift register according to the baud rate that was set. a reception completion interrupt (intsr0) is generated each time the reception of one frame of data is complete d. normally, the receive data is transferred from the reception buffer register 0 (rxb0) to memory by this interrupt servicing. (a) reception enabled state the receive operation is set to rec eption enabled state by setting the rxe0 bit in the asim0 register to 1. ? rxe0 bit = 1: reception enabled state ? rxe0 bit = 0: reception disabled state in reception disabled state, the rece ption hardware stands by in the initial state. at this time, the contents of the reception buffer register 0 (rxb0) are retain ed, and no reception completion interrupt or reception error interrupt is generated. (b) start of reception operation a reception operation is started by the detection of a start bit. the rxd0 pin is sampled according to the seri al clock from the baud rate generator 0 (brg0). (c) reception completion interrupt when rxe0 bit = 1 in the asim0 register and the re ception of one frame of data is completed (the stop bit is detected), a reception completion interrupt (intsr0) is generated and t he receive data within the reception shift register is transferred to rxb0 at the same time. also, if an overrun error (ove) occurs, the receive data at that time is not transferred to the reception buffer register 0 (rxb0), and either a reception co mpletion interrupt (intsr0) or a reception error interrupt (intser0) is generated according to the isrm bit setting in the asim0 register. even if a parity error (pe) or framing error (fe) occu rs during a reception operat ion, the receive operation continues until stop bit is received, and after recept ion is completed, either a reception completion interrupt (intsr0) or a reception error interrupt (intser0) is generated (t he receive data within the reception shift register is transferred to rxb0) acco rding to the isrm bit setting in the asim0 register. if the rxe0 bit is reset (0) during a receive operation, the receive operation is immediately stopped. the contents of the reception buffer register 0 (rxb0) and of the asynchronous serial interface status register (asis0) at this time do not change, and no reception completion interrupt (intsr0) or reception error interrupt (intser0) is generated. no reception completion interrupt is generated when rxe0 bit = 0 (reception is disabled). chapter 10 serial interface function user?s manual u14492ej4v1ud 423 figure 10-7. asynchronous serial interf ace reception completion interrupt timing start d0 d1 d2 d6 d7 rxd0 (input) intsr0 (output) rxb0 register parity stop cautions 1. even if a reception error occurs, be su re to read reception buffer register 0 (rxb0). if rxb0 is not read, an overrun error will occur at the next data reception, and the reception error state will continue indefinitely. 2. reception is always performed wit h the stop bit length set to 1. a second stop bit is ignored. (5) reception error the three types of error that can occur during a receive operation are a parity error, framing error, or overrun error. the data reception result is that the various flags of the asis0 register are set (1), and a reception error interrupt (intser0) or a reception completion in terrupt (intsr0) is generated at the same time. the isrm bit of the asim0 register specifie s whether intser0 or intsr0 is generated. the type of error that occurred during reception c an be detected by reading th e contents of the asis0 register during the intser0 or intsr0 interrupt servicing. the contents of the asis0 r egister are reset (0) by reading the asis0 register. table 10-2. reception error causes error flag reception error cause pe parity error the parity specificat ion during transmission did not match the parity of the reception data fe framing error no stop bit was detected ove overrun error the reception of the next data was completed before data was read from the reception buffer register 0 (rxb0) chapter 10 serial interface function user?s manual u14492ej4v1ud 424 (a) separation of rece ption error interrupt a reception error interrupt can be separated from the intsr0 interrupt and generated as an intser0 interrupt by clearing the isrm bit of the asim0 register to 0. figure 10-8. when reception error interrupt is se parated from in tsr0 interrupt (isrm bit = 0) (a) no error occurs during reception (b) an e rror occurs during reception intsr0 (output) (reception completion interrupt) intser0 (output) (reception error interrupt) intsr0 (output) (reception completion interrupt) intser0 (output) (reception error interrupt) intsr0 does not occur figure 10-9. when reception error interrupt is included in intsr0 in terrupt (isrm bit = 1) (a) no error occurs during reception (b) an erro r occurs during reception intsr0 (output) (reception completion interrupt) intser0 (output) (reception error interrupt) intsr0 (output) (reception completion interrupt) intser0 (output) (reception error interrupt) intser0 does not occur chapter 10 serial interface function user?s manual u14492ej4v1ud 425 (6) parity types and co rresponding operation a parity bit is used to detect a bit error in communication data. normally, the same type of parity bit is used at the transmission and reception sides. (a) even parity (i) during transmission the parity bit is controlled so t hat the number of bits with the value ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1? within the transmit data is even: 0 (ii) during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (b) odd parity (i) during transmission in contrast to even parity, the parity bit is contro lled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1? within the transmit data is even: 1 (ii) during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (d) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no parity bit. since there is no parity bit, no parity error is generated. chapter 10 serial interface function user?s manual u14492ej4v1ud 426 (7) receive data noise filter the rxd0 signal is sampled at the rising edge of the prescaler output base clock. if the same sampling value is obtained twice, the match detector output c hanges, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see figure 10-11 ). refer to 10.2.6 (1) (a) base clock regarding the base clock. also, since the circuit is configured as shown in figur e 10-10, internal processing during a receive operation is delayed by up to 2 clocks accord ing to the external signal status. figure 10-10. noise filter circuit rxd0 q base clock in ld_en q in internal signal a internal signal b match detector figure 10-11. timing of rx d0 signal judged as noise internal signal a base clock rxd0 (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match chapter 10 serial interface function user?s manual u14492ej4v1ud 427 10.2.6 dedicated baud ra te generator 0 (brg0) a dedicated baud rate generator, which consists of a s ource clock selector and an 8-bit programmable counter, generates serial clocks during transmi ssion/reception at uart0. the dedicated baud rate generator output can be selected as the serial clock for each channel. separate 8-bit counters exist fo r transmission and for reception. (1) baud rate generator 0 (brg0) configuration figure 10-12. baud rate genera tor 0 (brg0) configuration f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 f xx /2048 base clock (f clk ) selector uartcae0 8-bit counter match detector baud rate brgc0: mdl7 to mdl0 1/2 uartcae0 and txe0 (or rxe0) cksr0: tps3 to tps0 f xx remark f xx : internal system clock (a) base clock when uartcae0 bit = 1 in the asim0 register, the clock selected according to the tps3 to tps0 bits of the cksr0 register is supplied to the transmission/rec eption unit. this clock is called the base clock, and its frequency is referred to as f clk . when uartcae0 bit = 0, the base clock is fixed at low level. chapter 10 serial interface function user?s manual u14492ej4v1ud 428 (2) serial clock generation a serial clock can be generated according to the settings of the cksr0 and brgc0 registers. the base clock to the 8-bit counter is selected accordi ng to the tps3 to tps0 bits of the cksr0 register. the 8-bit counter divisor value can be set according to the mdl7 to mdl0 bits of the brgc0 register. (a) clock selection register 0 (cksr0) the cksr0 register is an 8-bit register for selecting th e base clock according to the tps3 to tps0 bits. the clock selected by the tps3 to tps0 bits bec omes the base clock of the transmission/reception module. its frequency is referred to as f clk . this register can be read/written in 8-bit units. cautions 1. the maximum allowabl e frequency of the base clock (f clk ) is 25 mhz. therefore, when the system clock?s freque ncy is 50 mhz, bits tps3 to tps0 cannot be set to 0000b. to use 50 mhz, set the tps3 to tps0 bits to a value other than 0000b, and set the uartcae0 bit of the asim0 register to 1. 2. if the tps3 to tps0 bits are to be overwritten, the uartcae0 bit of the asim0 register should be set to 0 first. 7 6 5 4 3 2 1 0 address initial value cksr0 0 0 0 0 tps3 tps2 tps1 tps0 fffffa06h 00h bit position bit name function specifies the base clock. tps3 tps2 tps1 tps0 base clock (f clk ) 0 0 0 0 f xx 0 0 0 1 f xx /2 0 0 1 0 f xx /4 0 0 1 1 f xx /8 0 1 0 0 f xx /16 0 1 0 1 f xx /32 0 1 1 0 f xx /64 0 1 1 1 f xx /128 1 0 0 0 f xx /256 1 0 0 1 f xx /512 1 0 1 0 f xx /1024 1 0 1 1 f xx /2048 1 1 arbitrary arbitrary setting prohibited 3 to 0 tps3 to tps0 remark f xx : internal system clock chapter 10 serial interface function user?s manual u14492ej4v1ud 429 (b) baud rate generator c ontrol register 0 (brgc0) the brgc0 register is an 8-bit regist er that controls the baud rate (serial transfer speed) of uart0. this register can be read/written in 8-bit units. caution if the mdl7 to mdl0 bits are to be over written, the txe0 bit and rxe0 bit of the asim0 register should be set to 0 first. 7 6 5 4 3 2 1 0 address initial value brgc0 mdl7 mdl6 mdl5 mdl4 mdl3 mdl2 mdl1 mdl0 fffffa07h ffh bit position bit name function specifies the 8-bit counter?s division value. mdl7 mdl6 mdl5 mdl4 mdl3 mdl2 mdl1 mdl0 set value (k) serial clock 0 0 0 0 0 x x x ? setting prohibited 0 0 0 0 1 0 0 0 8 f clk /8 0 0 0 0 1 0 0 1 9 f clk /9 0 0 0 0 1 0 1 0 10 f clk /10 1 1 1 1 1 0 1 0 250 f clk /250 1 1 1 1 1 0 1 1 251 f clk /251 1 1 1 1 1 1 0 0 252 f clk /252 1 1 1 1 1 1 0 1 253 f clk /253 1 1 1 1 1 1 1 0 254 f clk /254 1 1 1 1 1 1 1 1 255 f clk /255 7 to 0 mdl7 to mdl0 remarks 1. f clk : frequency [hz] of base clock selected according to tps3 to tps0 bits of cksr0 register 2. k: value set according to mdl7 to mdl0 bits (k = 8, 9, 10, ..., 255) 3. the baud rate is the output clock fo r the 8-bit counter divided by 2 4. x: don?t care ? ? ? ? ? ? ? ? ? ? chapter 10 serial interface function user?s manual u14492ej4v1ud 430 (c) baud rate the baud rate is the value obtained according to the following formula. baud rate = [bps] f clk = frequency [hz] of base clock selected according to tps3 to tps0 bits of cksr0 register k = value set according to mdl7 to mdl0 bits of brgc0 register (k = 8, 9, 10, ..., 255) (d) baud rate error the baud rate error is obtained according to the following formula. [%] 100 1 rate) baud (normal rate baud desired error) with rate (baud rate baud actual (%) error ? ? ? ? ? ? ? ? ? = cautions 1. make sure that the baud rate erro r during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error duri ng reception is within th e allowable baud rate range during reception, whic h is described in (4) allo wable baud rate range during reception. example: base clock frequency (f clk ) = 20 mhz = 20,000,000 hz settings of mdl7 to mdl0 bits in brgc0 register = 01000001b (k = 65) target baud rate = 153,600 bps baud rate = 20m/(2 65) = 20000000/(2 65) = 153,846 [bps] error = (153846/153600 ? 1) 100 = 0.160 [%] f clk 2 k chapter 10 serial interface function user?s manual u14492ej4v1ud 431 (3) baud rate setting example table 10-3. baud rate generator setting data f xx = 50 mhz f xx = 40 mhz f xx = 33 mhz f xx = 10 mhz baud rate (bps) f clk k err f clk k err f clk k err f clk k err 300 f xx /2 9 163 0.15 f xx /2 10 65 0.16 f xx /2 8 215 ?0.07 f xx /2 7 130 0.16 600 f xx /2 8 163 0.15 f xx /2 9 65 0.16 f xx /2 7 215 ?0.07 f xx /2 6 130 0.16 1200 f xx /2 7 163 0.15 f xx /2 8 65 0.16 f xx /2 6 215 ?0.07 f xx /2 5 130 0.16 2400 f xx /2 6 163 0.15 f xx /2 7 65 0.16 f xx /2 5 215 ?0.07 f xx /2 4 130 0.16 4800 f xx /2 5 163 0.15 f xx /2 6 65 0.16 f xx /2 4 215 ?0.07 f xx /2 3 130 0.16 9600 f xx /2 4 163 0.15 f xx /2 5 65 0.16 f xx /2 3 215 ?0.07 f xx /2 2 130 0.16 19200 f xx /2 3 163 0.15 f xx /2 4 80 0.16 f xx /2 2 215 ?0.07 f xx /2 1 130 0.16 31250 f xx /2 3 100 0 f xx /2 3 65 0 f xx /2 2 132 0 f xx /2 1 80 0 38400 f xx /2 2 163 0.15 f xx /2 3 65 0.16 f xx /2 1 215 ?0.07 f xx /2 0 130 0.16 76800 f xx /2 2 81 0.47 f xx /2 2 65 0.16 f xx /2 1 107 0.39 f xx /2 0 65 0.16 153600 f xx /2 1 81 0.47 f xx /2 1 65 0.16 f xx /2 1 54 ?0.54 f xx /2 0 33 ?1.36 312500 f xx /2 1 40 0 f xx /2 1 32 0 f xx /2 1 26 1.54 f xx /2 0 16 0 625000 f xx /2 1 20 0 f xx /2 1 16 0 f xx /2 1 13 ? 1.52 f xx /2 0 8 0 1250000 f xx /2 1 10 0 f xx /2 1 8 0 f xx /2 1 8 ? 17.5 ? ? ? 1562500 f xx /2 1 8 0 f xx /2 1 8 ? 18.6 ? ? ? ? ? ? caution the maximum allowable frequency of the base clock (f clk ) is 25 mhz. remark f xx : internal system clock frequency f clk : base clock frequency k: setting values of mdl7 to mdl0 bits in brgc0 register err: baud rate error [%] chapter 10 serial interface function user?s manual u14492ej4v1ud 432 (4) allowable baud rate range during reception the degree to which a discrepancy from the transmission destination?s baud rate is allowed during reception is shown below. caution the equations described be low should be used to set the baud rate error during reception so that it always is withi n the allowable error range. figure 10-13. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uart0 transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 10-13, after the start bit is detect ed, the receive data latch timing is determined according to the counter that was set by the brgc 0 register. if all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. applying this to 11-bit reception is, theoretically, as follows. fl = (brate) ?1 brate: uart0 baud rate k: brgc0 register setting value fl: 1-bit data length when the latch timing margin is made 2 base clocks, the minimum allowable transfer rate (flmin) is as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 min fl + = ? ? = chapter 10 serial interface function user?s manual u14492ej4v1ud 433 therefore, the transfer destination?s maximum baud ra te (brmax) that can be received is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum allowable transfer rate (flmax) can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 max fl 11 10 ? = + ? = 11 fl k 20 2 k 21 max fl ? = therefore, the transfer destination?s minimum baud ra te (brmin) that can be received is as follows. brmin = (flmax/11) ? 1 = brate the allowable baud rate error of uart0 and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 10-4. maximum and mini mum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% ?3.61% 20 +4.26% ?4.31% 50 +4.56% ?4.58% 100 +4.66% ?4.67% 255 +4.72% ?4.73% remarks 1. the reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). the higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: brgc0 setting value 22k 21k + 2 20k 21k ? 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 434 (5) transfer rate durin g continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of base clock longer than normal. however, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 10-14. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bit length by flstp, and the base clock frequency by f clk yields the following equation. flstp = fl + 2/f clk therefore, the transfer rate during co ntinuous transmission is as follows. transfer rate = 11 fl = 2/f clk 10.2.7 precautions precautions to be observed when using uart0 are shown below. (1) when the supply of clocks to uart0 is stopped (for example, idle or software stop mode), operation stops with each register retaining the value it had immediat ely before the supply of clocks was stopped. the txd0 pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. however, operation is not guaranteed a fter the supply of clocks is restart ed. therefore, after the supply of clocks is restarted, the circuits should be initialized by setting uartcae0 bi t = 0, rxe0 bit = 0, and txe0 bit = 0 in the asim0 register. (2) uart0 has a 2-stage buffer configuration consisting of transmission buffer register 0 (txb0) and the transmission shift register, and has status flags (txbf0 and txsf0 bits of asif0 register) that indicate the status of each buffer. if the txbf0 and txsf0 bits are read in continuous transmission simultaneously, the values change from 10 11 01. thus, judge by using only the t xbf0 bit during continuous transmission. chapter 10 serial interface function user?s manual u14492ej4v1ud 435 10.3 asynchronous serial interfaces 1, 2 (uart1, uart2) 10.3.1 features ? clocked (synchronous) mode/asynchronous mode can be selected ? operation clock synchronous mode: baud rate generator/external clock selectable asynchronous mode: baud rate generator ? transfer rate 600 bps to 153,600 bps (in asynchronous mode, f xx = 50 mhz) 4,800 bps to 1,000,000 bps (in synchronous mode) ? full-duplex communications (lsb first) on-chip reception buffer register n (rxbn) ? three-pin configuration txdn: transmit data output pin rxdn: receive data input pin asckn: synchronous serial clock i/o ? reception error detection function ? parity error ? framing error ? overrun error ? interrupt sources: 2 types ? reception completion interrupt (intsrn): interrupt is generated when receive data is transferred from the shift register to the reception bu ffer register n (r xbn) after serial transfer is completed during a reception enabled state. ? transmission completion interrupt (intstn): interrupt is generated when the serial transmission of trans- mit data (8/7 bits) from the shift register is completed. ? the character length of transmit/receive data is specified with the asimn0 r egister (extension bits are specified with the asimn1 register) ? character length: 7 or 8 bits 9 bits (when extension bit is added) ? parity functions: odd, even, 0, or no parity ? transmission stop bits: 1 or 2 bits ? communication mode: 1-frame transfer or 2-frame continuous transfer enabled ? on-chip dedicated baud rate generator remarks 1. n = 1, 2 2. f xx : internal system clock chapter 10 serial interface function user?s manual u14492ej4v1ud 436 10.3.2 configuration uart1 and uart2 are controlled by asynchronous serial interface mode registers 10, 11, 20, and 21 (asim10, asim11, asim20, asim21) and asynchronous serial interface status registers 1 and 2 (asis1, asis2). receive data is held in the reception buffer registers (rxb1, rxbl1, r xb2, rxbl2), and transmit data is held in the transmission shift registers (txs1, txsl1, txs2, txsl2). figure 10-15 shows the configuration of asynchro nous serial interfaces 1 and 2 (uart1, uart2). (1) asynchronous serial interface m ode registers 10, 11, 20, 21 (asim10, asim11, asim20, asim21) the asimn0 and asimn1 registers are 8- bit registers that specify the oper ation of the asynchronous serial interface (n = 1, 2). (2) asynchronous serial interface status registers 1, 2 (asis1, asis2) the asis1 and asis2 registers consist of a transmission status flag (sotn), recept ion status flag (sirn), a bit (rb8) that indicates the 9th bit when extension bit addition is enabled, and 3-bit error flags (pen, fen, oven) that indicate the error status at reception end (n = 1, 2). (3) reception control parity check the receive operation is controlled according to t he contents set in the asim n0 and asimn1 registers. a check for parity errors is also performed during rece ive operation, and if an e rror is detected, a value corresponding to the error contents is se t in the asis1 and asis2 registers. (4) 2-frame continuous reception buffer registers (r xb1, rxb2)/reception bu ffer registers (rxbl1, rxbl2) rxbn is a 16-bit (during 2-frame cont inuous reception, 9-bit extension da ta reception) buffer register that holds receive data. during 7, 8 bit/charac ter reception, 0 is stored in the msb. for 16-bit access to this register, specify rxb1, rxb2, and for access to the lower 8 bits, specify rxbl1, rxbl2. in the reception enabled state, receiv e data is transferred from the reception shift register to the reception buffer in synchronization with the completion of shift-in processing of one frame. a reception completion interrupt request (intsrn) is generated upon transfer to the reception buffer (when 2- frame continuous reception is specified, reception buffer tr ansfer of the second frame). (5) 2-frame continuous transmission shift registers (txs1, txs2)/tran smission shift registers (txsl1, txsl2) txsn is a 9-bit/2-frame continuous transmission processi ng shift register. transmission is started by writing data to this register. a transmission completion interrupt request (intstn) is generat ed in synchronization with the end of transmission of 1 frame or 2 frames including the txsn data. for 16-bit access to this register, specify txs1, txs2 , and for access to the lower 8 bits, specify txsl1, txsl2. (6) addition of transmission control parity a transmission operation is controlled by adding a start bit, par ity bit, or stop bit to the data that is written to the txsn or txsln register, according to the contents set in the asim n0, asimn1 registers. (7) selector the selector selects the serial clock source. chapter 10 serial interface function user?s manual u14492ej4v1ud 437 figure 10-15. block diagram of a synchronous serial interfaces 1, 2 transmission shift registers (txsn, txsln) asynchronous serial interface mode registers n0, n1 (asimn0, asimn1) asynchronous serial interface status register n (asisn) transmission control parity addition reception buffers n, ln (rxbn, rxbln) pen fen oven reception shift register rxdn txdn mod bit asckn reception control parity check selector selector selector intstn intsrn sotn flag brgn sirn flag internal bus 1 16 1 16 remark n = 1, 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 438 10.3.3 control registers (1) asynchronous serial inte rface mode registers 10, 20 (asim10, asim20) the asimn0 register is an 8-bit regist er that controls the uart1, uart 2 transfer operation (n = 1, 2). this register can be read/written in 8-bit or 1-bit units. cautions 1. if a bit other than the rxen bit of the asimn0 register is changed during uartn transmission or reception, the uartn operat ion cannot be guaranteed (n = 1, 2). 2. set a bit other than the rxen bit of th e asimn0 register when the uartn operation is stopped (when rxen bit = 0 and transmission is completed). cha nge the port 3 mode control register (pmc3) after setting the co mmunication mode for bits other than the rxen bit of the asimn0 register. 3. in the case of serial clock output in the clocked (synchr onous) mode, ensure that nodes do not output to one another causing conflicts. chapter 10 serial interface function user?s manual u14492ej4v1ud 439 7 1 asim10 <6> rxe1 5 ps1 4 ps0 3 cl 2 sl 1 0 0 scls address fffffa28h initial value 81h 7 1 asim20 <6> rxe2 5 ps1 4 ps0 3 cl 2 sl 1 0 0 scls address fffffa48h initial value 81h bit position bit name function 6 rxen enables/disables reception. 0: disable reception 1: enable reception specifies parity bit length. ps1 ps0 operation 0 0 no parity, extension bit operation 0 1 0 parity transmit side transmission with parity bit = 0 receive side no parity error generated during reception 1 0 odd parity 5, 4 ps1, ps0 1 1 even parity 3 cl specifies character length of tr ansmit/receive data (1 frame). 0: 7 bits 1: 8 bits 2 sl specifies stop bit length of transmit data. 0: 1 bit 1: 2 bits specifies serial clock source. operation scls in asynchronous mode in synchronous mode 0 external clock input 1 internal baud rate generator 0 scls remark n = 1, 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 440 (2) asynchronous serial inte rface mode registers 11, 21 (asim11, asim21) the asimn1 register is an 8-bit register that controls the uart1 and uart2 transfer modes. this register can be read/written in 8-bit or 1-bit units. 7 0 asim11 6 0 5 0 4 0 3 mod 2 umst 1 umsr 0 ebs address fffffa2ah initial value 00h 7 0 asim21 6 0 5 0 4 0 3 mod 2 umst 1 umsr 0 ebs address fffffa4ah initial value 00h bit position bit name function 3 mod specifies operation mode (asynchronous/synchronous mode). 0: asynchronous mode 1: synchronous mode 2 umst specifies number of conti nuous frame transmissions. 0: 1-frame data transmission 1: 2-frame continuous data transmission 1 umsr specifies number of cont inuous frame receptions. 0: 1-frame data reception 1: 2-frame continuous data reception 0 ebs specifies extension bit operation for tr ansmit/receive data when no parity is specified (ps0 = ps1 = 0). 0: disable extension bit addition 1: enable extension bit addition when the extension bit is specified, 1 dat a bit is added on top of the 8 bits of transmit/receive data, enabling 9-bit data communication. extension bit specification is valid only w hen no parity (asimn0 register?s ps0 bit = ps1 bit = 0) and 1-frame data transmission (umst bit = 0) are specified. when 0 parity, odd parity, or even parity are sp ecified, or when 2-frame continuous data transmission (umst bit = 1) is specified, the ebs bit setting becomes invalid and extension bit addition is not performed. extension bit addition (ebs bit = 1) and 2-frame continuous data reception (umsr bit = 1) cannot be set simultaneously. chapter 10 serial interface function user?s manual u14492ej4v1ud 441 (3) asynchronous serial interface status registers 1, 2 (asis1, asis2) the asisn register is a register that is configured of a uartn transmission status flag (sotn), reception status flag (sirn), a bit (rb8) indicating the 9th bit when extension bit addition is enabled, and 3-bit error flags (pen, fen, oven) that indicate the er ror status at reception end (n = 1, 2). the status flag that indicates reception errors always indicates the most re cent error status. in other words, if the same error occurs several times before receive data is read, this flag holds only the status of the error that occurred last. each time the asisn register is read after a receive completion interrupt (intsrn), read the reception buffer (rxbn or rxbln). the error flag is cleared when the reception buffer (rxbn or rxbln) is read. also, clear the error flag by reading the reception bu ffer (rxbn or rxbln) when a reception error occurs. this register is read-only, in 8-bit or 1-bit units. chapter 10 serial interface function user?s manual u14492ej4v1ud 442 <7> sot1 asis1 <6> sir1 5 0 4 rb8 3 0 <2> pe1 <1> fe1 <0> ove1 address fffffa2ch initial value 00h <7> sot2 asis2 <6> sir2 5 0 4 rb8 3 0 <2> pe2 <1> fe2 <0> ove2 address fffffa4ch initial value 00h bit position bit name function 7 sotn status flag indicating transmission status 0: transmission end timing (when intstn is generated) 1: indicates transmission status note note the transmission status is the stat us until the specified number of stop bits has been transmitted following writ e operation to the transmit register. during 2-frame continuous tr ansmission, this status is until the stop bit of the 2nd frame has been transmitted. 6 sirn status flag indicating reception status 0: reception end timing (when intsrn is generated) 1: indicates reception status note note the reception status is the status until stop bit detection from the start bit detection timing. 4 rb8 indicates contents of receive data extensi on bit (1 bit) when 9-bit extended format is specified (ebs bit of asimn1 register = 1). 2 pen status flag indicating parity error 0: processing to read data from reception buffer 1: when transmit parity and receive parity don?t match caution no parity error is generated if no parity is specified or 0 parity is specified with the ps1, ps0 bits of the asimn0 register. 1 fen status flag indicating framing error 0: processing to read data from reception buffer 1: when stop bit is not detected 0 oven status flag indicating overrun error 0: processing to read data from reception buffer 1: when uartn has completed next reception processing prior to loading receive data from reception buffer since the contents of the reception shift register are transferred to the reception buffer (rxbn, rxbln) every time 1 frame is received, the following receive data is overwritten to the reception buffer (rxbn, rxbln) and the previous receive data is discarded. remark n = 1, 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 443 (4) 2-frame continuous reception buffe r registers 1, 2 (rxb1, rxb2)/ reception buffer registers l1, l2 (rxbl1, rxbl2) the rxbn register is a 16-bit buffer register that holds receive data (during 2-frame continuous reception (umsr bit of asimn1 register = 1), during 9-bit extended data reception (ebs bit of asimn1 register = 1)) (n = 1, 2). during 7 or 8 bit/character rec eption, 0 is stored in the msb. for 16-bit access to this register, specify rxbn, and for access to the lower 8 bits, specify rxbln. in the receive enabled status, receive data is transferr ed from the reception shift register to the reception buffer in synchronization with the end of shi ft-in processing for 1 frame of data. the reception completion interrupt request (intsrn) is generated upon transfer of data to the reception buffer (when 2-frame continuous reception is specif ied, reception buffer transfer of the second frame). in the reception disabled status, transfer processing to the reception buffer is not performed even if shift-in processing for 1 frame of data has been completed, and the contents of the rec eption buffer are held. neither is a reception completion interrupt request generated. the rxbn register is read-only, in 16-bit units, and the rxbln register is read-only, in 8-bit units. chapter 10 serial interface function user?s manual u14492ej4v1ud 444 14 rxb14 13 rxb13 12 rxb12 2 rxb2 3 rxb3 4 rxb4 5 rxb5 6 rxb6 7 rxb7 8 rxb8 9 rxb9 10 rxb10 11 rxb11 15 rxb15 1 rxb1 0 rxb0 rxb1 [2-frame continuous reception buffer register 1] address fffffa20h initial value undefined 2 rxb2 3 rxb3 4 rxb4 5 rxb5 6 rxb6 7 rxb7 1 rxb1 0 rxb0 rxbl1 [reception buffer register l1] address fffffa22h initial value undefined 14 rxb14 13 rxb13 12 rxb12 2 rxb2 3 rxb3 4 rxb4 5 rxb5 6 rxb6 7 rxb7 8 rxb8 9 rxb9 10 rxb10 11 rxb11 15 rxb15 1 rxb1 0 rxb0 rxb2 [2-frame continuous reception buffer register 2] address fffffa40h initial value undefined 2 rxb2 3 rxb3 4 rxb4 5 rxb5 6 rxb6 7 rxb7 1 rxb1 0 rxb0 rxbl2 [reception buffer register l2] address fffffa42h initial value undefined bit position bit name function 15 to 0 rxb15 to rxb0 stores receive data. 0 can be read for the rxbn register w hen 7, 8 bit/character data is received. when an extension bit is set during 9 bit/cha racter data reception, the extension bit (rxb8) is stored in rb8 of the asisn register simultaneously with saving to the reception buffer. 0 can be read for the rxb7 bit of the rxbln register during 7 bit/character data reception. (a) when 2-frame contin uous reception is set 14 rxb14 13 rxb13 12 rxb12 2 rxb2 3 rxb3 4 rxb4 5 rxb5 6 rxb6 7 rxb7 8 rxb8 9 rxb9 10 rxb10 11 rxb11 15 rxb15 1 rxb1 0 rxb0 rxbn 7-/8-bit data of 1st frame 7-/8-bit data of 2nd frame (b) when 9-bit extension reception is set 14 rxb14 13 rxb13 12 rxb12 2 rxb2 3 rxb3 4 rxb4 5 rxb5 6 rxb6 7 rxb7 8 rxb8 9 rxb9 10 rxb10 11 rxb11 15 rxb15 1 rxb1 0 rxb0 rxbn 9-bit extended data when 9-bit extension is set, the extension bit (rxb8) is stored in the rb8 bit of the asisn register simultaneously with saving to the reception buffer. chapter 10 serial interface function user?s manual u14492ej4v1ud 445 (c) cautions <1> operation upon occurrence of overrun error during 2-frame c ontinuous reception ? during normal reception reception completion interrupt (intsrn) generated upon end of reception of 2nd frame, no error rxdn frame 1 frame 2 ? reception of 3rd frame started be fore performing reception processing reception completion interrupt (intsrn) generated upon end of reception of 2nd frame, no error rxdn frame 1 frame 2 reception completion interrupt not generated upon end of reception of 3rd frame, occurrence of error rxdn frame 3 frame 3 value of oven bit of asisn register becomes 1. ? start of reception of 3rd frame and 4th fr ame before performing reception processing reception completion interrupt (intsrn) generated upon end of reception of 2nd frame, no error rxdn frame 1 frame 2 reception completion interrupt not generated upon end of reception of 3rd frame, occurrence of error rxdn frame 3 frame 3 value of oven bit of asisn register becomes 1. reception completion interrupt (intsrn) generated upon end of reception of 4th frame, no error rxdn frame 3 frame 4 value of oven bit of asisn register remains 1. ? start of reception of 3rd frame before perfo rming reception processing, start of reception of 4th frame after performing reception processing reception completion interrupt (intsrn) generated upon end of reception of 2nd frame, no error rxdn frame 1 frame 2 reception completion interrupt not generated upon end of reception of 3rd frame, occurrence of error rxdn frame 3 frame 3 value of oven bit of asisn register becomes 1. value of oven flag becomes 0 during reception processing. reception completion interrupt (intsrn) generated upon end of reception of 4th frame, no error rxdn frame 3 frame 4 no occurrence of error chapter 10 serial interface function user?s manual u14492ej4v1ud 446 (5) 2-frame continuous transmission sh ift registers 1, 2 (txs1, txs2)/tr ansmission shift registers l1, l2 (txsl1, txsl2) the txsn register is a 9-bit/2-f rame continuous transmission processing shift register (n = 1, 2). transmission is started by writing data to this register. a transmission completion interrupt request (intstn) is generat ed in synchronization with the end of transmission of 1 frame or 2 frames including the txsn data. for 16-bit access to this register, specify txsn, and for access to the lower 8 bits, specify txsln. the txsn register is write-only, in 16-bit units, and the txsln register is write-only, in 8-bit units. caution txsn, txsln can be read, but since shifting is done in synch ronization with the shift clock, the data that is read cannot be guaranteed. 14 txs14 13 txs13 12 txs12 2 txs2 3 txs3 4 txs4 5 txs5 6 txs6 7 txs7 8 txs8 9 txs9 10 txs10 11 txs11 15 txs15 1 txs1 0 txs0 txs1 [2-frame continuous transmission shift register 1] address fffffa24h initial value undefined 2 txs2 3 txs3 4 txs4 5 txs5 6 txs6 7 txs7 1 txs1 0 txs0 txsl1 [transmission shift register l1] address fffffa26h initial value undefined 14 txs14 13 txs13 12 txs12 2 txs2 3 txs3 4 txs4 5 txs5 6 txs6 7 txs7 8 txs8 9 txs9 10 txs10 11 txs11 15 txs15 1 txs1 0 txs0 txs2 [2-frame continuous transmission shift register 2] address fffffa44h initial value undefined 2 txs2 3 txs3 4 txs4 5 txs5 6 txs6 7 txs7 1 txs1 0 txs0 txsl2 [transmission shift register l2] address fffffa46h initial value undefined bit position bit name function 15 to 0 txb15 to txb0 writes transmit data. chapter 10 serial interface function user?s manual u14492ej4v1ud 447 10.3.4 interrupt requests the following two types of interrupt request are generated from uartn (n = 1, 2). ? reception completion interrupt (intsrn) ? transmission completion interrupt (intstn) the reception completion interrupt has higher default pr iority than the transmission completion interrupt. table 10-5. default priori ty of generated interrupts interrupt priority reception completion 1 transmission completion 2 (1) reception completion interrupt (intsrn) in the reception enabled state, t he reception completion interrupt (int srn) is generated when data in the reception shift register undergoes shift-in proc essing and is transferred to the reception buffer. the reception completion interrupt r equest (intsrn) is generated follow ing stop bit sampling. the reception completion interrupt (intsrn) is gener ated upon occurrence of an error. in the reception disabled state, no rec eption completion interrupt is generated. caution a reception completion interrupt (intsrn) is generated when the last bit of receive data (stop bit) is sampled. (2) transmission completion interrupt (intstn) since uartn does not have a transmission buffer, a tran smission completion interrupt request (intstn) is generated when one frame of dat a containing 7-bit or 8-bit characters or two frames of data containing 9-bit characters are shifted out from the tr ansmission shift register (txsn, txsln). chapter 10 serial interface function user?s manual u14492ej4v1ud 448 10.3.5 operation (1) data format full-duplex serial data is transmitted and received. figure 10-16 shows the format of transmit/receive data. o ne data frame consists of a start bit, character bits, a parity bit, and a stop bit(s). when 2 data frame tr ansfer is set, both frames have the above-described format. specification of the character bit length in one data fr ame, parity selection, and s pecification of the stop bit length is done using asynchronous serial interface mode registers 10, 20 (asim10, asi m20). specification of the number of frames and specificatio n of the extension bit is done with asynchronous serial interface mode registers 11, 21 (asim11, asim21). data is transmitted lsb first. figure 10-16. asynchronous serial interface transmit/receive data format (a) 1-frame format 1 frame data stop bit start bit parity/ extension bit d0 d1 d2 d3 d4 d5 d6 d7 (b) 2-frame format higher frame lower frame data d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit parity bit stop bit start bit ? start bit: 1 bit ? character bits: 7 or 8 bits ? parity bit: even parity, odd parity, 0 parity, or no parity ? stop bit: 1 or 2 bits caution the extension bit is invalid in the 2-frame c ontinuous mode or when a parity bit is added. chapter 10 serial interface function user?s manual u14492ej4v1ud 449 table 10-6. asimn0, asimn1 regi ster settings and data format asimn0, asimn1 register settings data format cl bit ps1 bit ps0 bit sl bit ebs bit d0 to d6 d7 d8 d9 d10 0 0 0 data stop bit ? ? ? 0 other than ps1 = ps0 = 0 data parity bit stop bit ? ? 1 0 0 data data stop bit ? ? 1 other than ps1 = ps0 = 0 0 0 data data parity bit stop bit ? 0 0 0 data stop bit stop bit ? ? 0 other than ps1 = ps0 = 0 data parity bit stop bit stop bit ? 1 0 0 data data stop bit stop bit ? 1 other than ps1 = ps0 = 0 1 0 data data parity bit stop bit stop bit 0 0 0 data stop bit ? ? ? 0 other than ps1 = ps0 = 0 data parity bit stop bit ? ? 1 0 0 data data data stop bit ? 1 other than ps1 = ps0 = 0 0 1 data data parity bit stop bit ? 0 0 0 data stop bit stop bit ? ? 0 other than ps1 = ps0 = 0 data parity bit stop bit stop bit ? 1 0 0 data data data stop bit stop bit 1 other than ps1 = ps0 = 0 1 1 data data parity bit stop bit stop bit chapter 10 serial interface function user?s manual u14492ej4v1ud 450 (2) transmission operation the transmission operation is started by writing data to 2-frame continuo us transmission shift registers 1, 2 (txs1, txs2)/transmission shift regi sters l1, l2 (txsl1, txsl2). following data write, the start bit is transmitted from the next shift timing. since the uartn does not have a cts (transmission enable signal) input pin, use a port when the other party confirms the reception enabled status (n = 1, 2). (a) transmission operation start the transmission operation is started by writing transmit data to 2-frame continuous transmission shift registers 1, 2 (txs1, txs2)/transmission shift register s l1, l2 (txsl1, txsl2). then data is output in sequence from lsb to the txdn pin (transmission in se quence from the start bit). a start bit, parity bit, and stop bit(s) are automatically added. (b) transmission interrupt request when the transmission shift register becomes empt y upon completion of the transmission of 1 or 2 frames of data, a transmission completion interrupt re quest (intstn) is generated. the intstn interrupt generation timing differs depending on the specified stop bit length. the intstn interrupt is generated at the same time that the last stop bit is output. the transmission operation remains st opped until the data to be transmitt ed next has been written to the txsn/txsln registers. figure 10-17 shows the intstn interrupt generation timing. cautions 1. normally, the transm ission completion interrupt (int stn) is generated when the transmission shift register b ecomes empty. however, if th e transmission shift register has become empty due to input of r eset, no transmission completion interrupt (intstn) is generated. 2. no data can be written to the txsn or txsln registers during transmission operation until intstn is generated. even if data is written, this does not affect the transmission operation. chapter 10 serial interface function user?s manual u14492ej4v1ud 451 figure 10-17. asynchronous serial interf ace transmission comple tion interrupt timing (a) when stop bit length = 1 bit start parity stop d0 txdn (output) intstn interrupt flag in transmission (sotn) d1 d2 d6 d7 (b) when stop bit length = 2 bits start parity stop d0 txdn (output) intstn interrupt flag in transmission (sotn) d1 d2 d6 d7 (c) in 2-frame contin uous transmission mode start start stop parity stop d0 txdn (output) intstn interrupt flag in transmission (sotn) d1 1st frame 2nd frame d1 d5 d6 d7 parity chapter 10 serial interface function user?s manual u14492ej4v1ud 452 (3) continuous transmission of 3 or more frames in addition to the 1-frame/2-frame transmission function, uartn also enables continuous transmission of 3 or more frames, using the method shown below (n = 1, 2). (a) how to continuously transmit 3 or more fr ames (when the stop bit is 1 bit (sl bit = 0)) three frames can be continuously transmitted by writ ing transmit data to the t xsn/txsln register in the period between the generation of the transmission completion interrupt request (intstn) and 4 2/f xx before the output of the last stop bit. the intstn interrupt becomes high level 2/f xx after being output and returns to low level 2/f xx later. txsn/txsln can only be written after the intstn inte rrupt level has fallen. the time from intstn interrupt generation to the completion of transmit dat a writing (t) is therefore indicated by the following expression. t = (time of one stop bit) ? (2 2/f xx + 4 2/f xx ) f xx = internal system clock caution 4 2/f xx has a margin of double the clock that can actually be used for operation. example count clock frequency = 32 mhz = 32,000,000 hz target baud rate in synchronous mode = 9,600 bps t = (1/9615.385) ? ((4 + 8)/32,000,000) = 104.000 ? 0.375 = 103.625 [ s] therefore, be sure to write tr ansmit data to txsn/txsln within 103 s of the generation of the intstn interrupt. note, however, that because writing to txsn/txsln ma y be delayed depending on the priority order of the intstn interrupt or the interrupt servicing time, be sure to allow sufficient time for writing transmit data after the intstn interrupt has been generated. if there is not enough time for continuous transmission due to a delay in writing to t xsn/txsln, a 1-bit high level is transmitted. note also that if the stop bit length is 2 bits (sl bi t = 1), the intstn interrupt will be generated when the second stop bit is output. figure 10-18. continuous transmission of 3 or more frames (when sl bit = 0) 2/f xx 2/f xx 2/f xx 4 2/f xx txsn/txsln write period for 3-frame continuous transmission stop bit intstn interrupt chapter 10 serial interface function user?s manual u14492ej4v1ud 453 (4) reception operation the reception wait status is entered by setting the rxen bit of the asim n0 register to 1 (n = 1, 2). to start the reception operation, first perform start bit detection. start bit detection is done by performing sampling of the rxdn pin. when the reception operat ion is started, serial data is stor ed to the reception shift register in sequence at the set baud rate. each time reception of 2 frames or 1 frame of rxbn or rxbln data has been completed, a reception completion interrupt (intsrn) is generated. receive data is transmitted from the reception buffer (rxbn/rxbln) to memory when this interrupt is serviced. (a) reception enabled status the reception operation is enabled by setting (1) the rxen bit of the asimn0 register. ? rxen = 1: reception enabled status ? rxen = 0: reception disabled status in the reception disabled status, the reception hardware is in standby in an initialized state. at this time, no reception completion interrupt is generated, and the contents of the reception buffer are held. (b) start of reception operation the reception operation is started th rough detection of the start bit. ? in asynchronous mode (mod bit of asimn1 register = 0) the rxdn pin is sampled using the serial clock from the baud rate generator. after 8 serial clocks have been output following detection of the falling edge of the rxdn pin, the rxdn pin is again sampled. if a low level is detected at this time, the falling edge of the rxdn pin is interpreted as a start bit, the operation shifts to reception processi ng, and the rxdn pin input is sampled from this point on in units of 16 serial clock output. if the high level is detected during sampling after 8 serial clocks from detection of the falling edge of the rxdn pin, this falling edge is not recognized as a start bit. the serial clock counter that generates the sample timing is initialized and stops, and i nput of the next falling edge is waited for. ? in synchronous mode (mod bit of asimn1 register = 1) the rxdn pin is sampled using the serial clock from the baud rate generator or at the rising edge of serial clock i/o. if the rxdn pin is lo w level at this time, th is is interpreted as a start bit and reception processing starts. if reception data is interrupted at the fixed low le vel during reception, recept ion of this receive data (including error detection) is completed and reception completion interrupt is generated. however, even if the rxd line is fixed at low leve l, the next reception operation is not started (start bit detection is not performed). be sure to set the high level when restarting the rec eption operation. if the high level is not set, the start bit detection position becomes undefined, and corre ct reception operation cannot be performed. chapter 10 serial interface function user?s manual u14492ej4v1ud 454 (c) reception completion interrupt request when reception of one frame of data has been complete d (stop bit detection) when the rxen bit of the asimn0 register = 1, the receive data in the shift re gister is transferred to rxbn/rxbln and a reception completion interrupt request (intsrn) is generated after 1 frame or 2 frames of data have been transferred to rxbn/rxbln. a reception completion interrupt is also generated upon detection of an error. when the rxen bit = 0 (reception disabled), no reception completion interrupt is generated. figure 10-19. asynchronous serial interface reception completion interrupt timing (a) when stop bit length = 1 bit start parity stop d0 rxdn (input) intsrn interrupt flag in reception (sirn) d1 d2 d6 d7 (b) when stop bit length = 2 bits start parity stop d0 rxdn (input) intsrn interrupt flag in reception (sirn) d1 d2 d6 d7 (c) in 2-frame contin uous transmission mode start start parity stop parity stop d0 rxdn (input) intsrn interrupt flag in reception (sirn) d1 1st frame 2nd frame d1 d5 d6 d7 chapter 10 serial interface function user?s manual u14492ej4v1ud 455 cautions 1. even if a reception error occurs, be sure to read 2-frame continuous reception buffer register n (rxbn)/reception buffer register n (rxb ln). if the rxbn or rxbln register is not read, an overrun error will occur at the next data reception, and the reception error state will continue indefinitely. 2. reception is always performed with the stop bi t length set to 1 bit. a second stop bit is ignored. (5) reception errors the three types of error flags of parity errors, fr aming errors, and overrun errors are affected in synchronization with reception operation. as a result of data reception, the pen, fen, and oven flags of the asisn register are set (1) and a reception completion interrupt request (intsrn) is generated at the same time. the contents of error that occurr ed during reception can be detected by reading the contents of the pen, fen, and oven flags of the asisn register during the intsrn interrupt servicing. the contents of the asisn r egister are reset (0) by reading the asisn register (if the next receive data contains an error, the corresponding error flag is set (1)). table 10-7. reception error causes error flag reception error causes pen parity error the parity specific ation during transmission did not match the parity of the reception data fen framing error no stop bit was detected oven overrun error the reception of the next data was completed before data was read from the reception buffer (6) parity types and co rresponding operation a parity bit is used to detect a bit error in communication data. normally, the same type of parity bit is used at the transmission and reception sides. (a) even parity <1> during transmission the parity bit is controlled so that number of bits with the value ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1? within the transmit data is even: 0 <2> during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. chapter 10 serial interface function user?s manual u14492ej4v1ud 456 (b) odd parity <1> during transmission in contrast to even parity, the parity bit is controlled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1? within the transmit data is even: 1 <2> during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity during transmission, the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (d) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no parity bit. since there is no parity bit, no parity error is generated. chapter 10 serial interface function user?s manual u14492ej4v1ud 457 10.3.6 synchronous mode the synchronous mode can be set wit h the asckn pin, which is the serial clock i/o pin (n = 1, 2). the synchronous mode is set with the mod bit of the asimn1 register, and the serial clock to be used for synchronization is selected with the scls bit of the asimn0 register. in the synchronous mode, external clock input is selected when the value of the scls bit is 0 (default), and the serial clock output is selected in the case of all other se ttings. therefore, when perfo rming settings, make sure that outputs between connection nodes do not conflict. in the synchronous mode, the falling edge of the serial clock is used as the transmission timing, and the rising edge as the reception timing, but tr ansmit data is output with a delay of 1 system cl ock (serial clock) (in the external clock synchronous mode, the maximum delay is 2.5 system clocks). figure 10-20. transmission/recep tion timing in sy nchronous mode d0 d1 d2 d3 d4 d5 d6 d7 parity start stop d0 d1 d2 d3 d4 d5 d6 d7 parity start stop asckn output data (txdn) input data (rxdn) on the data output side, the data changes at the falling edge of the serial clock output. on the data input side, the data is latched at the rising edge of the serial clock output. serial clock output continues as long as the setting is not canceled. remark n = 1, 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 458 figure 10-21. transmission/reception ti ming chart for sync hronous mode (1/3) (a) in 1-frame transm ission/reception mode serial clock transmission register write signal flag in transmission (sotn) transmission completion interrupt (intstn) reception completion interrupt (intsrn) reception buffer (rxbn) reception buffer (rxbln) flag in reception (sirn) transmit data stop bit undefined (hold previous value) undefined (hold previous value) 005ah 5ah remark n = 1, 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 459 figure 10-21. transmission/reception ti ming chart for sync hronous mode (2/3) (b) in 2-frame continuous transmission/reception mode serial clock transmission register write signal flag in transmission (sotn) transmission completion interrupt (intstn) reception completion interrupt (intsrn) reception buffer (rxbn) reception buffer (rxbln) flag in reception (sirn) transmit data stop bit stop bit undefined (hold previous value) undefined (hold previous value) 5a5ah 5ah 5a15h 15h remark n = 1, 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 460 figure 10-21. transmission/reception ti ming chart for sync hronous mode (3/3) (c) transmission/reception timing and transmit data ti ming during serial clock output note serial clock (output) system clock transmit data transmission timing reception timing note the transmit data is delayed by 1 system clock in relation to the serial clock. (d) transmission/reception timi ng and transmit data timing using external serial clock note external serial clock system clock transmit data transmission timing reception timing note since, during external serial cl ock synchronization, synchronization is done with the internal system clock when feeding the external serial clock to the in ternal circuit, a delay ranging from 1 system clock to a maximum of 2.5 system clocks results. chapter 10 serial interface function user?s manual u14492ej4v1ud 461 figure 10-22. reception completion interrupt a nd error interrupt generation timing during synchronous mode reception (a) during normal operation (in 1-frame reception mode) start receive data flag in reception (sirn) reception completion interrupt (intsrn) error interrupt stop (b) in 2-frame cont inuous reception mode start start receive data flag in reception (sirn) reception completion interrupt (intsrn) error interrupt stop stop (1) (2) (3) chapter 10 serial interface function user?s manual u14492ej4v1ud 462 10.3.7 dedicated baud rate gene rators 1, 2 (brg1, brg2) (1) configuration of baud rate ge nerators 1, 2 (brg1, brg2) for uart1 and uart2, the serial clock can be selected from the dedicated baud rate generator output or internal system clock (f xx ) for each channel. the serial clock source is specif ied with registers asim10 and asim20. if dedicated baud rate generator output is specified, brg1 and brg2 are selected as the clock sources. since the same serial clock can be shared for transmission and reception for one channel, baud rate is the same for the transmission/reception. figure 10-23. block diagram of baud ra te generators 1, 2 (brg1, brg2) bgcs1, bgcs0 prscmn match detector 1/2 uartn 8-bit timer counter f xx /2 f xx /4 f xx /8 f xx /16 selector remark f xx : internal system clock n = 1, 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 463 (2) dedicated baud rate genera tors 1, 2 (brg1, brg2) brgn is configured of an 8-bit timer counter for baud ra te signal generation, a prescaler mode register that controls the generation of the baud rate signal (prsmn), a prescaler compare register that sets the value of the 8-bit timer counter (prscmn), and a prescaler (n = 1, 2). (a) input clock the internal system clock (f xx ) is input to brgn. (b) prescaler mode registers 1, 2 (prsm1, prsm2) the prsmn register controls generation of t he uartn baud rate signal (n = 1, 2). these registers can be read/written in 8-bit or 1-bit units. cautions 1. do not change the values of th e bgcs1 and bgcs0 bits during transmission/ reception operations. 2. set prsmn register other than the uart cen bit prior to setting the uartcen bit to 1 (n = 1, 2). <7> uartce1 prsm1 6 0 5 0 4 0 3 0 2 0 1 bgcs1 0 bgcs0 address fffffa2eh initial value 00h <7> uartce2 prsm2 6 0 5 0 4 0 3 0 2 0 1 bgcs1 0 bgcs0 address fffffa4eh initial value 00h bit position bit name function 7 uartcen enables baud rate counter operation. 0: stop baud rate counter operation and fix baud rate output signal to ?0?. 1: enable baud rate counter operation and start baud rate output operation. selects count clock to baud rate counter. bgcs1 bgcs0 count clock selection 0 0 f xx /2 0 1 f xx /4 1 0 f xx /8 1 1 f xx /16 1, 0 bgcs1, bgcs0 remark f xx : internal system clock remark n = 1, 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 464 (c) prescaler compare register s 1, 2 (prscm1, prscm2) prscmn is an 8-bit compare register that sets t he value of the 8-bit timer counter (n = 1, 2). these registers can be read/written in 8-bit units. cautions 1. the internal timer counter is cleare d by writing to the prsc mn register. therefore, do not overwrite the prscmn regist er during transmission operation. 2. perform prscmn register settings prior to setting the uartcen bit to 1. if the contents of the prscmn register are over written when the value of the uartcen bit is 1, the cycle of the baud rate signal is not guaranteed. 3. set the baud rate to 15 3,600 bps or lower in asynch ronous mode, and 1,000,000 bps or lower in synchronous mode. 7 prscm7 prscm1 6 prscm6 5 prscm5 4 prscm4 3 prscm3 2 prscm2 1 prscm1 0 prscm0 address fffffa30h initial value 00h 7 prscm7 prscm2 6 prscm6 5 prscm5 4 prscm4 3 prscm3 2 prscm2 1 prscm1 0 prscm0 address fffffa50h initial value 00h (d) baud rate generation first, when the uartcen bit of the prsmn register is overwritten with 1, the 8-bit timer counter for baud rate signal generation starts c ounting up with the clock selected with bits bgcs1 and bgcs0 of the prsmn register. the count value of the 8-bit time r counter is compared with the value of the prscmn register, and if these values match, a timer count clock pulse of 1 cycle is output to the output controller for the baud rate. the output controller for the baud rate reverses the ba ud rate signal in synchronization with the rising edge of the timer count clock when this pulse is ?1?. (e) cycle of baud rate signal the cycle of the baud rate signal is calculated as follows. ? when setting value of prscmn register is 00h (cycle of signal selected with bits bgcs1, bgcs0 of prsmn register) 256 2 ? in cases other than above (cycle of signal selected with bits bgcs1, bgcs0 of prsmn register) (setting value of prscmn register) 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 465 (f) baud rate setting value the formulas for calculating the baud rate in the asynchronous mode and the synchronous mode and the formula for calculating the error are as follows. <1> formula for calculating baud rate in asynchronous mode baud rate = [bps] f xx = internal system clock frequency [hz] = cpu clock/2 [hz] m: setting value of prscmn register (1 m 256 note ) k: value set with bits bgcs1, bgcs0 of prsmn register (k = 0, 1, 2, 3) note the setting of m = 256 is performed by writing 00h to the prscmn register. <2> formula for calculating the ba ud rate in synchronous mode baud rate = [bps] f xx = internal system clock frequency [hz] = cpu clock/2 [hz] m: setting value of prscmn register (1 m 256 note ) k: value set with bits bgcs1, bgcs0 of prsmn register (k = 0, 1, 2, 3) note the setting of m = 256 is performed by writing 00h to the prscmn register. <3> formula for calculating error error [%] = 100 example (9520 ? 9600)/9600 100 = ? 0.833 [%] remark actual baud rate: baud rate with error desired baud rate: normal baud rate f xx 2 m 2 k 16 f xx 2 m 2 k actual baud rate ? desired baud rate desired baud rate chapter 10 serial interface function user?s manual u14492ej4v1ud 466 <4> baud rate setting example in an actual system, the output of a prescaler module , etc. is connected to input clock. table 10-8 shows the baud rate generator setting data at this time. table 10-8. baud rate gene rator setting data (brg = f xx /2) (1/2) (a) when f xx = 32 mhz desired baud rate actual baud rate synchronous mode asynchronous mode synchronous mode asynchronous mode bgcsm bit (m = 0, 1) prscmn register setting value (n = 1, 2) error 4800 300 4807.692 300.4808 3 208 0.16 9600 600 9615.385 600.9615 3 104 0.16 19200 1200 19230.77 1201.923 3 52 0.16 38400 2400 38461.54 2403.846 3 26 0.16 76800 4800 76923.08 4807.692 3 13 0.16 153600 9600 153846.2 9615.385 2 13 0.16 166400 10400 166666.7 10416.67 1 24 0.16 307200 19200 307692.3 19230.77 1 13 0.16 614400 38400 615384.6 38461.54 0 13 0.16 setting prohibited 76800 ? 71428.57 0 7 ? 6.99 setting prohibited 153600 ? 166666.7 0 3 8.51 (b) when f xx = 40 mhz desired baud rate actual baud rate synchronous mode asynchronous mode synchronous mode asynchronous mode bgcsm bit (m = 0, 1) prscmn register setting value (n = 1, 2) error 4800 300 4882.813 305.1758 3 256 1.73 9600 600 9615.385 600.9615 3 130 0.16 19200 1200 19230.77 1201.923 3 65 0.16 38400 2400 38461.54 2403.846 2 65 0.16 76800 4800 76923.08 4807.692 1 65 0.16 153600 9600 153846.2 9615.385 0 65 0.16 166400 10400 166666.7 10416.67 0 60 0.16 307200 19200 303030.3 18939.39 0 33 ? 1.36 614400 38400 625000 39062.5 0 16 1.73 setting prohibited 76800 ? 78125 0 8 1.73 setting prohibited 153600 ? 156250 0 4 1.73 chapter 10 serial interface function user?s manual u14492ej4v1ud 467 table 10-8. baud rate gene rator setting data (brg = f xx /2) (2/2) (c) when f xx = 50 mhz desired baud rate actual baud rate synchronous mode asynchronous mode synchronous mode asynchronous mode bgcsm bit (m = 0, 1) prscmn register setting value (n = 1, 2) error 9600 600 9585.89 599.1181 3 163 ? 0.15 19200 1200 19171.78 1198.236 2 163 ? 0.15 38400 2400 38343.56 2396.472 1 163 ? 0.15 76800 4800 76687.12 4792.945 0 163 ? 0.15 153600 9600 154321 9645.062 0 81 0.47 166400 10400 166666.7 10416.67 0 75 0.16 307200 19200 312500 19531.25 0 40 1.73 614400 38400 625000 39062.5 0 20 1.73 setting prohibited 76800 ? 78125 0 10 1.73 setting prohibited 153600 ? 156250 0 5 1.73 chapter 10 serial interface function user?s manual u14492ej4v1ud 468 (3) allowable baud rate range during reception the degree to which a discrepancy from the transmission destination?s baud rate is allowed during reception is shown below. caution the equations described be low should be used to set th e baud rate error during reception so that it always is withi n the allowable error range. figure 10-24. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartn transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 10-24, after the start bit is detecte d, the receive data latch timing is determined according to the counter that was set by the prscmn register. if all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. if this is applied to 11-bit reception, the following is theoretically true. fl = (brate) ?1 brate: uartn baud rate k: prscmn register setting value fl: 1-bit data length when the latch timing margin is 2 clocks of f xx /2, the minimum allowable transfer rate (flmin) is as follows (f xx : internal system clock). fl k 2 2 k 21 fl k 2 2 k fl 11 min fl + = ? ? = chapter 10 serial interface function user?s manual u14492ej4v1ud 469 therefore, the transfer destination?s maximum re ceivable baud rate (brmax) is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum allowable transfer rate (flmax) can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 max fl 11 10 ? = + ? = 11 fl k 20 2 k 21 max fl ? = therefore, the transfer destination?s minimum receivable baud rate (brmin) is as follows. brmin = (flmax/11) ? 1 = brate (4) transfer rate in 2 -frame continuous reception in 2-frame continuous reception, the ti ming is initialized by detecting the st art bit of the second frame, so the transfer results are not affected. 22k 21k + 2 20k 21k ? 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 470 10.4 clocked serial inte rfaces 0, 1 (csi0, csi1) 10.4.1 features ? high-speed transfer: maximum 5 mbps ? half-duplex communications ? master mode or slave mode can be selected ? transmission data length: 8 bits or 16 bits can be set ? transfer data direction can be swit ched between msb first and lsb first ? eight clock signals can be selected (7 master clocks and 1 slave clock) ? 3-wire type son: serial transmit data output sin: serial receive data input sckn: serial clock i/o ? interrupt sources: 1 type ? transmission/reception completion interrupt (intcsin) ? transmission/reception mode and rece ption-only mode can be specified ? two transmission buffers (sotbfn/ sotbfln, sotbn/sotbln) and two re ception buffers (sirbn/sirbln, sirben/sirbeln) are provided on chip ? single transfer mode and repeat transfer mode can be specified remark n = 0, 1 10.4.2 configuration csin is controlled via the clocked serial interface mode re gister (csimn) (n = 0, 1). transmission/reception of data is performed by writing/reading the sion register (n = 0, 1). (1) clocked serial interface mode re gisters 0, 1 (csim0, csim1) the csimn register is an 8-bit register that specifies the operation of csin. (2) clocked serial interface clock selecti on registers 0, 1 (csic0, csic1) the csicn register is an 8-bit register that controls the csin serial transfer operation. (3) serial i/o shift registers 0, 1 (sio0, sio1) the sion register is a 16-bit shift register that converts parallel data into serial data. the sion register is used for bot h transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations ar e started up by accessing the buffer register. (4) serial i/o shift registers l0, l1 (siol0, siol1) the sioln register is an 8-bit shift register th at converts parallel data into serial data. the sioln register is used for bot h transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations are started up by accessing the buffer register. chapter 10 serial interface function user?s manual u14492ej4v1ud 471 (5) clocked serial interface reception bu ffer registers 0, 1 (sirb0, sirb1) the sirbn register is a 16-bit buffer r egister that stores receive data. (6) clocked serial interface reception buffe r registers l0, l1 (sirbl0, sirbl1) the sirbln register is an 8-bit buffer r egister that stores receive data. (7) clocked serial interface read-only reception buffer registers 0, 1 (sirbe0, sirbe1) the sirben register is a 16-bit buffer register that stores receive data. the sirben register is the same as the sirbn register. it is used to read the contents of the sirbn register. (8) clocked serial interface read-only reception buffer registers l0, l1 (sirbel0, sirbel1) the sirbeln register is an 8-bit buffer register that stores receive data. the sirbeln register is the same as the sirbln register. it is used to read the contents of the sirbln register. (9) clocked serial interface transmission buf fer registers 0, 1 (sotb0, sotb1) the sotbn register is a 16-bit buffer r egister that stores transmit data. (10) clocked serial interface transmission buffer registers l0, l1 (sotbl0, sotbl1) the sotbln register is an 8-bit buffer register that stores transmit data. (11) clocked serial interface initial tran smission buffer registers (sotbf0, sotbf1) the sotbfn register is a 16-bit buffer register that stores the initial trans mit data in the repeat transfer mode. (12) clocked serial interface initial transm ission buffer register l (sotbfl0, sotbfl1) the sotbfln register is an 8-bit buffer register that st ores initial transmit data in the repeat transfer mode. (13) selector the selector selects the serial clock to be used. (14) serial clock controller controls the serial clock supply to the shift register. also controls the clock output to the sckn pin when the internal clock is used. (15) serial clock counter counts the serial clock output or input during transmi ssion/reception operation, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) interrupt controller controls the interrupt request timing. chapter 10 serial interface function user?s manual u14492ej4v1ud 472 figure 10-25. block diagram of clocked serial interface selector transmission control so selection so latch transmission buffer register (sotbn/sotbln) reception buffer register (sirbn/sirbln) shift register (sion/sioln) initial transmission buffer register (sotbfn/sotbfln) interrupt controller clock start/stop control & clock phase control serial clock controller sckn intcsin son sin control signal transmission data control f xx /2 7 f xx /2 6 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 brg3 sckn remarks 1. n = 0, 1 2. f xx : internal system clock 10.4.3 control registers (1) clocked serial interface mode re gisters 0, 1 (csim0, csim1) the csimn register controls the csin operation (n = 0, 1). these registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only). caution overwriting the trmdn, ccl, dirn, csit, and auto bits of the csimn register can be done only when the csotn bit = 0. if these bits are overwritten at any other time, the operation cannot be guaranteed. chapter 10 serial interface function user?s manual u14492ej4v1ud 473 <7> csicae0 csim0 <6> trmd0 5 ccl <4> dir0 3 csit 2 auto 1 0 <0> csot0 <7> csicae1 <6> trmd1 5 ccl <4> dir1 3 csit 2 auto 1 0 <0> csot1 address fffff900h initial value 00h csim1 address fffff910h initial value 00h bit position bit name function 7 csicaen enables/disables csin operation. 0: disable csin operation. 1: enable csin operation. the internal csin circuit can be reset asynchronously by setting the csicaen bit to 0. for the sckn and son pin output status when the csicaen bit = 0, refer to 10.4.5 output pins . 6 trmdn specifies transmission/reception mode. 0: receive-only mode 1: transmission/reception mode when the trmdn bit = 0, receive-only transfer is performed and the son pin output is fixed to low level. data reception is started by reading the sirbn register. when the trmdn bit = 1, transmission/recept ion is started by writing data to the sotbn register. 5 ccl specifies data length. 0: 8 bits 1: 16 bits 4 dirn specifies transfer direction mode (msb/lsb). 0: first bit of transfer data is msb 1: first bit of transfer data is lsb 3 csit controls delay of interrupt request signal. 0: no delay 1: delay mode (interrupt request signal is delayed 1/2 cycle). caution the delay mode (csit bit = 1) is valid only in the master mode (cks2 to csk0 bits of the csicn register are not 111b). in the slave mode (cks2 to cks0 bits are 111b), do not set the delay mode. 2 auto specifies single transfer mode or repeat transfer mode. 0: single transfer mode 1: repeat transfer mode 0 csotn flag indicating transfer status. 0: idle status 1: transfer execution status caution the csotn bit is cleared (0 ) by writing 0 to the csicaen bit. remark n = 0, 1 chapter 10 serial interface function user?s manual u14492ej4v1ud 474 (2) clocked serial interface clock selecti on registers 0, 1 (csic0, csic1) the csicn register is an 8-bit register that co ntrols the csin transfer operation (n = 0, 1). these registers can be read/written in 8-bit or 1-bit units. caution the csicn register can be overwritten only when the csicaen bi t of the csimn register = 0. chapter 10 serial interface function user?s manual u14492ej4v1ud 475 7 0 csic0 6 0 5 0 4 ckp 3 dap 2 cks2 1 cks1 0 cks0 7 0 6 0 5 0 4 ckp 3 dap 2 cks2 1 cks1 0 cks0 address fffff901h initial value 00h csic1 address fffff911h initial value 00h bit position bit name function specifies operation mode. ckp dap operation mode 0 0 0 1 1 0 1 1 4, 3 ckp, dap remark n = 0, 1 specifies serial clock. cks2 cks1 cks0 serial clock mode 0 0 0 f xx /2 7 master mode 0 0 1 f xx /2 6 master mode 0 1 0 f xx /2 5 master mode 0 1 1 f xx /2 4 master mode 1 0 0 f xx /2 3 master mode 1 0 1 f xx /2 2 master mode 1 1 0 clock generated by brg3 master mode 1 1 1 external clock (sckn) slave mode 2 to 0 cks2 to cks0 remark f xx : internal system clock frequency n = 0, 1 do7 do6 do5 do4 do3 do2 do1 do0 di7 son (output) sckn (i/o) sin (input) di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 son (output) sckn (i/o) sin (input) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 son (output) sckn (i/o) sin (input) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 son (output) sckn (i/o) sin (input) chapter 10 serial interface function user?s manual u14492ej4v1ud 476 (3) clocked serial interface reception bu ffer registers 0, 1 (sirb0, sirb1) the sirbn register is a 16-bit buffer register that stores receive data (n = 0, 1). when the receive-only mode is set (trmdn bit of csimn register = 0), the recepti on operation is started by reading data from the sirbn register. these registers are read-only, in 16-bit units. in addition to reset input, these registers can also be initialized by clearing (0) the csicaen bit of the csimn register. cautions 1. read the sirbn register only when the 16-bit data length has been set (ccl bit of csimn register = 1). 2. when the single tr ansfer mode has been set (auto bi t of csimn register = 0), perform read operation only in the idle state (csotn bi t of csimn register = 0). if the sirbn register is read during data transfer, the data cannot be guaranteed. 14 sirb 14 13 sirb 13 12 sirb 12 2 sirb 2 3 sirb 3 4 sirb 4 5 sirb 5 6 sirb 6 7 sirb 7 8 sirb 8 9 sirb 9 10 sirb 10 11 sirb 11 15 sirb 15 1 sirb 1 0 sirb 0 sirb0 address fffff902h initial value 0000h 14 sirb 14 13 sirb 13 12 sirb 12 2 sirb 2 3 sirb 3 4 sirb 4 5 sirb 5 6 sirb 6 7 sirb 7 8 sirb 8 9 sirb 9 10 sirb 10 11 sirb 11 15 sirb 15 1 sirb 1 0 sirb 0 sirb1 address fffff912h initial value 0000h bit position bit name function 15 to 0 sirb15 to sirb0 stores receive data. chapter 10 serial interface function user?s manual u14492ej4v1ud 477 (4) clocked serial interface reception buffe r registers l0, l1 (sirbl0, sirbl1) the sirbln register is an 8-bit buffer register that stores receive data (n = 0, 1). when the receive-only mode is set (trmdn bit of csimn register = 0), the recepti on operation is started by reading data from the sirbln register. these registers are read-only, in 8-bit or 1-bit units. in addition to reset input, these registers can also be initialized by clearing (0) the csicaen bit of the csimn register. the sirbln register is the same as t he lower bytes of the sirbn register. cautions 1. read the sirbln register only when the 8-bit data length has been set (ccl bit of csimn register = 0). 2. when the single transfer mode is set ( auto bit of csimn register = 0), perform read operation only in the idle state (csotn bit of cs imn register = 0). if the sirbln register is read during data transfer, th e data cannot be guaranteed. 7 sirb7 sirbl0 6 sirb6 5 sirb5 4 sirb4 3 sirb3 2 sirb2 1 sirb1 0 sirb0 address fffff902h initial value 00h 7 sirb7 sirbl1 6 sirb6 5 sirb5 4 sirb4 3 sirb3 2 sirb2 1 sirb1 0 sirb0 address fffff912h initial value 00h bit position bit name function 7 to 0 sirb7 to sirb0 stores receive data. chapter 10 serial interface function user?s manual u14492ej4v1ud 478 (5) clocked serial interface read-only reception buffer registers 0, 1 (sirbe0, sirbe1) the sirben register is a 16-bit buffer register that stores receive data (n = 0, 1). these registers are read-only, in 16-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csicaen bit of the csimn register. the sirben register is the same as the sirbn register. it is used to read the contents of the sirbn register. cautions 1. the receive operation is not started ev en if data is read fr om the sirben register. 2. the sirben register can be read only if th e 16-bit data length is set (ccl bit of csimn register = 1). 14 sirbe 14 13 sirbe 13 12 sirbe 12 2 sirbe 2 3 sirbe 3 4 sirbe 4 5 sirbe 5 6 sirbe 6 7 sirbe 7 8 sirbe 8 9 sirbe 9 10 sirbe 10 11 sirbe 11 15 sirbe 15 1 sirbe 1 0 sirbe 0 14 sirbe 14 13 sirbe 13 12 sirbe 12 2 sirbe 2 3 sirbe 3 4 sirbe 4 5 sirbe 5 6 sirbe 6 7 sirbe 7 8 sirbe 8 9 sirbe 9 10 sirbe 10 11 sirbe 11 15 sirbe 15 1 sirbe 1 0 sirbe 0 sirbe0 address fffff906h initial value 0000h sirbe1 address fffff916h initial value 0000h bit position bit name function 15 to 0 sirbe15 to sirbe0 stores receive data. chapter 10 serial interface function user?s manual u14492ej4v1ud 479 (6) clocked serial interface read-only reception buffer registers l0, l1 (sirbel0, sirbel1) the sirbeln register is an 8-bit buffer regist er that stores receive data (n = 0, 1). these registers are read-only, in 8-bit or 1-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csicaen bit of the csimn register. the sirbeln register is the same as the sirbln register. it is used to read the contents of the sirbln register. cautions 1. the receive operation is not started ev en if data is read fr om the sirbeln register. 2. the sirbeln register can be read only if th e 8-bit data length has been set (ccl bit of csimn register = 0). 7 sirbe7 sirbel0 6 sirbe6 5 sirbe5 4 sirbe4 3 sirbe3 2 sirbe2 1 sirbe1 0 sirbe0 address fffff906h initial value 00h 7 sirbe7 sirbel1 6 sirbe6 5 sirbe5 4 sirbe4 3 sirbe3 2 sirbe2 1 sirbe1 0 sirbe0 address fffff916h initial value 00h bit position bit name function 7 to 0 sirbe7 to sirbe0 stores receive data. chapter 10 serial interface function user?s manual u14492ej4v1ud 480 (7) clocked serial interface transmission buf fer registers 0, 1 (sotb0, sotb1) the sotbn register is a 16-bit buffer register that stores transmit data (n = 0, 1). when the transmission/reception mode is set (trmdn bit of csimn register = 1), the transmission operation is started by writing data to the sotbn register. these registers can be read/written in 16-bit units. cautions 1. access the sotbn register only when the 16-bit data length is set (ccl bit of csimn register = 1). 2. when the single transfer mode is set (auto bit of csimn register = 0), perform access only in the idle state (csotn bit of csimn re gister = 0). if the sotbn register is accessed during data transfer, th e data cannot be guaranteed. 14 sotb 14 13 sotb 13 12 sotb 12 2 sotb 2 3 sotb 3 4 sotb 4 5 sotb 5 6 sotb 6 7 sotb 7 8 sotb 8 9 sotb 9 10 sotb 10 11 sotb 11 15 sotb 15 1 sotb 1 0 sotb 0 sotb0 address fffff904h initial value 0000h 14 sotb 14 13 sotb 13 12 sotb 12 2 sotb 2 3 sotb 3 4 sotb 4 5 sotb 5 6 sotb 6 7 sotb 7 8 sotb 8 9 sotb 9 10 sotb 10 11 sotb 11 15 sotb 15 1 sotb 1 0 sotb 0 sotb1 address fffff914h initial value 0000h bit position bit name function 15 to 0 sotb15 to sotb0 stores transmit data. chapter 10 serial interface function user?s manual u14492ej4v1ud 481 (8) clocked serial interface transmission buffe r registers l0, l1 (sotbl0, sotbl1) the sotbln register is an 8-bit buffer regist er that stores transmit data (n = 0, 1). when the transmission/reception mode is set (trmdn bit of csimn register = 1), the transmission operation is started by writing data to the sotbln register. these registers can be read/written in 8-bit or 1-bit units. the sotbln register is the same as t he lower bytes of the sotbn register. cautions 1. access the sotbln register only when the 8-bit data length has been set (ccl bit of csimn register = 0). 2. when the single transfer mode is set (auto bit of csimn register = 0), perform access only in the idle state (csotn bit of csimn register = 0). if the sotbln register is accessed during data transfer, the data cannot be guaranteed. 7 sotb7 sotbl0 6 sotb6 5 sotb5 4 sotb4 3 sotb3 2 sotb2 1 sotb1 0 sotb0 address fffff904h initial value 00h 7 sotb7 sotbl1 6 sotb6 5 sotb5 4 sotb4 3 sotb3 2 sotb2 1 sotb1 0 sotb0 address fffff914h initial value 00h bit position bit name function 7 to 0 sotb7 to sotb0 stores transmit data. chapter 10 serial interface function user?s manual u14492ej4v1ud 482 (9) clocked serial interface init ial transmission buffer regist ers 0, 1 (sotbf0, sotbf1) the sotbfn register is a 16-bit bu ffer register that stores initial tr ansmission data in the repeat transfer mode (n = 0, 1). the transmission operation is not started even if data is writt en to the sotbfn register. these registers can be read/written in 16-bit units. caution access the sotbfn register only when the 16-bit data lengt h has been set (ccl bit of csimn register = 1), and only in the idle stat e (csotn bit of csimn register = 0). if the sotbfn register is accessed during data transfer, the da ta cannot be guaranteed. 14 sotbf 14 13 sotbf 13 12 sotbf 12 2 sotbf 2 3 sotbf 3 4 sotbf 4 5 sotbf 5 6 sotbf 6 7 sotbf 7 8 sotbf 8 9 sotbf 9 10 sotbf 10 11 sotbf 11 15 sotbf 15 1 sotbf 1 0 sotbf 0 14 sotbf 14 13 sotbf 13 12 sotbf 12 2 sotbf 2 3 sotbf 3 4 sotbf 4 5 sotbf 5 6 sotbf 6 7 sotbf 7 8 sotbf 8 9 sotbf 9 10 sotbf 10 11 sotbf 11 15 sotbf 15 1 sotbf 1 0 sotbf 0 sotbf0 address fffff908h initial value 0000h sotbf1 address fffff918h initial value 0000h bit position bit name function 15 to 0 sotbf15 to sotbf0 stores initial transmission data in repeat transfer mode. chapter 10 serial interface function user?s manual u14492ej4v1ud 483 (10) clocked serial interface initial transmissi on buffer registers l0, l1 (sotbfl0, sotbfl1) the sotbfln register is an 8-bit bu ffer register that stores initial tr ansmission data in the repeat transfer mode (n = 0, 1). the transmission operation is not started even if data is written to the sotbfln register. these registers can be read/written in 8-bit or 1-bit units. the sotbfln register is the same as t he lower bytes of the sotbfn register. caution access the sotbfln register only when the 8-bit data length has been set (ccl bit of csimn register = 0), and only in the idle stat e (csotn bit of csimn register = 0). if the sotbfln register is accessed during data transfer, the data cannot be guaranteed. 7 sotbf7 sotbfl0 6 sotbf6 5 sotbf5 4 sotbf4 3 sotbf3 2 sotbf2 1 sotbf1 0 sotbf0 address fffff908h initial value 00h 7 sotbf7 sotbfl1 6 sotbf6 5 sotbf5 4 sotbf4 3 sotbf3 2 sotbf2 1 sotbf1 0 sotbf0 address fffff918h initial value 00h bit position bit name function 7 to 0 sotbf7 to sotbf0 stores initial transmission data in repeat transfer mode. chapter 10 serial interface function user?s manual u14492ej4v1ud 484 (11) serial i/o shift re gisters 0, 1 (sio0, sio1) the sion register is a 16-bit shift register that c onverts parallel data into serial data (n = 0, 1). the transfer operation is not started even if the sion register is read. these registers are read-only, in 16-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csicaen bit of the csimn register. caution read the sion register onl y when the 16-bit data length has been set (ccl bit of csimn register = 1), and only in the idle state (cso tn bit of csimn register = 0). if the sion register is read during data transfer, the data cannot be guaranteed. 14 sio14 13 sio13 12 sio12 2 sio2 3 sio3 4 sio4 5 sio5 6 sio6 7 sio7 8 sio8 9 sio9 10 sio10 11 sio11 15 sio15 1 sio1 0 sio0 sio0 address fffff90ah initial value 0000h 14 sio14 13 sio13 12 sio12 2 sio2 3 sio3 4 sio4 5 sio5 6 sio6 7 sio7 8 sio8 9 sio9 10 sio10 11 sio11 15 sio15 1 sio1 0 sio0 sio1 address fffff91ah initial value 0000h bit position bit name function 15 to 0 sio15 to sio0 data is shifted in (reception) or shift ed out (transmission) from the msb or lsb side. chapter 10 serial interface function user?s manual u14492ej4v1ud 485 (12) serial i/o shift registers l0, l1 (siol0, siol1) the sioln register is an 8-bit shift register that c onverts parallel data into serial data (n = 0, 1). the transfer operation is not started even if the s ioln register is read. these registers are read-only, in 8-bit or 1-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csicaen bit of the csimn register. the sioln register is the same as t he lower bytes of the sion register. caution read the sioln register only when the 8-bit data length h as been set (ccl bit of csimn register = 0), and only in the idle state (cso tn bit of csimn register = 0). if the sioln register is read during data transfer, the data cannot be guaranteed. 7 sio7 siol0 6 sio6 5 sio5 4 sio4 3 sio3 2 sio2 1 sio1 0 sio0 7 sio7 6 sio6 5 sio5 4 sio4 3 sio3 2 sio2 1 sio1 0 sio0 address fffff90ah initial value 00h siol1 address fffff91ah initial value 00h bit position bit name function 7 to 0 sio7 to sio0 data is shifted in (reception) or shift ed out (transmission) from the msb or lsb side. chapter 10 serial interface function user?s manual u14492ej4v1ud 486 10.4.4 operation (1) single transfer mode (a) usage in the receive-only mode (trmdn bit of csimn register = 0), transfer is started by reading note 1 the receive data buffer register (sirbn/sirbln) (n = 0, 1). in the transmission/reception mode (t rmdn bit of csimn register = 1), transfer is started by writing note 2 to the transmit data buffer register (sotbn/sotbln). in the slave mode, the operation must be enabled bef orehand (csicaen bit of csimn register = 1). when transfer is started, the valu e of the csotn bit of the csimn register becomes 1 (transmission execution status). upon transfer completion, the transmission/reception co mpletion interrupt (intcs in) is set (1), and the csotn bit is cleared (0). the next dat a transfer request is then waited for. notes 1. when the 16-bit data length (ccl bit of csimn register = 1) has been set, read the sirbn register. when the 8-bit data length (ccl bi t of csimn register = 0) has been set, read the sirbln register. 2. when the 16-bit data length (ccl bit of csimn register = 1) has been set, write to the sotbn register. when the 8-bit data length (ccl bit of csimn register = 0) has been set, write to the sotbln register. caution when the csotn bit of the csimn register = 1, do not manipulate the csin register. chapter 10 serial interface function user?s manual u14492ej4v1ud 487 figure 10-26. timing chart in single transfer mode (1/2) (a) in transmission/recepti on mode, data length: 8 bits , transfer direction: msb first, no interrupt delay, single transfer mode, operation mode: ckp bit = 0, dap bit = 0 01010101 10101010 (55h) (aah) aah aah abh 56h adh 5ah b5h 6ah d5h sckn (i/o) son (output) sin (input) reg_r/w sotbln register sioln register sirbln register csotn bit intcsin interrupt 55h (transmit data) write 55h to sotbln register remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data bu ffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed . chapter 10 serial interface function user?s manual u14492ej4v1ud 488 figure 10-26. timing chart in single transfer mode (2/2) (b) in transmission/reception mode, da ta length: 8 bits, transfer directi on: msb first, no interrupt delay, single transfer mode, operation mode: ckp bit = 0, dap bit = 1 01010101 10101010 aah aah abh 56h adh 5ah b5h 6ah d5h sckn (i/o) son (output) sin (input) reg_r/w sotbln register sioln register sirbln register csotn bit intcsin interrupt (55h) (aah) 55h (transmit data) write 55h to sotbln register remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data bu ffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed . chapter 10 serial interface function user?s manual u14492ej4v1ud 489 (b) clock phase selection the following shows the timing when changing the conditions for clock phase selection (ckp bit of csicn register) and data phase selection (dap bit of csicn register) under the following conditions. ? data length = 8 bits (ccl bit of csimn register = 0) ? first bit of transfer data = msb (dirn bit of csimn register = 0) ? no interrupt request signal delay cont rol (csit bit of csimn register = 0) figure 10-27. timing chart accord ing to clock phase selection (1/2) (a) when ckp bit = 0, dap bit = 0 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 (b) when ckp bit = 1, dap bit = 0 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data bu ffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed . chapter 10 serial interface function user?s manual u14492ej4v1ud 490 figure 10-27. timing chart accord ing to clock phase selection (2/2) (c) when ckp bit = 0, dap bit = 1 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 (d) when ckp bit = 1, dap bit = 1 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data bu ffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed . chapter 10 serial interface function user?s manual u14492ej4v1ud 491 (c) transmission/reception completion interr upt request signals (intcsi0, intcsi1) intcsin is set (1) upon completion of data transmission/reception. caution the delay mode (csit bit = 1) is valid only in the master m ode (bits cks2 to cks0 of the csicn register are not 111b). the delay mode cannot be set when the slave mode is set (bits cks2 to cks0 = 111b). figure 10-28. timing chart of interrupt re quest signal output in delay mode (1/2) (a) when ckp bit = 0, dap bit = 0 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit delay remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data bu ffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed . chapter 10 serial interface function user?s manual u14492ej4v1ud 492 figure 10-28. timing chart of interrupt re quest signal output in delay mode (2/2) (b) when ckp bit = 1, dap bit = 1 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit delay remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data bu ffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed . chapter 10 serial interface function user?s manual u14492ej4v1ud 493 (2) repeat transfer mode (a) usage (receive-only) <1> set the repeat transfer mode (auto bit of csimn r egister = 1) and the receive-only mode (trmdn bit of csimn register = 0). <2> read sirbn register (start transfer with dummy read). <3> wait for transmission/reception comp letion interrupt request (intcsin). <4> when the transmission/reception completion interr upt request (intcsin) has been set (1), read the sirbn register note (reserve next transfer). <5> repeat steps <3> and <4> (n ? 2) times (n: number of transfer data). <6> following output of the last transmission/reception completion inte rrupt request (intcsin), read the sirben register and the sion register note . note when transferring n number of data, receive data is loaded by reading the sirbn register from the first data to the (n ? 2)th data. the (n ? 1)th data is loaded by reading the sirben register, and the nth (last) data is loaded by reading the sion register. chapter 10 serial interface function user?s manual u14492ej4v1ud 494 figure 10-29. repeat transfer (receive-only) timing chart din-1 sckn (i/o) sin (input) son (output) l sioln register sirbln register reg_rd csotn bit intcsin interrupt rq_clr trans_rq din-2 din-1 sirbn (dummy) sirbn (d1) sirbn (d2) sirbn (d3) sirben (d4) sion (d5) < 4 >< 6 > < 4 >< 3 > < 3 > < 4 > < 5 > period during which next transfer can be reserved < 3 > < 2 > < 1 > din-2 din-3 din-4 din-5 din-5 din-3 din-4 remarks 1. n = 0, 1 2. reg_rd: internal signal. this signal indicates that the receive data buffer register (sirbn/ sirbln) has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. in the case of the repeat transfer mode, two transfer r equests are set at the start of the first transfer. following the transmission/reception completion interrupt request (intcsin), trans fer is continued if the sirbn register can be read within the next transfer rese rvation period. if the sirbn register cannot be read, transfer ends and the sirbn register does not receive the new value of the sion register. the last data can be obtained by reading the sion register following completion of the transfer. chapter 10 serial interface function user?s manual u14492ej4v1ud 495 (b) usage (transmission/reception) <1> set the repeat transfer mode (auto bit of csim n register = 1) and the transmission/reception mode (trmdn bit of csimn register = 1). <2> write the first data to the sotbfn register. <3> write the 2nd data to the sotbn register (start transfer). <4> wait for a transmission/reception comp letion interrupt re quest (intcsin). <5> when the transmission/reception completion interru pt request (intcsin) has been set (1), write the next data to the sotbn register (reserve next trans fer), and read the sirbn register to load the receive data. <6> repeat steps <4> and <5> as long as data to be sent remains. <7> wait for the intcsin interrupt. when the interrupt request signal is set (1), read the sirbn register to load the (n ? 1)th receive data (n: number of transfer data). <8> following the last transmission/reception comple tion interrupt request (intcsin), read the sion register to load the nth (last) receive data. chapter 10 serial interface function user?s manual u14492ej4v1ud 496 figure 10-30. repeat transfer (t ransmission/reception) timing chart dout-1 dout-1 sckn (i/o) son (output) sin (input) sotbfln register sotbln register sioln register sirbln register reg_wr reg_rd csotn bit intcsin interrupt rq_clr trans_rq dout-2 dout-3 dout-4 dout-5 dout-2 dout-3 dout-4 dout-5 din-1 din-1 sotbfn (d1) sotbn (d2) sotbn (d3) sotbn (d4) sotbn (d5) sirbn (d1) sirbn (d2) < 5 >< 7 >< 8 > < 4 > < 5 > < 4 > < 6 > period during which next transfer can be reserved < 5 > < 4 > < 3 > < 2 > < 1 > sirbn (d3) sirbn (d4) sion (d5) din-2 din-3 din-4 din-5 din-2 din-3 din-4 din-5 remarks 1. n = 0, 1 2. reg_wr: internal signal. this signal indicates that the transmit data buffer register (sotbn/ sotbln) has been written. reg_rd: internal signal. this signal indicates that the receive data buffer register (sirbn/ sirbln) has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. in the case of the repeat transfer mode, two transfer r equests are set at the start of the first transfer. following the transmission/reception completion interrupt request (intcsin), trans fer is continued if the sotbn register can be writt en within the next transfer reservation peri od. if the sotbn register cannot be written, transfer ends and the si rbn register does not receive the ne w value of the sion register. the last receive data can be obtained by reading the sion register following completion of the transfer. chapter 10 serial interface function user?s manual u14492ej4v1ud 497 (c) next transfer reservation period in the repeat transfer mode, the next transfer must be prepared with the period shown in figure 10-31. figure 10-31. timing chart of next transfer reservation period (1/2) (a) when data length: 8 bits, operati on mode: ckp bit = 0, dap bit = 0 sckn (i/o) intcsin interrupt reservation period: 7 sckn cycles (b) when data length: 16 bits, opera tion mode: ckp bit = 0, dap bit = 0 sckn (i/o) intcsin interrupt reservation period: 15 sckn cycles remark n = 0, 1 chapter 10 serial interface function user?s manual u14492ej4v1ud 498 figure 10-31. timing chart of next transfer reservation period (2/2) (c) when data length: 8 bits, opera tion mode: ckp bit = 0, dap bit = 1 sckn (i/o) intcsin interrupt reservation period: 6.5 sckn cycles (d) when data length: 16 bits, opera tion mode: ckp bit = 0, dap bit = 1 sckn (i/o) intcsin interrupt reservation period: 14.5 sckn cycles remark n = 0, 1 chapter 10 serial interface function user?s manual u14492ej4v1ud 499 (d) cautions to continue repeat transfers, it is necessary to eith er read the sirbn register or write to the sotbn register during the transfer reservation period. if access is performed to the sirbn register or the sotbn register when the transfer reservation period is over, the following occurs. (i) in case of contention between transf er request clear and register access since request cancellation has higher priority, t he next transfer request is ignored. therefore, transfer is interrupted, and normal data transfer cannot be performed. figure 10-32. transfer request clea r and register access contention sckn (i/o) intcsin interrupt rq_clr reg_r/w transfer reservation period remarks 1. n = 0, 1 2. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indicates that the receive data buffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed. chapter 10 serial interface function user?s manual u14492ej4v1ud 500 (ii) in case of contention between in terrupt request and register access since continuous transfer has stopped once, executed as a new repeat transfer. in the slave mode, a bit phase erro r transfer error results (refer to figure 10-33 ). in the transmission/reception mode, the value of th e sotbfn register is retransmitted, and illegal data is sent. figure 10-33. interrupt request and register access contention sckn (i/o) intcsin interrupt rq_clr reg_r/w transfer reservation period 01 234 remarks 1. n = 0, 1 2. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indi cates that receive data buffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed. chapter 10 serial interface function user?s manual u14492ej4v1ud 501 10.4.5 output pins (1) sckn pin when the csin operation is disabled (csicaen bit of cs imn register = 0), the sckn pin output status is as follows (n = 0, 1). table 10-9. sckn pin output status ckp cks2 cks1 cks0 sckn pin output 0 don?t care don?t care don?t care fixed to high level 1 1 1 fixed to high level 1 other than above fixed to low level remarks 1. n = 0, 1 2. when any of bits ckp and cks2 to cks0 of the csicn register is overwritten, the sckn pin output changes. (2) son pin when the csin operation is disabled (csicaen bit of cs imn register = 0), the son pin output status is as follows (n = 0, 1). table 10-10. son pin output status trmdn dap auto ccl dirn son pin output 0 don?t care don?t care don?t care don?t care fixed to low level 0 don?t care don?t care don?t care so latch value (low level) 0 sotb7 value 0 1 sotb0 value 0 sotb15 value 0 1 1 sotb0 value 0 sotbf7 value 0 1 sotbf0 value 0 sotbf15 value 1 1 1 1 1 sotbf0 value remarks 1. n = 0, 1 2. when any of bits trmdn, ccl, dirn, and auto of the csimn register or dap bit of the csicn register is overwritten, the son pin output changes. 3. sotbm: bit m of sotbn register (m = 0, 7, 15) 4. sotbfm: bit m of sotbfn register (m = 0, 7, 15) chapter 10 serial interface function user?s manual u14492ej4v1ud 502 10.4.6 dedicated baud ra te generator 3 (brg3) (1) configuration of baud rate generator 3 (brg3) the csi0 and csi1 serial clocks can be selected from the dedicated baud rate generator output or internal system clock (f xx ). the serial clock source is specifi ed with registers csic0 and csic1. if dedicated baud rate generator output is specifi ed, brg3 is selected as the clock source. since the same serial clock can be shared for transmi ssion and reception, baud rate is the same for the transmission/reception. figure 10-34. block diagram of baud rate generator 3 (brg3) bgcs1, bgcs0 prscm3 match detector 1/2 csin 8-bit timer counter f xx /4 f xx /8 f xx /16 f xx /32 selector remark f xx : internal system clock n = 0, 1 chapter 10 serial interface function user?s manual u14492ej4v1ud 503 (2) dedicated baud rate generator 3 (brg3) brg3 is configured of an 8-bit timer counter that gen erates the baud rate signal, a prescaler mode register 3 (prsm3) that controls baud rate signal generation, a prescaler compare register 3 (prscm3) that sets the value of the 8-bit timer counter, and a prescaler. (a) input clock the internal system clock (f xx ) is input to brg3. (b) prescaler mode register 3 (prsm3) the prsm3 register controls generation of the csi0 and csi1 baud rate signals. this register can be read/written in 8-bit or 1-bit units. cautions 1. do not change the values of th e bgcs1 and bgcs0 bits during transmission/ reception operation. 2. set the prsm3 register prior to setting the csicaen bit of the csimn register to 1 (n = 0, 1). 7 0 prsm3 6 0 5 0 4 ce 3 0 2 0 1 bgcs1 0 bgcs0 address fffff920h initial value 00h bit position bit name function 4 ce enables baud rate counter operation. 0: stop baud rate counter operation and fix baud rate output signal to 0. 1: enable baud rate counter operation and start baud rate output operation. selects count clock for baud rate counter. bgcs1 bgcs0 count clock selection 0 0 f xx /4 0 1 f xx /8 1 0 f xx /16 1, 0 bgcs1, bgcs0 1 1 f xx /32 remark f xx : internal system clock chapter 10 serial interface function user?s manual u14492ej4v1ud 504 (c) prescaler compare register 3 (prscm3) prscm3 is an 8-bit compare register that sets the value of the 8-bit timer counter. this register can be read/written in 8-bit units. cautions 1. the internal timer counter is cleare d by writing to the prsm 3 register. therefore, do not write to the prscm3 re gister during transmission. 2. set the prscm3 register pr ior to setting the csicaen bit of the csimn register to 1. if the contents of the prscm3 register are overwritten when the value of the csicaen bit is 1, the cycle of the ba ud rate signal is not guaranteed. 7 prscm7 prscm3 6 prscm6 5 prscm5 4 prscm4 3 prscm3 2 prscm2 1 prscm1 0 prscm0 address fffff922h initial value 00h (d) baud rate signal cycle the baud rate signal cycle is calculated as follows. ? when setting value of prscm3 register is 00h (cycle of signal selected with bits bgcs1, bgcs0 of prsm3 register) 256 2 ? in cases other than above (cycle of signal selected with bits bgcs1, bgcs0 of prsm3 register) (setting value of prscm3 register) 2 chapter 10 serial interface function user?s manual u14492ej4v1ud 505 (e) baud rate setting value table 10-11. baud rate generator setting data (a) when f xx = 32 mhz bgcs1 bgcs0 prscm register value clock (hz) 0 0 1 4000000 0 0 2 2000000 0 0 4 1000000 0 0 8 500000 0 0 16 250000 0 0 40 100000 0 0 80 50000 0 0 160 25000 0 1 200 10000 1 0 200 5000 (b) when f xx = 40 mhz bgcs1 bgcs0 prscm register value clock (hz) 0 0 2 2500000 0 0 5 1000000 0 0 10 500000 0 0 20 250000 0 0 50 100000 0 0 100 50000 0 0 200 25000 0 1 250 10000 1 0 250 5000 (c) when f xx = 50 mhz bgcs1 bgcs0 prscm register value clock (hz) 0 0 2 3125000 0 0 4 1562500 0 0 5 1250000 0 0 10 625000 0 0 25 250000 0 0 50 125000 0 0 125 50000 0 0 250 25000 0 1 250 12500 1 0 250 6250 caution set the transfer cl ock so that it does not fall below the minimum value of 200 ns of the sckn cycle (t cysk1 ) prescribed in the elect rical specifications. 506 user?s manual u14492ej4v1ud chapter 11 fcan controller the v850e/ia1 features a 1 channel on-ch ip fcan (full controller area network) controller that complies with the can specification ver. 2.0, partb active. 11.1 function overview table 11-1 presents an overview of v850e/ia1 functions. table 11-1. overview of functions function description protocol can protocol ver. 2.0, partb active (standard and extended frame transmission/reception) baud rate maximum 1 mbps (during 16 mhz clock input) data storage ? allocated to common access-enabled ram area ? ram that is mapped to an unused message byte can be used for cpu processing or other processing mask functions ? four ? global masks and local masks can be used without distinction message configuration can be declared as transmit or receive messages no. of messages 32 message storage method ? storage to reception buffer corresponding to id ? storage to buffer specified by receive mask function remote reception ? remote frames can be received in either t he receive message buffer or the transmit message buffer ? if a remote frame is received by a transmit mess age buffer, there is a choice between having the remote request processed by the cpu or starting the auto transmit function. remote transmission the remote frame can be sent either by setting the transmit message? s rtr bit (m_ctrln register) or by setting the receive message?s send request. time stamp function a time stamp function can be set for receive messages and transmit messages. diagnostic functions ? read-enabled error counter is provided. ? ?valid protocol operation flag? is pr ovided for verification of bus connections. ? receive-only mode (with auto baud rate detection) is provided. ? diagnostic processing mode is provided. low-power mode ? can sleep mode (wake up function using can bus is enabled) ? can stop mode (wake up functi on using can bus is disabled) remark n = 00 to 31 chapter 11 fcan controller 507 user?s manual u14492ej4v1ud 11.2 configuration fcan is composed of the following four blocks. (1) npb interface this functional block provides an npb (nec peripheral i/o bus) interface as a means of transmitting and receiving signals. (2) mac (memory access controller) this functional block controls access to the can module and to the can ram within the fcan. (3) can module this functional block is involved in the operati on of the can protocol layer and its related settings. (4) can ram this is the can memory functional block, which is used to store message ids, message data, etc. chapter 11 fcan controller 508 user?s manual u14492ej4v1ud figure 11-1. blo ck diagram of fcan cpu fcan controller can ram npb (nec peripheral i/o bus) mac (memory access controller) npb interface can module interrupt request intcrec intctrx intcerr intcmac message buffer 0 message buffer 1 message buffer 2 message buffer 3 message buffer 31 cmask0 cmask1 cmask2 cmask3 ... ctxd crxd can_h can_l can transceiver can bus chapter 11 fcan controller 509 user?s manual u14492ej4v1ud 11.3 configuration of messages and buffers table 11-2. configuration of messages and buffers address note (m = 2, 6, a, e) register name address note (m = 2, 6, a, e) register name xxxxm800h to xxxxm81fh message buffer 0 field x xxxma00h to xxxxma1fh message buffer 16 field xxxxm820h to xxxxm83fh message buffer 1 field x xxxma20h to xxxxma3fh message buffer 17 field xxxxm840h to xxxxm85fh message buffer 2 field x xxxma40h to xxxxma5fh message buffer 18 field xxxxm860h to xxxxm87fh message buffer 3 field xxxxma60h to xxxxma7f h message buffer 19 field xxxxm880h to xxxxm89fh message buffer 4 field x xxxma80h to xxxxma9fh message buffer 20 field xxxxm8a0h to xxxxm8bf h message buffer 5 field xxxxmaa0h to xxxxmabfh message buffer 21 field xxxxm8c0h to xxxxm8df h message buffer 6 field xxxxmac0h to xxxxmadfh message buffer 22 field xxxxm8e0h to xxxxm8ffh message buffer 7 field xxxxmae0h to xxxxmaffh message buffer 23 field xxxxm900h to xxxxm91fh message buffer 8 field x xxxmb00h to xxxxmb1fh message buffer 24 field xxxxm920h to xxxxm93fh message buffer 9 field x xxxmb20h to xxxxmb3fh message buffer 25 field xxxxm940h to xxxxm95fh message buffer 10 field x xxxmb40h to xxxxmb5fh message buffer 26 field xxxxm960h to xxxxm97fh message buffer 11 field x xxxmb60h to xxxxmb7fh message buffer 27 field xxxxm980h to xxxxm99fh message buffer 12 field x xxxmb80h to xxxxmb9fh message buffer 28 field xxxxm9a0h to xxxxm9bf h message buffer 13 field xxxxmba0h to xxxxmbbfh message buffer 29 field xxxxm9c0h to xxxxm9df h message buffer 14 field xxxxmbc0h to xxxxmbdfh message buffer 30 field xxxxm9e0h to xxxxm9ffh message buffer 15 field xxxxmbe0h to xxxxmbffh message buffer 31 field note can message buffer registers can be allocated to the xxxx addresses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. caution when emulating the fcan c ontroller using the in-circuit emul ator (ie-v850e-mc or ie-703116-mc- em1), perform the following settings in the confi guration screen that app ears when the debugger is started. ? set the start address of the programmable peripheral i/o area that is set using the bpc register to the programable i/o area field. ? map the programmable peripheral i/o area as ?t arget? or ?emulation ram? in the memory mapping field. remark for details of message buffers, see 3.4.9 programmable peripheral i/o registers . chapter 11 fcan controller 510 user?s manual u14492ej4v1ud 11.4 time stamp function the fcan controller supports a time stamp function. this function is needed to build a global time system. the time stamp function is implemented usin g a 16-bit free-running time stamp counter. two types of time stamp function can be selected for mess age reception in the fcan controller. use bit 3 (tmr) of the can1 control register (c1ctrl) to set the desired time stamp function. when the tmr bit is 0, the time stamp counter value is captured after the sof is detected on the can bus (see figure 11-2 ) and when the tmr bit is 1, the time stamp counter value is captured after the eof is detected on the can bus (a valid message is confirmed) (see figure 11-3 ). figure 11-2. time stamp function setting for message reception (when c1 ctrl register?s tmr bit = 0) message ack field eof sof <2> <1> time stamp counter temporary buffer m_timen can message buffer n chapter 11 fcan controller 511 user?s manual u14492ej4v1ud figure 11-3. time stamp function setting for message reception (when c1 ctrl register?s tmr bit = 1) message ack field eof sof <1> time stamp counter m_timen can message buffer n chapter 11 fcan controller 512 user?s manual u14492ej4v1ud figure 11-4. time stamp function se tting for message transmission (when m_ctrl register?s ats bit = 1) message ack field eof sof <2> <1> time stamp counter temporary buffer chapter 11 fcan controller 513 user?s manual u14492ej4v1ud 11.5 message processing a modular system is used for the fcan controller. c onsequently, messages can be placed at any location within the message area. the messages can be linked to mask functions that are in turn linked to can modules. 11.5.1 message transmission the fcan system is a multiplexed communication system . the priority of message transmission within this system is determined based on message identifiers (ids). to facilitate communication processing by application software when there are several messages awaiting transmission, the can module uses hardware to check th e message ids and automatically determine whether or not linked messages are prioritized. this eliminates the need for software-based priority control. in addition, the priority at transmission can be cont rolled by setting the pbb bit of the c1def register. ? when the pbb bit is set to 0 (see figure 11-5 ) transmission priority is controlled by the identifier (id). the number note of messages waiting to be transmitted in the me ssage buffer that can be set simultaneously by application software is up to five messages per can module. note the number of message buffers when the trq bi t of the m_stat00 to m_ stat31 registers = 1. ? when the pbb bit is set to 1 (see figure 11-6 ) transmission priority is controlled by the message numbers. the number of messages waiting to be transmitted in the message buffer is not limited by the application software. chapter 11 fcan controller 514 user?s manual u14492ej4v1ud figure 11-5. message processing example (when pbb bit = 0) message no. can module transmits messages in the following sequence. message waiting to be transmitted id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 6 2. message 1 3. message 8 4. message 5 5. message 2 figure 11-6. message processing example (when pbb bit = 1) message no. can module transmits messages in the following sequence. message waiting to be transmitted id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 1 2. message 2 3. message 5 4. message 6 5. message 8 chapter 11 fcan controller 515 user?s manual u14492ej4v1ud 11.5.2 message reception when two or more message buffers of the can module receive a message, the storage priority of the received messages is as follows (the storage priority diffe rs between data frames and remote frames). table 11-4. storage priority for data frame reception priority conditions 2 (high) unmasked message buffer 3 message buffer linked to mask 0 4 message buffer linked to mask 1 5 message buffer linked to mask 2 6 (low) message buffer linked to mask 3 table 11-5. storage priority for remote frame reception priority conditions 1 (high) transmit message buffer 2 unmasked message buffer 3 message buffer linked to mask 0 4 message buffer linked to mask 1 5 message buffer linked to mask 2 6 (low) message buffer linked to mask 3 a message (data frame or remote frame) is always stored in a receive message buffer with a higher priority, not in a receive buffer with a lower priority. for example, when the unmasked receive message buffer and the message buffer linked to mask 0 have the same id, a message is always stored in the unmasked receive message buffer even if the unmasked receive message buffer has already received a message. when two or more message buffers with the same priority exis t in the same can module, the priority is as follows. table 11-6. priority of same priority level priority condition 1 (high) dn bit of m_stat register is not set (1) 2 (low) dn bit of m_stat register is set (1) when two or more message buffers with the same priority exist, the message buffer with the smaller message number takes precedence. also, when two or more message buffers with the same id exist, the message buffer with the smaller message number takes precedence. chapter 11 fcan controller 516 user?s manual u14492ej4v1ud 11.6 mask function a mask linkage function can be defined for each received message. this means that there is no need to dist inguish between local masks and global masks. when the mask function is used, the received message?s id entifier is compared with the message buffer?s identifier and the message can be stored in the defined message buffer regardless of whether the mask sets ?0? or ?1? as a result of the comparison. when the mask function is operating, a bit whose value is defined as ?1? by masking is not subject to the abovementioned comparison between the received message? s identifier and the message buffer?s identifier. however, this comparison is performed for any bit whose value is defined as ?0? by masking. for example, let us assume that all messages that have a standard-format id in which bits id27 to id25 = 0 and bits id24 and id22 = 1 are to be stored in message buffer 14 (which is linked by mask 1 as explained in 11.10 (7) ). the procedure for this example is shown below. <1> identifier bits to be stored in message buffer id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x 0 0 0 1 x 1 x x x x remark x = don?t care messages with an id in which bits id27 to id25 = 0 and bits id24 and id22 = 1 are registered (initialized) in message buffer 14 (see 11.10 (6) ). <2> identifier bits set to message buffer 14 (example) (using can message id registers l14 and h14 (m_idl14 and m_idh14)) id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 0 0 0 0 1 0 1 0 0 0 0 id17 id16 id15 id14 id13 id12 id11 id10 id9 id8 id7 0 0 0 0 0 0 0 0 0 0 0 id6 id5 id4 id3 id2 id1 id0 0 0 0 0 0 0 0 message buffer 14 is set as a standard-format identifier linked to mask 1 (see 11.10 (7) ). chapter 11 fcan controller 517 user?s manual u14492ej4v1ud <3> mask setting for mask 1 (example) (using can1 address mask 1 registers l and h (c1maskl1 and c1maskh1)) cmid28 cmid27 cmid26 cmid25 cmid24 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 1 0 0 0 0 1 0 1 1 1 1 cmid17 cmid16 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 cmid7 1 1 1 1 1 1 1 1 1 1 1 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 1 1 1 1 1 1 1 remark 1: do not compare (mask) 0: compare values are written to mask 1 (see 11.10 (19) ), bits cmid27 to cmid24 and cmid22 are set to 0 and bits cmid28, cmid23, and cmid21 to cmid0 are set to 1. chapter 11 fcan controller 518 user?s manual u14492ej4v1ud 11.7 protocol fcan is a high-speed multiplex communication protocol designed to enable real-time communications in automotive applications. the can specif ication is generally divided into two layers (physical layer and data link layer). the data link layer is further divided into logical link control and medium access c ontrol. the composition of these layers is illustrated below. figure 11-7. composition of layers application layer physical layer data link layer logical link control (llc) medium access control (mac) not applicable message and status handling rules protocol rules signal level and bit expression rules higher lower 11.7.1 protocol mode function (1) standard format mode 2048 different identifiers can be set in this mode. the standard format mode uses 11-bit identifiers, whic h means that it can handle up to 2032 messages. (2) extended format mode this mode is used to extend the num ber of identifiers that can be set. while the standard format mode uses 11-bit identifiers , the extended format mode uses 29-bit (11 bits + 18 bits) identifiers which expands the amount of messages that can be handled to 2048 2 18 messages. extended format mode is set when ?recessive (r): recessive in wired or? is set for both the srr and ide bits in the arbitration field. when an extended format mode message and a standard format mode remote frame are transmitted at the same time, the node that trans mitted the extended format mode message is set to receive mode. chapter 11 fcan controller 519 user?s manual u14492ej4v1ud 11.7.2 message formats four types of frames are used in can protocol messages. the output condi tions for each type of frame are as follows. data frame: frame used for transmit data remote frame: frame used for transmit requests from receiving side error frame: frame that is output when an error has been detected overload frame: frame that is output when receiving side is not ready remark dominant (d): domi nant in wired or recessive (r): recessive in wired or in the figure shown below, (d) = 0 and (r) = 1. (1) data frame and remote frame <1> data frame a data frame is the frame used for transmit data. this frame is composed of seven fields. figure 11-8. data frame r d interframe space end of frame (eof) ack field crc field data field control field arbitration field start of frame (sof) data frame <1> <2> <3> <4> <5> <6> <7> <8> chapter 11 fcan controller 520 user?s manual u14492ej4v1ud <2> remote frame a remote frame is transmitted when the receiving node issues a transmit request. a remote frame is similar to a data frame, except that the ?data field? is deleted and the rtr bit of the ?arbitration fiel d? is recessive. figure 11-9. remote frame r d interframe space end of frame (eof) ack field crc field control field arbitration field start of frame (sof) remote frame <1> <2> <3> <5> <6> <7> <8> remark the data field is not transferred even if the cont rol field?s data length code is not ?0000b?. (2) description of fields <1> start of frame (sof) the start of frame field is a 1-bit dominant (d) field that is located at the start of a data frame or remote frame. figure 11-10. start of frame (sof) r d 1 bit start of frame (interframe space or bus idle) (arbitration field) the start of frame field starts when the bus line level changes. when ?dominant (d)? is detected at t he sample point, reception continues. when ?recessive (r)? is detected at the sample point, bus idle mode is set. chapter 11 fcan controller 521 user?s manual u14492ej4v1ud <2> arbitration field the arbitration field is used to set the priority , data frame or remote frame, and protocol mode. this field includes an identifier, frame setting (rtr bit), and protocol mode setting bit. figure 11-11. arbitration field (in standard format mode) r d ide (r1) r0 rtr identifier arbitration field (control field) (11 bits) id28 id18 (1 bit) (1 bit) figure 11-12. arbitration field (in extended format mode) r d r1 r0 rtr ide srr identifier note identifier arbitration field (control field) (11 bits) (18 bits) id28 id18 id17 id0 (1 bit) (1 bit) (1 bit) note setting the higher 7 bits of the identifier as 1111111b is prohibited. cautions 1. id28 to id0 are identifier bits. 2. identifier bits are tr ansferred in msb-first order. table 11-7. rtr bit settings frame type rtr bit data frame dominant remote frame recessive table 11-8. protocol mode setting an d number of identifier (id) bits protocol mode srr bit ide bit no. of bits standard format mode none dominant (d) 11 bits extended format mode recessive (r) recessive (r) 29 bits chapter 11 fcan controller 522 user?s manual u14492ej4v1ud <3> control field the control field sets ?n? as the number of da ta bytes in the data field (n = 0 to 8). r1 and r0 are fixed as dominant (d). the data leng th code bits (dlc3 to dlc0) set the byte count. remark dlc3 to dlc0: bits 3 to 0 in can message data length registers 00 to 31 (m_dlc00 to m_dlc31) (see 11.10 (2) ) figure 11-13. control field r d r1 (ide) r0 rtr dlc2 dlc3 dlc1 dlc0 control field (data field) (arbitration field) in standard format mode, the ar bitration field?s ide bit is the same bit as the r1 bit. table 11-9. data length code settings data length code dlc3 dlc2 dlc1 dlc0 data byte count 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes other than above 8 bytes regardless of the values of dlc3 to dlc0 caution in the remote frame, there is no da ta field even if the data length code is not 0000b. chapter 11 fcan controller 523 user?s manual u14492ej4v1ud <4> data field the data field contains the amount of data set by the control field. up to 8 units of data can be set. remark data units in the data field are each 8 bits long and are ordered msb first. figure 11-14. data field r d data (8 bits) data (8 bits) data field (crc field) (control field) <5> crc field the crc field is a 16-bit field that is used to check for errors in transmit data. it includes a 15-bit crc sequence and a 1-bit crc delimiter. figure 11-15. crc field r d crc sequence crc delimiter (1 bit) (15 bits) crc field (ack field) (data field, control field) the polynomial p(x) used to generate the 15-bit crc seq uence is expressed as: x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1 transmitting node: no bit stuffing in start of frame, arbitration field, control field, or data field: the transferred crc sequence is calculat ed entirely from basic data bits. receiving node: the crc sequence calculated using da ta bits that exclude the stuffing bits in the receive data is compared with the crc sequence in the crc field. if the two crc sequences do not match, the node is passed to an error frame. chapter 11 fcan controller 524 user?s manual u14492ej4v1ud <6> ack field the ack field is used to confirm normal reception. it includes a 1-bit ack slot and a 1-bit ack delimiter. figure 11-16. ack field r d ack slot (1 bit) ack delimiter (1 bit) ack field (end of frame) (crc field) the receiving node outputs the following depending on whether or not an error is detected between the start of frame field and the crc field. if an error is detected: ack slot = recessive (r) if no error is detected: ack slot = dominant (d) the transmitting node outputs two ?recessive (r)? bits and confirms the receiving node?s receive status. <7> end of frame (eof) the end of frame field indicates the end of transmission or reception. it includes 7 ?recessive (r)? bits. figure 11-17. end of frame (eof) r d end of frame (7 bits) (interframe space or overload frame) (ack field) chapter 11 fcan controller 525 user?s manual u14492ej4v1ud <8> interframe space the interframe space is inserted after the data fram e, remote frame, error frame, and overload frame to separate one frame from the next one. error active node when the bus is idle, transmit enable mode is set for each node. transmission then starts from a node that has received a transmit request. if the node is an error active node, the interframe space is composed of a 3- or 2-bit intermission field and bus idle field. error passive node after an 8-bit bus idle field, transmit enable mode is set. receive mode is set if a transmission starts from a different node in bus idle mode. the error passive node is composed of an intermission field, suspend transmission field, and bus idle field. figure 11-18. interframe space (a) error active r d interframe space intermission (3 or 2 bits) bus idle (0 or more bits) (frame) (frame) (b) error passive r d interframe space intermission (3 or 2 bits) suspend transmission (8 bits) bus idle (0 or more bits) (frame) (frame) bit length of intermission when transmission is pending, transmission is resumed after a 3-bit intermission. when receiving, the receive operation starts after only two bits. bus idle this mode is set when no nodes are using any buses. suspend transmission this is an 8-bit recessive (r) field that is trans mitted from a node that is in error passive mode. chapter 11 fcan controller 526 user?s manual u14492ej4v1ud table 11-10. operation when third bi t of intermission is ?dominant (d)? transmit status operation no pending transmissions rece ive operation is performed when start of frame output by other node is detected. pending transmission exists identifier is tran smitted when start of frame output by local node is detected. <9> error frame an error frame is used to output from a node in which an error has been detected. when a passive error flag is being output, if ther e is ?dominant (d)? output from another node, the passive error flag does not end until 6 consecutive bits are detected on the same level. if the bit following the 6 consecutive ?recessive (r)? bits is ?dominant (d)?, the error frame ends when the next ?recessive (r)? bit is detected. figure 11-19. error frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame error delimiter error flag error flag error bit error frame no name bit count definition error active node consecutive output of 6 ?dominant (d)? bits <1> error flag 6 error passive node consecutive output of 6 ?recessive (r)? bits <2> error flag 0 to 6 a node that receives an error flag is a node in which bit stuffing errors are detected, after which an error flag is output. <3> error delimiter 8 8 consecutive ?recessive (r)? bits are output. if a ?dominant (d)? bit is detected as the eighth bit, an overload frame is sent starting at the next bit. <4> error bit ? this bit is output following the bit where an error occurred. if the error is a crc error, it is output following an ack delimiter. <5> interframe space or overload frame 3/10 20 max. an interframe space or overload frame starts from here. chapter 11 fcan controller 527 user?s manual u14492ej4v1ud <10> overload frame an overload frame is output starting from the first bit in an intermission in cases where the receiving node is not yet ready to receive. if a bit error is detected in intermission mode, it is output starting from the bit following the bit where the bit error was detected. figure 11-20. overload frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame overload delimiter overload flag (node n) overload flag (node m) frame overload frame no name bit count definition <1> overload flag starting from node m 6 consecutive output of 6 ?dominant (d)? bits. output when node m is not ready to receive. <2> overload flag starting from node n 0 to 6 node n, which has received an overload flag in the interframe space, outputs an overload flag. <3> overload delimiter 8 8 consecutive ?recessive (r)? bits are output. if a ?dominant (d)? bit is detected as the eighth bit, an overload frame is sent starting at the next bit. <4> frame ? output following an end of frame, error delimiter, or overload delimiter. <5> interframe space or overload frame 3/10 20 max. an interframe space or overload frame starts from here. remark n m chapter 11 fcan controller 528 user?s manual u14492ej4v1ud 11.8 functions 11.8.1 determination of bus priority (1) when one node has started transmitting in bus idle mode, the node that outputs data first starts transmission. (2) when several nodes have started transmitting the node that has the longest string of consecutive ?dominant (d)? bits starting from the first bit in the arbitration field has top priority for bus access (?dom inant (d)? bits take precedence due to wired or bus arbitration). the transmitting node compares the arbitration fi eld which it has output and the bus data level. table 11-11. determinat ion of bus priority matched levels transmission continues mismatched levels when a mismatch is detected, data output stops at the next bit, and the operation switches to receiving. (3) priority between data frame and remote frame if a bus conflict occurs between a data frame and a remo te frame, the data frame takes priority because its last bit (rtr) is ?dominant (d)?. 11.8.2 bit stuffing bit stuffing is when one bit of inverted data is added for resynchronization to prevent burst errors when the same level is maintained for five consecutive bits. table 11-12. bit stuffing transmit when transmitting data frames and remote fram es, if the same level is maintained for five bits between the start of frame and crc fields, one bit of data whose level is inverted from the previous level is inserted before the next bit. receive when receiving data frames and remote frames, if the same level is maintained for five bits between the start of frame and crc fields, the ne xt bit of data is deleted before receiving is resumed. 11.8.3 multi-master since bus priority is determined based on the ident ifier, any node can be used as the bus master. 11.8.4 multi-cast even when there is only one transmitting node, the same i dentifier can be set for several nodes, so that the same data can be received by several nodes at the same time. chapter 11 fcan controller 529 user?s manual u14492ej4v1ud 11.8.5 can sleep mode/can stop mode function the can sleep mode/can stop mode function is able to set the fcan controller to sleep (standby) mode to reduce power consumption. the can sleep mode is set via the procedure stipulated in the can specification. t he can sleep mode can be set to wake up by the bus operation, howeve r the can stop mode cannot be set to wake up by the bus operation (this is controlled via cpu access). 11.8.6 error control function (1) types of errors table 11-13. types of errors description of error detected status error type detection method detection condition transmit/ receive field/frame bit error comparison of output level and bus level (excludes stuff bits) mismatch between levels transmitting/ receiving nodes bits outputting data on bus in start of frame to end of frame, error frame, or overload frame stuff error use stuff bits to check receive data six consecutive bits of same-level data transmitting/ receiving nodes start of frame to crc sequence crc error comparison of crc generated from receive data and received crc sequence crc mismatch receiving node start of frame to data field form error check fixed-format field/frame detection of inverted fixed format receiving node ? crc delimiter ? ack field ? end of frame ? error frame ? overload frame ack error use transmitting node to check ack slot use ack slot to detect recessive transmitting node ack slot (2) error frame output timing table 11-14. error frame output timing error type output timing bit error, stuff error, form error, ack error error frame is output at the next bit following the bit where error was detected crc error error frame is output at the next bit following the ack delimiter (3) handling of errors the transmitting node retransmits the data frame or re mote frame after the error frame has been transmitted. chapter 11 fcan controller 530 user?s manual u14492ej4v1ud (4) error statuses (a) types of error statuses the three types of error statuses are listed below. error active error passive bus off error status is controlled by the transmit error counter and receive error counter (see 11.10 (23) can1 error count register (c1erc) ). the various error statuses are categorized according to their error counter values. the error flags used to output error statuses differ between transmit and receive operations. when the error counter value reaches 96 or more, the bus status must be tested since the bus may become seriously damaged. during startup, if only one node is active, the e rror frame and data are repeatedly resent because no ack is returned even data has been transmitted. in such cases, bus off mode cannot be set. even if the node that is sending the transmit message repeatedly experiences an error status, bus off mode cannot be set. table 11-15. types of error statuses error status type operation error c ounter value type of output error flag error active transmit/ receive 0 to 127 active error flag (6 consecutive ?dominant (d)? bits) transmit 128 to 255 error passive receive 128 or more passive error flag (6 consecutive ?recessive (r)? bits) bus off transmit 256 or more transfer is not possible. when a string of at least 11 consecutive ?recessive (r)? bits occurs 128 times, the error counter is zero-cleared and the error active status can be resumed. chapter 11 fcan controller 531 user?s manual u14492ej4v1ud (b) error counter the error counter value is incremented each time an error occurs and is decremented when a transmit or receive operation ends normally. t he count-up/count-down timing occurs at the first bit of the error delimiter. table 11-16. error counter status transmit error counter (tec7 to tec0) receive error counter (rec7 to rec0) receiving node has detected an error (except for bit errors that occur in an active error flag or overload flag) no change +1 ?dominant (d)? is detected following error frame?s error flag output by the receiving node no change +8 transmitting node has sent an error flag [when error counter = 0] <1> when an ack error was detected during error passive status and a ?dominant (d)? was not detected during passive error flag output <2> when a stuff error occurs in the arbitration field +8 no change detection of bit error during output of active error flag or overload flag (transmitting node wi th error active status) +8 no change detection of bit error during output of active error flag or overload flag (receiving node with error active status) no change +8 14 consecutive ?dominant (d)? bits were detected from the start of each node?s active error flag or overload flag, followed by detection of eight consecutive dominant bits. each node has detected eight consecutive dominant bits after a passive error flag. +8 +8 the transmitting node has completed a transmit operation without any errors (0 if error counter value is 0). ?1 no change the receiving node has completed a receive operation without any errors. no change ? ? 1 (1 rec7 to rec0 127) ? 0 (rec7 to rec0 = 0) ? 127 is set (rec7 to rec0 > 127) (c) occurrence of bit error during intermission in this case, an overload frame occurs. caution when an error occurs, error control is performed accord ing to the contents of the transmitting and receiving error counters as they existed prior to the error?s occurrence. the error counter value is incremented on ly after an error flag has been output. chapter 11 fcan controller 532 user?s manual u14492ej4v1ud 11.8.7 baud rate control function (1) prescaler the fcan controller of the v850e/ia1 includes a prescaler for dividing the clock supplied to the can (f mem1 ). this prescaler generates a clock (f btl ) that is based on a division ratio ranging from 2 to 128 applied to the can base clock (f mem ) when the c1brp register?s tlm bit = 0 and based on a division ratio ranging from 2 to 256 applied to the can base clock (f mem ) when the tlm bit = 1 (refer to 11.10 (26) can1 bit rate prescaler register (c1brp) ). (2) nominal bit time (8 to 25 time quantum) a definition of 1 data bit time is shown below. remark 1 time quantum = 1/f btl figure 11-21. nominal bit time nominal bit time sjw sjw phase segment 2 phase segment 1 sample point prop segment sync segment segment name segment length description sync segment (synchronization segment) 1 this segment begins when resynchronization occurs. prop segment (propagation segment) 1 to 8 (programmable) this segment is used to absorb the delays caused by the output buffer, can bus, and input buffer. it is set to return an ack signal until phase segment 1 begins. prop segment time (output buffer delay) + (can bus delay) + (input buffer delay) phase segment 1 (phase buffer segment 1) 1 to 8 (programmable) phase segment 2 (phase buffer segment 2) maximum value from phase segment 1 or ipt note (ipt = 0 to 2) this segment is used to compensate for errors in the data bit time. it accommodates a wide margin or error but slows down communication speed. sjw (resynchronization jump width) 1 to 4 (programmable) this sets the range for bit synchronization. note ipt: information processing time ipt is a period in which the current bit level is referenced and judgment for the next processing is performed. ipt is indicated by the expressi on below using the clock supplied to can (f mem1 ). ipt = 1/f mem1 3 chapter 11 fcan controller 533 user?s manual u14492ej4v1ud (3) data bit synchronization since the receiving node has no synchronization signal, synchronization is performed using level changes that occur on the bus. as for the transmitting node, data is transmitted in sync with the transmitting node?s bit timing. (a) hardware synchronization this is bit synchronization that is performed when the receiving node has detected a start of frame in bus idle mode. when a falling edge is detected on the bus, the cu rrent bit is assigned to the sync segment and the next bit is assigned to the prop segment. in such cases, synchronization is performed regardless of the sjw. since bit synchronization must be established after a reset or after a wake-up, hardware synchronization is performed only at the first level change that occu rs on the bus (for the second and subsequent level changes, bit synchronization is performed as shown below). figure 11-22. coordination of data bit synchronization phase segment 2 phase segment 1 prop segment sync segment start of frame bus idle can bus bit timing chapter 11 fcan controller 534 user?s manual u14492ej4v1ud (b) resynchronization resynchronization is performed when a level change is detected on the bus (only when the previous sampling is at the recessive level) during a receive operation. the edge?s phase error is produced by the relati ve positions of the detec ted edge and sync segment. chapter 11 fcan controller 535 user?s manual u14492ej4v1ud 11.9 cautions on bit set/clear function the fcan control registers include registers whose bits can be set or cleared via the cpu and via the can interface. an operation error occurs if the following register s are written to directly, so do not directly write (via bit manipulation, read/modify/write, or direct wr iting of target values) values to them. can global status register (cgst) can global interrupt enable register (cgie) can1 control register (c1ctrl) can1 definition register (c1def) can1 interrupt enable register (c1ie) all 16 bits in the above registers can be read via the us ual method. use the procedure described in figure 11-24 below to set or clear the lower 8 bits in these registers. setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (see figure 11-25 ). figure 11-24 shows how the values of set bits or cl ear bits relate to set/clear/no change operations in the corresponding register. figure 11-24. example of bi t setting/clearing operations 0000000011010001 1514131211109876543210 1514131211109876543210 1514131211109876543210 0000101111011000 set00001011 0000000000000011 clear 11011000 set set no change no change clear no change clear clear bit status register?s current values write values register?s value after write operations chapter 11 fcan controller 536 user?s manual u14492ej4v1ud figure 11-25. 16-bit data during write operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 c lear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n bit n status after bit set/clear operation 0 0 no change 0 1 0 1 0 1 1 1 no change remark n = 0 to 7 chapter 11 fcan controller 537 user?s manual u14492ej4v1ud 11.10 control registers (1) fcan clock selection register (prm04) the prm04 register is used to select the clock (f mem1 ) supplied to can1. the clock is selected according to the clock frequency. this register can be read/written in 8-bit or 1-bit units. caution set this regist er before using fcan. 7 0 prm04 6 0 5 0 4 0 3 0 2 0 1 prm5 0 prm4 address fffff930h initial value 00h bit position bit name function specifies fcan clock (f mem1 ) supplied to can1. prm5 prm4 input clock specification 0 0 f xx /4 (when f xx > 48 mhz) 0 1 f xx /2 (when 16 mhz < f xx 32 mhz) 1 0 f xx /3 (when 32 mhz < f xx 48 mhz) 1 1 f xx (when f xx 16 mhz) 1, 0 prm5, prm4 remark f xx : internal system clock chapter 11 fcan controller 538 user?s manual u14492ej4v1ud (2) can message data length register s 00 to 31 (m_dlc00 to m_dlc31) the m_dlcn register sets the byte count in the data field of can message buffer n (n = 00 to 31). when receiving, the receive data field?s byte count is set (to 1). these registers can be read/written in 8-bit units. caution when receiving a remote frame with an extended id and storing it in the receive message buffer, the values of dl c3 to dlc0 in the message buffer are cleared to 0 regardless of the values of dlc3 to dlc0 on the can bus. 7 rfu note m_dlcn (n = 00 to 31) 6 rfu note 5 rfu note 4 rfu note 3 dlc3 2 dlc2 1 dlc1 0 dlc0 address see table 11-17 initial value undefined bit position bit name function control field data for setting the number of bytes in the data field dlc3 dlc2 dlc1 dlc0 data length code of transmit/receive message 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes other than above 8 bytes regardless of the values of dlc3 to dlc0 3 to 0 dlc3 to dlc0 note rfu (reserved for future use) indicates a reserved bi t. be sure to clear this bit to 0 when writing the m_dlcn register. chapter 11 fcan controller 539 user?s manual u14492ej4v1ud table 11-17. addresses of m_dlcn (n = 00 to 31) register name address note (m = 2, 6, a, e) register name address note (m = 2, 6, a, e) m_dlc00 xxxxm804h m_dlc16 xxxxma04h m_dlc01 xxxxm824h m_dlc17 xxxxma24h m_dlc02 xxxxm844h m_dlc18 xxxxma44h m_dlc03 xxxxm864h m_dlc19 xxxxma64h m_dlc04 xxxxm884h m_dlc20 xxxxma84h m_dlc05 xxxxm8a4h m_dlc21 xxxxmaa4h m_dlc06 xxxxm8c4h m_dlc22 xxxxmac4h m_dlc07 xxxxm8e4h m_dlc23 xxxxmae4h m_dlc08 xxxxm904h m_dlc24 xxxxmb04h m_dlc09 xxxxm924h m_dlc25 xxxxmb24h m_dlc10 xxxxm944h m_dlc26 xxxxmb44h m_dlc11 xxxxm964h m_dlc27 xxxxmb64h m_dlc12 xxxxm984h m_dlc28 xxxxmb84h m_dlc13 xxxxm9a4h m_dlc29 xxxxmba4h m_dlc14 xxxxm9c4h m_dlc30 xxxxmbc4h m_dlc15 xxxxm9e4h m_dlc31 xxxxmbe4h note can message buffer registers c an be allocated to the xxxx addresse s as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. chapter 11 fcan controller 540 user?s manual u14492ej4v1ud (3) can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) the m_ctrln register is used to set the frame forma t of the data field in messages stored in can message buffer n (n = 00 to 31). these registers can be read/written in 8-bit units. (1/2) 7 rmde1 m_ctrln (n = 00 to 31) 6 rmde0 5 at s 4 ie 3 movr 2 rfu notes 1, 2 1 rfu notes 1, 3 0 rtr address see table 11-18 initial value undefined bit position bit name function specifies operation of the dn flag when a remote frame is received on a transmit message buffer. 0: dn flag not set when remote frame is received 1: dn flag set when remote frame is received 7 rmde1 cautions 1. when the rmde1 bit is set, the setting of the rmde0 bit is irrelevant. 2. if a remote frame arrives at th e transmit message buffer when the rmde1 bit has not been set, the cpu is not notified, nor are other operations performed. specifies setting/clearing status of re mote frame auto acknowledge function. 0: remote frame auto acknowledge function cleared 1: remote frame auto acknowledge function set 6 rmde0 cautions 1. the rmde0 bit?s setting is used only for transmit messages. 2. when the rtr bit has been se t (to 1) (when the receive message or transmit message has a remote frame), the rmde0 bit is processed as rmde0 = 0. this prevents a worst-case scenario (in which transmission of a remote frame draws a 100% bus load due to reception of the same remote frame). notes 1. rfu (reserved for future use) indicates a reserved bit. be sure to clear this bit to 0 when writing the m_dlcn register. 2. the value of the r1 bit on the can bus is set during reception. 3. the value of the r0 bit on the can bus is set during reception. remark dn: bit 2 of m_statn register (see 11.10 (8) can message status registers 00 to 31 (m_stat00 to m_stat31) ) chapter 11 fcan controller 541 user?s manual u14492ej4v1ud (2/2) bit position bit name function specifies whether or not to add a time stamp when transmitting. 0: time stamp not added when transmitting 1: time stamp added when transmitting 5 ats cautions 1. the ats bit is used only for transmit messages. 2. when the ats bit has been set (to 1) and the data length code specifies at least two bytes, the last two bytes are replaced by a time stamp (see table 11-3). the added time stamp counter value is sent over the bus via the sof of the message. when this occurs, the last two bytes (which are defined as a data field) are ignored. specifies the enable/disable setting for interrupt requests. 0: interrupt requests disabled 1: interrupt requests enabled 4 ie cautions 1. an interrupt request is generated when interrupts are enabled under the following conditions. ? when a message is transmitted fr om the transmit message buffer ? when a message is received by the receive message buffer ? when a remote frame is transmitted from the receive message buffer ? when a remote frame is received by the transmit message buffer when the auto acknowledge function has not been set (rmde0 bit = 0) 2. an interrupt request is not generated when interrupts are enabled under the following conditions. ? when a remote frame is received by the transmit message buffer when the auto acknowledge function has been set (rmde0 bit = 1) 3. an interrupt request is generated under the following conditions even if interrupts are disabled. ? when a remote frame is received by the receive message buffer when the auto acknowledge function has not been set (rmde0 bit = 0) this is the flag that indicates a message buffer overwrite. 0: overwrite does not occur after dn bit is cleared 1: overwrite occurs at leas t once after dn bit is cleared 3 movr caution an overwrite of the message buffer occurs when the can module writes new data to the message buffer or when the dn bit has already been set (to 1). the movr bit is updated each time new data is stored in the message buffer. specifies frame type. 0: data frame transmit/receive 1: remote frame transmit/receive 0 rtr caution when the rtr bit has been set (to 1) for a transmit message, a remote frame is transmitted instead of a data frame. remark dn: bit 2 of m_statn register (see 11.10 (8) can message status registers 00 to 31 (m_stat00 to m_stat31) ) chapter 11 fcan controller 542 user?s manual u14492ej4v1ud table 11-18. addresses of m_ctrln (n = 00 to 31) register name address note (m = 2, 6, a, e) register name address note (m = 2, 6, a, e) m_ctrl00 xxxxm805h m_ctrl16 xxxxma05h m_ctrl01 xxxxm825h m_ctrl17 xxxxma25h m_ctrl02 xxxxm845h m_ctrl18 xxxxma45h m_ctrl03 xxxxm865h m_ctrl19 xxxxma65h m_ctrl04 xxxxm885h m_ctrl20 xxxxma85h m_ctrl05 xxxxm8a5h m_ctrl21 xxxxmaa5h m_ctrl06 xxxxm8c5h m_ctrl22 xxxxmac5h m_ctrl07 xxxxm8e5h m_ctrl23 xxxxmae5h m_ctrl08 xxxxm905h m_ctrl24 xxxxmb05h m_ctrl09 xxxxm925h m_ctrl25 xxxxmb25h m_ctrl10 xxxxm945h m_ctrl26 xxxxmb45h m_ctrl11 xxxxm965h m_ctrl27 xxxxmb65h m_ctrl12 xxxxm985h m_ctrl28 xxxxmb85h m_ctrl13 xxxxm9a5h m_ctrl29 xxxxmba5h m_ctrl14 xxxxm9c5h m_ctrl30 xxxxmbc5h m_ctrl15 xxxxm9e5h m_ctrl31 xxxxmbe5h note can message buffer registers c an be allocated to the xxxx addresse s as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. chapter 11 fcan controller 543 user?s manual u14492ej4v1ud (4) can message time stamp register s 00 to 31 (m_time00 to m_time31) the m_timen register is the register where the time stamp counter valu e is written upon completion of data reception (n = 00 to 31). these registers can be read/written in 16-bit units. 14 ts 14 13 ts 13 12 ts 12 2 ts 2 3 ts 3 4 ts 4 5 ts 5 6 ts 6 7 ts 7 8 ts 8 9 ts 9 10 ts 10 11 ts 11 15 ts 15 1 ts 1 0 ts 0 m_timen (n = 00 to 31) address see table 11-19 initial value undefined bit position bit name function indicates the time stamp counter value. 15 to 0 ts15 to ts0 caution when a data frame or remote frame is received in the receive message buffer, if the new data is stored in the message buffer, a 16-bit time tag (time stamp counter value) is stored in the m_timen register only when the mt2 to mt0 bits of the m_confn re gister are set to value other than ?000? or ?110? (receive message). this time tag is set according to the fcan?s time stamp setting, which is either the time stamp counter value that was captured when the sof was sent via the bus or the value captured when the can module writes data to the message buffer. table 11-19. addresses of m_timen (n = 00 to 31) register name address note (m = 2, 6, a, e) register name address note (m = 2, 6, a, e) m_time00 xxxxm806h m_time16 xxxxma06h m_time01 xxxxm826h m_time17 xxxxma26h m_time02 xxxxm846h m_time18 xxxxma46h m_time03 xxxxm866h m_time19 xxxxma66h m_time04 xxxxm886h m_time20 xxxxma86h m_time05 xxxxm8a6h m_time21 xxxxmaa6h m_time06 xxxxm8c6h m_time22 xxxxmac6h m_time07 xxxxm8e6h m_time23 xxxxmae6h m_time08 xxxxm906h m_time24 xxxxmb06h m_time09 xxxxm926h m_time25 xxxxmb26h m_time10 xxxxm946h m_time26 xxxxmb46h m_time11 xxxxm966h m_time27 xxxxmb66h m_time12 xxxxm986h m_time28 xxxxmb86h m_time13 xxxxm9a6h m_time29 xxxxmba6h m_time14 xxxxm9c6h m_time30 xxxxmbc6h m_time15 xxxxm9e6h m_time31 xxxxmbe6h note can message buffer registers c an be allocated to the xxxx addresse s as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. chapter 11 fcan controller 544 user?s manual u14492ej4v1ud (5) can message data registers n0 to n7 (m_datan0 to m_datan7) (n = 00 to 31) the m_datanx registers are areas where up to 8 bytes of transmit or receive data is stored (n = 00 to 31, x = 0 to 7). these registers can be read/written in 8-bit units. 7 d0_7 m_datan0 (n = 00 to 31) 6 d0_6 5 d0_5 4 d0_4 3 d0_3 2 d0_2 1 d0_1 0 d0_0 address see table 11-20 initial value undefined 7 d1_7 m_datan1 (n = 00 to 31) 6 d1_6 5 d1_5 4 d1_4 3 d1_3 2 d1_2 1 d1_1 0 d1_0 address see table 11-20 initial value undefined 7 d2_7 m_datan2 (n = 00 to 31) 6 d2_6 5 d2_5 4 d2_4 3 d2_3 2 d2_2 1 d2_1 0 d2_0 address see table 11-20 initial value undefined 7 d3_7 m_datan3 (n = 00 to 31) 6 d3_6 5 d3_5 4 d3_4 3 d3_3 2 d3_2 1 d3_1 0 d3_0 address see table 11-20 initial value undefined 7 d4_7 m_datan4 (n = 00 to 31) 6 d4_6 5 d4_5 4 d4_4 3 d4_3 2 d4_2 1 d4_1 0 d4_0 address see table 11-20 initial value undefined 7 d5_7 m_datan5 (n = 00 to 31) 6 d5_6 5 d5_5 4 d5_4 3 d5_3 2 d5_2 1 d5_1 0 d5_0 address see table 11-20 initial value undefined 7 d6_7 m_datan6 (n = 00 to 31) 6 d6_6 5 d6_5 4 d6_4 3 d6_3 2 d6_2 1 d6_1 0 d6_0 address see table 11-20 initial value undefined 7 d7_7 m_datan7 (n = 00 to 31) 6 d7_6 5 d7_5 4 d7_4 3 d7_3 2 d7_2 1 d7_1 0 d7_0 address see table 11-20 initial value undefined bit position bit name function indicates the contents of the message data. 7 to 0 d7_7 to d0_0 cautions 1. the m_datan0 to m_datan7 registers are fields used to hold receive data and transmit data. when data is transmitted, the number of messages defined by the dlc3 to dlc0 bits in the m_dlcn register are transmitted via the can bus. 2. when the m_ctrln register?s ats bit has been set (to 1) and the value of the dlc3 to dlc0 bits in the m_dlcn register is at least two bytes, the last two bytes that are sent normally via the can bus are ignored and the time stamp value is sent. 3. when a new message is received, all data fields are updated, even when the value of the dlc3 to dlc0 bits in the m_dlcn register is less than 8 bytes. the values of data bytes that have not been received may be updated, but they are ignored. remark n = 00 to 31 chapter 11 fcan controller 545 user?s manual u14492ej4v1ud table 11-20. addresses of m_datan x (n = 00 to 31, x = 0 to 7) register name m_datan0 note (m = 2, 6, a, e) m_datan1 note (m = 2, 6, a, e) m_datan2 note (m = 2, 6, a, e) m_datan3 note (m = 2, 6, a, e) m_datan4 note (m = 2, 6, a, e) m_datan5 note (m = 2, 6, a, e) m_datan6 note (m = 2, 6, a, e) m_datan7 note (m = 2, 6, a, e) 00 xxxxm808h xxxxm809h xxxxm80ah xxxxm80bh xxxxm80ch xxxxm80dh xxxxm80eh xxxxm80fh 01 xxxxm828h xxxxm829h xxxxm82ah xxxxm82bh xxxxm82ch xxxxm82dh xxxxm82eh xxxxm82fh 02 xxxxm848h xxxxm849h xxxxm84ah xxxxm84bh xxxxm84ch xxxxm84dh xxxxm84eh xxxxm84fh 03 xxxxm868h xxxxm869h xxxxm86ah xxxxm86bh xxxxm86ch xxxxm86dh xxxxm86eh xxxxm86fh 04 xxxxm888h xxxxm889h xxxxm88ah xxxxm88bh xxxxm88ch xxxxm88dh xxxxm88eh xxxxm88fh 05 xxxxm8a8h xxxxm8a9h xxxxm8aah xxxxm8abh xxxxm8ach xxxxm8adh xxxxm8aeh xxxxm8afh 06 xxxxm8c8h xxxxm8c9h xxxxm8cah xxxxm8cb h xxxxm8cch xxxxm8cdh xxxxm8ceh xxxxm8cfh 07 xxxxm8e8h xxxxm8e9h xxxxm8eah xxxxm8ebh xxxxm8ech xxxxm8edh xxxxm8eeh xxxxm8efh 08 xxxxm908h xxxxm909h xxxxm90ah xxxxm90bh xxxxm90ch xxxxm90dh xxxxm90eh xxxxm90fh 09 xxxxm928h xxxxm929h xxxxm92ah xxxxm92bh xxxxm92ch xxxxm92dh xxxxm92eh xxxxm92fh 10 xxxxm948h xxxxm949h xxxxm94ah xxxxm94bh xxxxm94ch xxxxm94dh xxxxm94eh xxxxm94fh 11 xxxxm968h xxxxm969h xxxxm96ah xxxxm96bh xxxxm96ch xxxxm96dh xxxxm96eh xxxxm96fh 12 xxxxm988h xxxxm989h xxxxm98ah xxxxm98bh xxxxm98ch xxxxm98dh xxxxm98eh xxxxm98fh 13 xxxxm9a8h xxxxm9a9h xxxxm9aah xxxxm9abh xxxxm9ach xxxxm9adh xxxxm9aeh xxxxm9afh 14 xxxxm9c8h xxxxm9c9h xxxxm9cah xxxxm9cb h xxxxm9cch xxxxm9cdh xxxxm9ceh xxxxm9cfh 15 xxxxm9e8h xxxxm9e9h xxxxm9eah xxxxm9ebh xxxxm9ech xxxxm9edh xxxxm9eeh xxxxm9efh 16 xxxxma08h xxxxma09h xxxxma0ah xxxxma0bh xxxxma0ch xxxxma0dh xxxxma0eh xxxxma0fh 17 xxxxma28h xxxxma29h xxxxma2ah xxxxma2bh xxxxma2ch xxxxma2dh xxxxma2eh xxxxma2fh 18 xxxxma48h xxxxma49h xxxxma4ah xxxxma4bh xxxxma4ch xxxxma4dh xxxxma4eh xxxxma4fh 19 xxxxma68h xxxxma69h xxxxma6ah xxxxma6bh xxxxma6ch xxxxma6dh xxxxma6eh xxxxma6fh 20 xxxxma88h xxxxma89h xxxxma8ah xxxxma8bh xxxxma8ch xxxxma8dh xxxxma8eh xxxxma8fh 21 xxxxmaa8h xxxxmaa9h xxxxmaaah xxxxmaabh xxxxmaach xxxxmaadh xxxxmaaeh xxxxmaafh 22 xxxxmac8h xxxxmac9h xxxxma cah xxxxmacbh xxxxmacch xxxx macdh xxxxmaceh xxxxmacfh 23 xxxxmae8h xxxxmae9h xxxxmaeah xxxxmaebh xxxxmaech xxxxmaedh xxxxmaeeh xxxxmaefh 24 xxxxmb08h xxxxmb09h xxxxmb0ah xxxxmb0bh xxxxmb0ch xxxxmb0dh xxxxmb0eh xxxxmb0fh 25 xxxxmb28h xxxxmb29h xxxxmb2ah xxxxmb2bh xxxxmb2ch xxxxmb2dh xxxxmb2eh xxxxmb2fh 26 xxxxmb48h xxxxmb49h xxxxmb4ah xxxxmb4bh xxxxmb4ch xxxxmb4dh xxxxmb4eh xxxxmb4fh 27 xxxxmb68h xxxxmb69h xxxxmb6ah xxxxmb6bh xxxxmb6ch xxxxmb6dh xxxxmb6eh xxxxmb6fh 28 xxxxmb88h xxxxmb89h xxxxmb8ah xxxxmb8bh xxxxmb8ch xxxxmb8dh xxxxmb8eh xxxxmb8fh 29 xxxxmba8h xxxxmba9h xxxxmbaah xxxxmbabh xxxxmbach xxxxmbadh xxxxmbaeh xxxxmbafh 30 xxxxmbc8h xxxxmbc9h xxxxmb cah xxxxmbcbh xxxxmbcch xxxx mbcdh xxxxmbceh xxxxmbcfh 31 xxxxmbe8h xxxxmbe9h xxxxmbeah xxxxmbebh xxxxmbech xxxxmbedh xxxxmbeeh xxxxmbefh note can message buffer registers can be allocated to the xxxx addresses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. n chapter 11 fcan controller 546 user?s manual u14492ej4v1ud (6) can message id registers l 00 to l31 and h00 to h31 (m_idl00 to m_idl31 and m_idh00 to m_idh31) the m_idln and m_idhn registers are areas used to set identifiers (n = 00 to 31). these registers can be read/written in 16-bit units. when in standard format mode, any data can be stored in the following areas. bits id17 to id10: first byte of receive data note is stored. bits id9 to id2: second byte of receive data note is stored. bits id1, id0: third byte (higher two bits) of receive data note is stored. note see 11.10 (5) can message data registers n0 to n7 (m_datan0 to m_datan7) (n = 00 to 31) . 14 0 13 0 12 id28 2 id18 3 id19 4 id20 5 id21 6 id22 7 id23 8 id24 9 id25 10 id26 11 id27 15 ide 1 id17 0 id16 m_idhn (n = 00 to 31) address see table 11-22 initial value undefined 14 id14 13 id13 12 id12 2 id2 3 id3 4 id4 5 id5 6 id6 7 id7 8 id8 9 id9 10 id10 11 id11 15 id15 1 id1 0 id0 m_idln (n = 00 to 31) address see table 11-21 initial value undefined bit position bit name function 15 (m_idhn) ide (m_idhn) specifies format setting mode. 0: standard format mode (id28 to id18: 11 bits) 1: extended format mode (id28 to id0: 29 bits) remark n = 00 to 31 chapter 11 fcan controller 547 user?s manual u14492ej4v1ud table 11-21. addresses of m_idln (n = 00 to 31) register name address note (m = 2, 6, a, e) register name address note (m = 2, 6, a, e) m_idl00 xxxxm810h m_idl16 xxxxma10h m_idl01 xxxxm830h m_idl17 xxxxma30h m_idl02 xxxxm850h m_idl18 xxxxma50h m_idl03 xxxxm870h m_idl19 xxxxma70h m_idl04 xxxxm890h m_idl20 xxxxma90h m_idl05 xxxxm8b0h m_idl21 xxxxmab0h m_idl06 xxxxm8d0h m_idl22 xxxxmad0h m_idl07 xxxxm8f0h m_idl23 xxxxmaf0h m_idl08 xxxxm910h m_idl24 xxxxmb10h m_idl09 xxxxm930h m_idl25 xxxxmb30h m_idl10 xxxxm950h m_idl26 xxxxmb50h m_idl11 xxxxm970h m_idl27 xxxxmb70h m_idl12 xxxxm990h m_idl28 xxxxmb90h m_idl13 xxxxm9b0h m_idl29 xxxxmbb0h m_idl14 xxxxm9d0h m_idl30 xxxxmbd0h m_idl15 xxxxm9f0h m_idl31 xxxxmbf0h note can message buffer registers c an be allocated to the addresses xxxx as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. table 11-22. addresses of m_idhn (n = 00 to 31) register name address note (m = 2, 6, a, e) register name address note (m = 2, 6, a, e) m_idh00 xxxxm812h m_idh16 xxxxma12h m_idh01 xxxxm832h m_idh17 xxxxma32h m_idh02 xxxxm852h m_idh18 xxxxma52h m_idh03 xxxxm872h m_idh19 xxxxma72h m_idh04 xxxxm892h m_idh20 xxxxma92h m_idh05 xxxxm8b2h m_idh21 xxxxmab2h m_idh06 xxxxm8d2h m_idh22 xxxxmad2h m_idh07 xxxxm8f2h m_idh23 xxxxmaf2h m_idh08 xxxxm912h m_idh24 xxxxmb12h m_idh09 xxxxm932h m_idh25 xxxxmb32h m_idh10 xxxxm952h m_idh26 xxxxmb52h m_idh11 xxxxm972h m_idh27 xxxxmb72h m_idh12 xxxxm992h m_idh28 xxxxmb92h m_idh13 xxxxm9b2h m_idh29 xxxxmbb2h m_idh14 xxxxm9d2h m_idh30 xxxxmbd2h m_idh15 xxxxm9f2h m_idh31 xxxxmbf2h note can message buffer registers c an be allocated to the addresses xxxx as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. chapter 11 fcan controller 548 user?s manual u14492ej4v1ud (7) can message configuration register s 00 to 31 (m_conf00 to m_conf31) the m_confn register is used to set the message buffer type and mask (n = 00 to 31). these registers can be read/written in 8-bit units. 7 0 m_confn (n = 00 to 31) 6 0 5 mt2 4 mt1 3 mt0 2 0 1 0 0 ma address see table 11-23 initial value undefined bit position bit name function specifies message type and mask setting. mt2 mt1 mt0 operation 0 0 0 transmit message 0 0 1 receive message (no mask setting) 0 1 0 receive message (mask 0 is set) 0 1 1 receive message (mask 1 is set) 1 0 0 receive message (mask 2 is set) 1 0 1 receive message (mask 3 is set) 1 1 0 setting prohibited 1 1 1 receive message (used in diagnostic processing mode) 5 to 3 mt2 to mt0 when bits mt2 to mt0 have been set as ?111 ?, processing can be performed only when the fcan has been set to diagnostic processi ng mode. in such cases, all messages received are stored regardless of the following conditions. ? storage to other message buffer ? identifier type (standard frame or extended frame) ? data frame or remote frame specifies message buffer?s address. ma operation 0 message buffer is not used 1 used as message buffer 0 ma caution when the ma bit has been set to 0, message buffer area is used for application ram or for event processing as a temporary buffer. chapter 11 fcan controller 549 user?s manual u14492ej4v1ud table 11-23. addresses of m_confn (n = 00 to 31) register name address note (m = 2, 6, a, e) register name address note (m = 2, 6, a, e) m_conf00 xxxxm814h m_conf16 xxxxma14h m_conf01 xxxxm834h m_conf17 xxxxma34h m_conf02 xxxxm854h m_conf18 xxxxma54h m_conf03 xxxxm874h m_conf19 xxxxma74h m_conf04 xxxxm894h m_conf20 xxxxma94h m_conf05 xxxxm8b4h m_conf21 xxxxmab4h m_conf06 xxxxm8d4h m_conf22 xxxxmad4h m_conf07 xxxxm8f4h m_conf23 xxxxmaf4h m_conf08 xxxxm914h m_conf24 xxxxmb14h m_conf09 xxxxm934h m_conf25 xxxxmb34h m_conf10 xxxxm954h m_conf26 xxxxmb54h m_conf11 xxxxm974h m_conf27 xxxxmb74h m_conf12 xxxxm994h m_conf28 xxxxmb94h m_conf13 xxxxm9b4h m_conf29 xxxxmbb4h m_conf14 xxxxm9d4h m_conf30 xxxxmbd4h m_conf15 xxxxm9f4h m_conf31 xxxxmbf4h note can message buffer registers c an be allocated to the xxxx addresse s as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. chapter 11 fcan controller 550 user?s manual u14492ej4v1ud (8) can message status registers 00 to 31 (m_stat00 to m_stat31) the m_statn register indicates the transmit/receive status information of each message buffer (n = 00 to 31). these registers are read-only, in 8-bit units. cautions 1. writing directly to m_statn register cannot be performed. writi ng must be performed using can status set/clear register n (sc_statn). 2. messages are transmitted only when the m_statn regist er?s trq and rdy bits have been set (to 1). 7 0 m_statn (n = 00 to 31) 6 0 5 0 4 0 3 rfu note 1 2 dn 1 trq 0 rdy note 2 address see table 11-24 initial value undefined bit position bit name function 2 dn this is the message update flag. 0: no message was received after dn bit was cleared. 1: at least one message was received after dn bit was cleared. ? when the dn bit has been set (to 1) by the transmit message buffer, it indicates that the message buffer has received a remote frame. when this message is sent, the dn bit is automatically cleared (to 0). ? when a frame is again received in the receive message buffer for which the dn bit has been set (to 1), an overwrite condition occurs and the m_ctrln register?s movr bit is set (to 1) (n = 00 to 31). 1 trq this is the transmit request flag. 0: message transmission disabled 1: message transmission enabled ? a transmit request is processed as a ca n module only when the rdy bit is set to 1. ? a remote frame is transmitted for the receive message buffer in which the trq bit is set to 1. 0 rdy this is the transmit message ready flag. 0: message is not ready. 1: message is ready. ? a receive operation is performed only for a message buffer in which the rdy bit is set to 1 during reception. ? a transmit operation is performed only for a me ssage buffer in which the rdy bit is set to 1 and the trq bit is set to 1 during transmission. notes 1. rfu (reserved for future use) indicates a reserved bit. 0 or 1 is read from this bit regardless of the message buffer setting. 2. the fcan controller incorporated in the v850e/ia 1 can perform reception even if the rdy bit is not set. however, in products other than the v850e /ia1, the rdy bit must be set for reception. in order to maintain software compatibility, be sure to set the rdy bit even for the fcan controller of the v850e/ia1 prior to reception. chapter 11 fcan controller 551 user?s manual u14492ej4v1ud table 11-24. addresses of m_statn (n = 00 to 31) register name address note (m = 2, 6, a, e) register name address note (m = 2, 6, a, e) m_stat00 xxxxm815h m_stat16 xxxxma15h m_stat01 xxxxm835h m_stat17 xxxxma35h m_stat02 xxxxm855h m_stat18 xxxxma55h m_stat03 xxxxm875h m_stat19 xxxxma75h m_stat04 xxxxm895h m_stat20 xxxxma95h m_stat05 xxxxm8b5h m_stat21 xxxxmab5h m_stat06 xxxxm8d5h m_stat22 xxxxmad5h m_stat07 xxxxm8f5h m_stat23 xxxxmaf5h m_stat08 xxxxm915h m_stat24 xxxxmb15h m_stat09 xxxxm935h m_stat25 xxxxmb35h m_stat10 xxxxm955h m_stat26 xxxxmb55h m_stat11 xxxxm975h m_stat27 xxxxmb75h m_stat12 xxxxm995h m_stat28 xxxxmb95h m_stat13 xxxxm9b5h m_stat29 xxxxmbb5h m_stat14 xxxxm9d5h m_stat30 xxxxmbd5h m_stat15 xxxxm9f5h m_stat31 xxxxmbf5h note can message buffer registers c an be allocated to the xxxx addresse s as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. chapter 11 fcan controller 552 user?s manual u14492ej4v1ud (9) can status set/clear registers 00 to 31 (sc_stat00 to sc_stat31) the sc_statn register is used to set/clear the tr ansmit/receive status information (n = 00 to 31). these registers are write- only, in 16-bit units. 14 0 13 0 12 0 2 clear dn 3 0 4 0 5 0 6 0 7 0 8 set rdy 9 set trq 10 set dn 11 0 15 0 1 clear trq 0 clear rdy sc_statn (n = 00 to 31) address see table 11-25 initial value 0000h bit position bit name function specifies setting/clearing of the message update flag. set dn clear dn operation 0 1 cleared (dn bit cleared) 1 0 set (dn bit set) other than above no change in dn bit value 10, 2 set dn, clear dn specifies setting/clearing of the transmit request flag. set trq clear trq operation 0 1 cleared (trq bit cleared) 1 0 set (trq bit set) other than above no change in trq bit value 9, 1 set trq, clear trq specifies setting of the message ready flag. set rdy clear rdy operation 0 1 cleared (rdy bit cleared) 1 0 set (rdy bit set) other than above no change in rdy bit value 8, 0 set rdy, clear rdy remark dn: bit 2 of can message status register n (m_statn) trq: bit 1 of can message status register n (m_statn) rdy: bit 0 of can message status register n (m_statn) chapter 11 fcan controller 553 user?s manual u14492ej4v1ud table 11-25. addresses of sc_statn (n = 00 to 31) register name address note (m = 2, 6, a, e) register name address note (m = 2, 6, a, e) sc_stat00 xxxxm816h sc_stat16 xxxxma16h sc_stat01 xxxxm836h sc_stat17 xxxxma36h sc_stat02 xxxxm856h sc_stat18 xxxxma56h sc_stat03 xxxxm876h sc_stat19 xxxxma76h sc_stat04 xxxxm896h sc_stat20 xxxxma96h sc_stat05 xxxxm8b6h sc_stat21 xxxxmab6h sc_stat06 xxxxm8d6h sc_stat22 xxxxmad6h sc_stat07 xxxxm8f6h sc_stat23 xxxxmaf6h sc_stat08 xxxxm916h sc_stat24 xxxxmb16h sc_stat09 xxxxm936h sc_stat25 xxxxmb36h sc_stat10 xxxxm956h sc_stat26 xxxxmb56h sc_stat11 xxxxm976h sc_stat27 xxxxmb76h sc_stat12 xxxxm996h sc_stat28 xxxxmb96h sc_stat13 xxxxm9b6h sc_stat29 xxxxmbb6h sc_stat14 xxxxm9d6h sc_stat30 xxxxmbd6h sc_stat15 xxxxm9f6h sc_stat31 xxxxmbf6h note can message buffer registers c an be allocated to the xxxx addresse s as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. chapter 11 fcan controller 554 user?s manual u14492ej4v1ud (10) can interrupt pending register (ccintp) the ccintp register is used to confirm t he pending status of various interrupts. this register is read-only, in 16-bit units. 14 intmac 13 0 12 0 2 can1 err 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1 can1 rec 0 can1 trx ccintp address xxxxmc00h note 1 initial value 0000h bit position bit name function 14 intmac indicates an mac error note 2 interrupt (gint2, gint1) is pending. 0: not pending 1: pending 2 can1err indicates a can access error interrupt (c1int6 to c1int2) is pending. 0: not pending 1: pending 1 can1rec indicates a can receive completion interrupt (c1int1) is pending. 0: not pending 1: pending 0 can1trx indicates a can transmit completion interrupt (c1int0) is pending. 0: not pending 1: pending notes 1. xxxx: can message buffer registers can be allo cated to the xxxx addresses as programmable peripheral i/o registers. note, however, th at the xxxx addresses cannot be changed after being set. m = 2, 6, a, e 2. mac (memory access control) errors are errors that are set only when an interrupt source has occurred for the can global interrupt pending register (cgintp). remark gint3 to gint1: bits 3 to 1 of the can global interrupt pending register (cgintp) c1int6 to c1int0: bits 6 to 0 of the can1 interrupt pending register (c1intp) chapter 11 fcan controller 555 user?s manual u14492ej4v1ud (11) can global interrupt pe nding register (cgintp) the cgintp register is used to confirm t he pending status of mac error interrupts. this register can be read/writt en in 16-bit or 8-bit units. cautions 1. when ?1? is written to a bit in the cgin tp register, that bit is cleared (to 0). when ?0? is written to it, the bit?s value does not change. 2. an interrupt is generated when the co rresponding interrupt request is enabled and when no interrupt pending bit has been set (to 1) for a new interrupt. the correct or incorrect timing of setting the interrupt pending bit (to 1) is controlled by an interrupt service routin e. the earlier that the interr upt service routine clears the interrupt pending bit (to 0), the more quickl y the interrupt is ge nerated without losing any new interrupts of the same type. the interrupt pending bit can be set (to 1) only when the interrupt enable bit has been set (to 1). however, the interrupt pending bi t is not automatically cleared (to 0) just because the interrupt enable bi t has been cleared (to 0). use software processing to clear the interrupt pending bit (to 0). remark for details of invalid write access error interrupts and unavailable memory address access error interrupts, see 11.14.2 interrupts that are ge nerated for global can interface . 14 0 13 0 12 0 2 gint2 3 gint3 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1 gint1 0 0 cgintp address xxxxmc02h note initial value 0000h bit position bit name function 3 gint3 indicates that a wake-up interrupt fr om can sleep mode with stopped clock supply to fcan is pending. 0: not pending 1: pending 2 gint2 indicates that an invalid write access error interrupt is pending. 0: not pending 1: pending 1 gint1 indicates that an unavailable memory address access error interrupt is pending. 0: not pending 1: pending note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 556 user?s manual u14492ej4v1ud (12) can1 interrupt pendi ng register (c1intp) the c1intp register is used to confirm t he pending status of interrupts issued to fcan. this register can be read/writt en in 16-bit or 8-bit units. cautions 1. when ?1? is written to a bit in the c1intp register, that bi t is cleared (to 0). when ?0? is written to it, the bit?s value does not change. 2. an interrupt is generated when the co rresponding interrupt request is enabled and when no interrupt pending bit has been set (to 1) for a new interrupt. the correct or incorrect timing of setting the interrupt pending bit (to 1) is controlled by an interrupt service routin e. the earlier that the interr upt service routine clears the interrupt pending bit (to 0), the more quickl y the interrupt is ge nerated without losing any new interrupts of the same type. the interrupt pending bit can be set (to 1) only when the interrupt enable bit has been set (to 1). however, the interrupt pending bi t is not automatically cleared (to 0) just because the interrupt enable bi t has been cleared (to 0). use software processing to clear the interrupt pending bit (to 0). 14 0 13 0 12 0 2 c1int2 3 c1int3 4 c1int4 5 c1int5 6 c1int6 7 0 8 0 9 0 10 0 11 0 15 0 1 c1int1 0 c1int0 c1intp address xxxxmc04h note initial value 0000h bit position bit name function 6 c1int6 indicates pending status of the can error interrupt. 0: not pending 1: pending 5 c1int5 indicates pending status of the can bus error interrupt. 0: not pending 1: pending 4 c1int4 indicates pending status of the wake-up interrupt from can sleep mode. 0: not pending 1: pending 3 c1int3 indicates pending status of the can receive error passive status interrupt. 0: not pending 1: pending 2 c1int2 indicates pending status of the can transmit error passive or bus-off status interrupt. 0: not pending 1: pending 1 c1int1 indicates pending status of the can receive completion interrupt. 0: not pending 1: pending 0 c1int0 indicates pending status of the can transmit completion interrupt. 0: not pending 1: pending note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 557 user?s manual u14492ej4v1ud (13) can stop register (cstop) the cstop register controls clo ck supply to the entire can system. this register can be read/ written in 16-bit units. cautions 1. be sure to set the cstp bit (to 1) if the fcan function will not be used. 2. when the cstp bit has b een set (to 1), access to fcan re gisters other than the cstop register is prohibited. access to fcan (oth er than the cstop register) is possible only when the cstp bit has not been set (to 1). 3. when a change occurs on the can bus via a cstp bit se tting while the clock supply to the cpu or peripheral functions is stopped, cpu can be woken up. 4. if the can main clock (f mem1 ) is stopped in other than can sleep mode, first set the can module to initial mode (init bit of c1ctrl register = 1), clear (0) the gom bit of the cgst register, and then set (1) the cstp bit. 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 cstp 1 0 0 0 cstop address xxxxmc0ch note initial value 0000h bit position bit name function 15 cstp controls clock supply to fcan. 0: fcan is operating (supplies clock to fcan) 1: fcan is stopped (access to fcan is disabled) note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 558 user?s manual u14492ej4v1ud (14) can global status register (cgst) the cgst register indicate s global status information. this register can be read/ written in 16-bit units. cautions 1. both bitwise writing and direct writing to the cgst register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 cauti ons on bit set/clear function. 2. when writing to the cgst register, se t or clear bits according to the register configuration shown in part (b) write. (1/3) address xxxxmc10h note initial value 0100h 14 0 13 0 12 0 2 tsm 3 efsd 4 0 5 0 6 0 7 merr 8 1 9 0 10 0 11 0 15 0 1 0 0 gom cgst (read) 14 0 13 0 12 0 2 clear tsm 3 clear efsd 4 0 5 0 6 0 7 clear merr 8 set gom 9 0 10 set tsm 11 set efsd 15 0 1 0 0 clear gom cgst (write) (a) read (1/2) bit position bit name function 7 merr this is the status flag that indicates an mac error. 0: error has not occurred after the merr bit has been cleared. 1: error occurred at least once after the merr bit was cleared. caution mac errors occur under the following conditions. ? when invalid address is accessed ? when access prohibited by mac is performed ? when the gom bit is cleared (0) before the init bit of the c1ctrl register is set (1) 3 efsd indicates shutdown request. 0: shutdown disabled 1: shutdown enabled caution be sure to set the efsd bit (to 1) before clearing the gom bit (to 0) (needs to be accessed twice). the efsd bit will be cleared (to 0) automatically when the cgst register is accessed again. note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 559 user?s manual u14492ej4v1ud (2/3) (a) read (2/2) bit position bit name function 2 tsm indicates the operation status of the time stamp counter note . 0: time stamp counter is stopped 1: time stamp counter is operating note see 11.10 (17) can time stamp count register (cgtsc) 0 gom indicates the status of the global operation mode. 0: access to can module register note 1 is prohibited 1: access to can module register note 1 is enabled cautions 1. the gom bit controls the method the memory is accessed by the mac and can module operation state. when gom bit = 0 all the can modules are reset. access to the can module register is prohibited (if accessed, a mac error interrupt occurs) note 2 . read/write access to the temporary buffer is enabled. access to the message buffer area is enabled. when gom bit = 1 access to the can module register is enabled note 3 . access to the temporary buffer is prohibited (if access is attempted, a mac error interrupt occurs). access to the message buffer area is enabled. 2. the gom bit is cleared to 0 only when all the can modules are in the initial status (when the istat bit of the c1ctrl register = 1). if one of the can modules is not in the initial status, the gom bit remains set (1) even if it is cleared to 0. 3. to clear (0) the gom bit, first set (1) the init bit of the c1ctrl register, and then set (1) the efsd bit. do not manipulate the gom bit and efsd bit simultaneously. notes 1. register with a name starting with ?c1? 2. the cgcs register can be accessed. write accessing the cgmss register is prohibit ed. if the cgmss register is write accessed, the wrong search result is reflected in the cgmsr register. 3. write-accessing the cgcs register is prohibited. write-accessing the cgmss register is possible. chapter 11 fcan controller 560 user?s manual u14492ej4v1ud (3/3) (b) write bit position bit name function sets/clears the efsd bit. set efsd clear efsd operation 0 1 efsd bit cleared (to 0) 1 0 efsd bit set (to 1) other than above no change in efsd bit value 11, 3 set efsd, clear efsd sets/clears the tsm bit. set tsm clear tsm operation 0 1 tsm bit cleared (to 0) 1 0 tsm bit set (to 1) other than above no change in tsm bit value 10, 2 set tsm, clear tsm sets/clears the gom bit. set gom clear gom operation 0 1 gom bit cleared (to 0) 1 0 gom bit set (to 1) other than above no change in gom bit value 8, 0 set gom, clear gom 7 clear merr clears the merr bit. 0: no change in the merr bit 1: merr bit cleared (to 0) chapter 11 fcan controller 561 user?s manual u14492ej4v1ud (15) can global interrupt enable register (cgie) the cgie register is used to issue inte rrupt requests for global interrupts. this register can be read/ written in 16-bit units. cautions 1. both bitwise writing and direct writing to the cgie register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 cauti ons on bit set/clear function. 2. when writing to the cgie register, se t or clear bits according to the register configuration during a write operation. address xxxxmc12h note initial value 0a00h cgie (read) 14 0 13 0 12 0 2 clear g_ie2 3 0 4 0 5 0 6 0 7 0 8 0 9 set g_ie1 10 set g_ie2 11 0 15 0 1 clear g_ie1 0 0 cgie (write) 14 0 13 0 12 0 2 g_ie2 3 0 4 0 5 0 6 0 7 0 8 0 9 1 10 0 11 1 15 0 1 g_ie 1 0 0 (a) read bit position bit name function 2 g_ie2 this is the invalid write access (to temporary buffer, etc.) interrupt enable flag. 0: interrupt disabled 1: interrupt enabled 1 g_ie1 this is the unavailable memory address access interrupt enable flag. 0: interrupt disabled 1: interrupt enabled (b) write bit position bit name function sets/clears the g_ien bit. set g_ien clear g_ien setting of g_ien bit 0 1 g_ien bit cleared 1 0 g_ien bit set other than above no change in g_ien bit value 10, 9, 2, 1 set g_ien, clear g_ien note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e remark n = 1, 2 chapter 11 fcan controller 562 user?s manual u14492ej4v1ud (16) can main clock selection register (cgcs) the cgcs register is used to select the main clock. this register can be read/written in 16-bit units. caution when the gom bit of th e cgst register is 1, write accessing the cgcs register is prohibited. (1/2) 14 cgts 6 13 cgts 5 12 cgts 4 2 mcp2 3 mcp3 4 0 note 1 5 0 6 gtcs 0 7 gtcs 1 8 cgts 0 9 cgts 1 10 cgts 2 11 cgts 3 15 cgts 7 1 mcp1 0 mcp0 cgcs address xxxxmc14h note 3 initial value 7f05h bit position bit name function indicates global time r system clock (f gts ) (see figure 11-26 ). n cgts 7 cgts 6 cgts 5 cgts 4 cgts 3 cgts 2 cgts 1 cgts 0 system timer prescaler selection f gts = f gts1 /(n + 1) 0 0 0 0 0 0 0 0 0 f gts = f gts1 /1 1 0 0 0 0 0 0 0 1 f gts = f gts1 /2 : f gts = f gts1 /(n + 1) 127 0 1 1 1 1 1 1 1 f gts = f gts1 /128 (after reset) : f gts = f gts1 /(n + 1) 254 1 1 1 1 1 1 1 0 f gts = f gts1 /255 255 1 1 1 1 1 1 1 1 f gts = f gts1 /256 the global timer system clock (f gts ) is the source clock for the time stamp counter note 3 that is used for the time stamp function. 15 to 8 cgts7 to cgts0 specifies the glo bal timer clock (f gts1 ) (see figure 11-26 ). gtcs1 gtcs0 global time r clock selection (f gts1 ) 0 0 f mem /2 0 1 f mem /4 1 0 f mem /8 1 1 f mem /16 7, 6 gtcs1, gtcs0 notes 1. when writing to this bit, always set it to 0. 2. xxxx: can message buffer registers can be allocated to the xxxx addresses as programmable peripheral i/o registers. note , however, that the xxxx addre sses cannot be changed after being set. m = 2, 6, a, e 3. refer to 11.10 (17) can time stamp count register (cgtsc) . chapter 11 fcan controller 563 user?s manual u14492ej4v1ud (2/2) bit position bit name function specifies the clock to memory access controller (f mem ) (see figure 11-26 ). n mcp3 mcp2 mcp1 mcp0 selection of clock to memory access controller (f mem ) 0 0 0 0 0 f mem1 1 0 0 0 1 f mem1 /2 2 0 0 1 0 f mem1 /3 : 14 1 1 1 0 f mem1 /15 15 1 1 1 1 f mem1 /16 3 to 0 mcp3 to mcp0 once the values of the mcp3 to mcp0 bits are set after reset is released, do not change these values. chapter 11 fcan controller 564 user?s manual u14492ej4v1ud figure 11-26. fcan clocks cgts7 cgts6 cgts5 cgts4 cgts3 cgts2 cgts1 cgts0 gtcs1 gtcs0 mcp 3 mcp2 prescaler data bit time can1 bit rate prescaler register (c1brp) can main clock selection register (cgcs) global timer clock prescaler baud rate generator global timer system clock can1 synchronization control register (c1sync) time stamp counter mcp1 mcp0 brp0 brp1 brp2 brp3 brp4 brp5 btype f mem1 prm04 f xx f xx /2 f xx /3 f xx /4 f mem f gts1 f btl f gts fcan selector brp7 note brp6 note note only when the tlm bit of the can1 bi t rate prescaler register (c1brp) is 1 caution when using a 1 mbps tran sfer rate for the cpu, input f mem1 as a 16 mhz clock signal. if input at another frequency, s ubsequent operation is not guaranteed. (17) can time stamp count register (cgtsc) the cgtsc register indicates the c ontents of the time stamp counter. this register can be read at any time. this register can be written to only when clearing bits. the clear function writes 0 to all bits in the cgtsc register. this register is read-only, in 16-bit units. 14 tsc14 13 tsc13 12 tsc12 2 tsc2 3 tsc3 4 tsc4 5 tsc5 6 tsc6 7 tsc7 8 tsc8 9 tsc9 10 tsc10 11 tsc11 15 tsc15 1 tsc1 0 tsc0 cgtsc address xxxxmc18h note initial value 0000h note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 565 user?s manual u14492ej4v1ud (18) can message search start/r esult register (cgmss (during write)/cgmsr (during read)) the cgmss/cgmsr register indicates the message search start/result status. messages in the message buffer that match the specified search criteria can be searched quickly. these registers can be read/written in 16-bit units. caution execute a search by writ ing the cgmss regi ster only once. (1/2) 14 0 13 0 12 0 2 mfnd2 3 mfnd3 4 mfnd4 5 0 6 0 7 0 8 am 9 mm 10 0 11 0 15 0 1 mfnd1 0 mfnd0 cgmsr (read) address xxxxmc1ah note initial value 0000h 14 0 13 ctrq 12 cmsk 2 strt2 3 strt3 4 strt4 5 0 6 0 7 0 8 smno 9 0 10 0 11 cdn 15 cide 1 strt1 0 strt0 cgmss (write) (a) read bit position bit name function 9 mm confirms multiple hits from message search. 0: no messages or only one message meets the search criteria 1: several messages meet the search criteria if several message buffers that meet search criteria are detected, the mm bit is set (to 1). 8 am confirms hits from message search. 0: no messages meet the search criteria 1: at least one message meets the search criteria 4 to 0 mfnd4 to mfnd0 indicates searched message number (0 to 31). when multiple message buffer numbers match as a result of a search (mm = 1), the return value of the mfnd4 to mfnd0 bits is the lowest message buffer number. when no message buffer numbers match as a result of a search (am = 0), the return value of the mfnd4 to mfnd0 bits is the number of message buffers ? 1. note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 566 user?s manual u14492ej4v1ud (2/2) (b) write bit position bit name function 15 cide checks message identifier (id) format flag. 0: message identifier format flag not checked 1: only message with standard format identifier checked 13 ctrq checks transmit request and message ready flag. 0: transmit request and message ready flag not checked 1: transmit request and message ready flag checked 12 cmsk checks masked messages. 0: masked messages not checked 1: only masked messages checked 11 cdn checks status of the dn flag of m_statn register (n = 00 to 31). 0: status of the dn flag of m_statn register not checked 1: status of the dn flag of m_statn register checked 8 smno sets search module. 0: no search module setting 1: can module set as search target 4 to 0 strt4 to strt0 indicates message search start position. 0 to 31: message search start position (message number) search starts from the message number def ined by bits strt4 to strt0. search continues until it reaches the message buf fer having the highest number among the usable message buffers. if the search results include several message buffer numbers among the matching messages, the message buffer with the lowest message buffer number is selected. to fetch the next message buffer number without changing the search criteria, ?(mfnd4 to mfnd0) + 1? mu st be set as the values of bits strt4 to strt0. chapter 11 fcan controller 567 user?s manual u14492ej4v1ud (19) can1 address mask a registers l and h (c1maskla and c1maskha) the c1maskla and c1maskha registers are used to extend the number of receivable messages by masking part of the message?s identifier (id) and th en ignoring the masked parts (a = 0 to 3). these registers can be read/written in 16-bit units. cautions 1. when the receive mess age buffer is linked to the c1ma skla and c1maskha registers, regardless of whether the id in the receive message buffer is a standard id (11 bits) or extended id (29 bits), set all the 32-bit values of the c1maskla and c1maskha registers (a = 0 to 3). 2. when the c1maskla and c1maskha re gisters are linked to a message buffer for standard id, the lower 18 bits of the data fi eld in the data frame are also automatically compared. therefore, if it is not necessary to compare the lower 18 bits (i.e., to mask the lower 18 bits), set the cmid 17 to cmid0 bits to 1 (a = 0 to 3). the standard id and extended id can use the same mask. address see table 11-26 initial value undefined 14 0 13 0 12 cmid 28 2 cmid 18 3 cmid 19 4 cmid 20 5 cmid 21 6 cmid 22 7 cmid 23 8 cmid 24 9 cmid 25 10 cmid 26 11 cmid 27 15 cmide 1 cmid 17 0 cmid 16 c1maskha (a = 0 to 3) address see table 11-26 initial value undefined 14 cmid 14 13 cmid 13 12 cmid 12 2 cmid 2 3 cmid 3 4 cmid 4 5 cmid 5 6 cmid 6 7 cmid 7 8 cmid 8 9 cmid 9 10 cmid 10 11 cmid 11 15 cmid 15 1 cmid 1 0 cmid 0 c1maskla (a = 0 to 3) bit position bit name function 15 (c1maskha) cmide sets mask for identifier (id) format. 0: id format (standard or extended) checked 1: id format (standard or extended) not checked when the cmide bit is set (1), the higher 11 bi ts of the id are compared. the receive message and the id format stored in a message buffer are not compared. 12 to 0 (c1maskha) 15 to 0 (c1maskla) cmid28 to cmid16 (c1maskha) cmid15 to cmid0 (c1maskla) sets mask for identifier (id) bit. 0: id bit in message buffer linked to bits cmid28 to cmid0 compared with received id bit 1: id bit in message buffer linked to bits cmid28 to cmid0 not compared (id bit masked) with received id bit remark n = 0 to 3 chapter 11 fcan controller 568 user?s manual u14492ej4v1ud table 11-26. addresses of c1maskla and c1maskha (a = 0 to 3) register name address note (m = 2, 6, a, e) c1maskl0 xxxxmc40h c1maskh0 xxxxmc42h c1maskl1 xxxxmc44h c1maskh1 xxxxmc46h c1maskl2 xxxxmc48h c1maskh2 xxxxmc4ah c1maskl3 xxxxmc4ch c1maskh3 xxxxmc4eh note can message buffer registers can be allocated to the xxxx addresses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. chapter 11 fcan controller 569 user?s manual u14492ej4v1ud (20) can1 control register (c1ctrl) the c1ctrl register is used to cont rol the operation of the can module. this register can be read/written in 16-bit units. cautions 1. both bitwise writing and direct writi ng to the c1ctrl register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 cauti ons on bit set/clear function. 2. when writing to the c1ct rl register, set or clear bi ts according to the register configuration during a write operation. 3. when canceling can stop mode, can sleep m ode must be canceled at the same time. (1/4) address xxxxmc50h note initial value 0101h c1ctrl (read) 14 set dlevr 13 set dlevt 12 set ovm 2 clear stop 3 clear tmr 4 clear ovm 5 clear dlevt 6 clear dlevr 7 0 8 set init 9 set sleep 10 set stop 11 set tmr 15 0 1 clear sleep 0 clear init c1ctrl (write) 14 tecs0 13 recs1 12 recs0 2 stop 3 tmr 4 ovm 5 dlevt 6 dlevr 7 0 8 i s tat 9 r s tat 10 t s tat 11 boff 15 tecs1 1 sleep 0 init (a) read (1/3) bit position bit name function this is the transmit error counter status flag. tecs1 tecs0 status of transmit error counter 0 0 transmit error counter value < 96 0 1 transmit error counter value = 96 to 127 (warning level) 1 0 not used 1 1 transmit error counter value 128 (error passive) 15, 14 tecs1, tecs0 this is the receive error counter status flag. recs1 recs0 status of receive error counter 0 0 receive error counter value < 96 0 1 receive error counter value = 96 to 127 (warning level) 1 0 not used 1 1 receive error counter value 128 (error passive) 13, 12 recs1, recs0 note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 570 user?s manual u14492ej4v1ud (2/4) (a) read (2/3) bit position bit name function 11 boff this is the bus off status flag. 0: transmit error counter < 256 (not bus off status) 1: transmit error counter 256 (bus off status) 10 tstat this is the transmit status flag. 0: transmission stopped status 1: transmitting status 9 rstat this is the receive status flag. 0: reception stopped status 1: receiving status 8 istat this is the initialization status flag. 0: normal operating status 1: fcan is stopped and initialized cautions 1. the istat bit is set (to 1) when the can protocol layer acknowledges the settings of the init and stop bits. also, this bit is automatically cleared (to 0) when the init and stop bits are cleared (to 0). 2. in the initialization status, ?recessive? is output to the ctxd pin. 3. the c1sync and c1brp registers can be written only in initialization mode. 4. in the initialization status, the error counter (see 11.10 (23) can1 error count register (c1erc)) is cleared (to 0) and the error status (bits tecs1, tecs0, recs0, and recs1) is reset. 6 dlevr this is the dominant level control bit for receive pins. 0: a low level to a receive pin is acknowledged as dominant 1: a high level to a receive pin is acknowledged as dominant 5 dlevt this is the dominant level control bit for transmit pins. 0: a low level is transmitted from a transmit pin as dominant 1: a high level is transmitted fr om a transmit pin as dominant 4 ovm this is the overwrite mode control bit. 0: new messages stored in message buffer in which dn bit of m_statn register (n = 00 to 31) is set 1: new messages in message buffer in which dn bit is set are discarded. when the ovm bit = 1, the receive completion interrupt (intcrec) is not generated even if new messages are received in the message buffer in which the dn bit is set. 3 tmr this is the time stamp control bit for reception. 0: captures time stamp counter value when sof is detected on can bus 1: captures time stamp counter value when eof is detected on can bus (a valid message is confirmed) 2 stop this is the can stop mode control bit. 0: no can stop mode setting 1: can stop mode the can stop mode can be selected only when the can module is set to can sleep mode (the sleep bit is set (to 1)). can stop mode can be canceled only by the cpu (stop bit cleared (to 0)). chapter 11 fcan controller 571 user?s manual u14492ej4v1ud (3/4) (a) read (3/3) bit position bit name function 1 sleep this is the can sleep mode control bit. 0: normal operation mode 1: switch to can sleep mode. change in can bus performs wake-up. cautions 1. can sleep mode can be set only when the can bus is in the idle state. 2. can sleep mode is canceled under the following conditions. when the cpu has cleared the sleep bit (to 0) when the can bus changes (only when can stop mode has not been set) 3. the wake bit (see 11.10 (21) can1 definition register (c1def)) can be set (to 1) only when can sleep mode is canceled by the change of the can bus, and an error interrupt occurs. 0 init this is the initialization reques t bit used to initialize the can module. 0: normal operation mode 1: initialization mode cautions 1. be sure to confirm that the can module has entered the initialization mode using the istat bit (istat bit = 1) after setting the init bit (to 1). when the istat bit = 0, set the init bit (to 1) again. 2. if the init bit is set (to 1) when the can module is in the bus off status (boff bit = 1), the can module enters initialization mode (istat bit = 1) after returning from the bus off status (boff bit = 0). (b) write (1/2) bit position bit name function sets/clears the dlevr bit. set dlevr clear dlevr operation 0 1 dlevr bit cleared (to 0) 1 0 dlevr bit set (to 1) other than above dlevr bit not changed 14, 6 set dlevr, clear dlevr sets/clears the dlevt bit. set dlevt clear dlevt operation 0 1 dlevt bit cleared (to 0) 1 0 dlevt bit set (to 1) other than above dlevt bit not changed 13, 5 set dlevt, clear dlevt chapter 11 fcan controller 572 user?s manual u14492ej4v1ud (4/4) (b) write (2/2) bit position bit name function sets/clears the ovm bit. set ovm clear ovm operation 0 1 ovm bit cleared (to 0) 1 0 ovm bit set (to 1) other than above ovm bit not changed 12, 4 set ovm, clear ovm sets/clears the tmr bit. set tmr clear tmr operation 0 1 tmr bit cleared (to 0) 1 0 tmr bit set (to 1) other than above tmr bit not changed 11, 3 set tmr, clear tmr sets/clears the stop bit. set stop clear stop operation 0 1 stop bit cleared (to 0) 1 0 stop bit set (to 1) other than above stop bit not changed 10, 2 set stop, clear stop sets/clears the sleep bit. set sleep clear sleep operation 0 1 sleep bit cleared (to 0) 1 0 sleep bit set (to 1) other than above sleep bit not changed 9, 1 set sleep, clear sleep sets/clears the init bit. set init clear init operation 0 1 init bit cleared (to 0) 1 0 init bit set (to 1) other than above init bit not changed 8, 0 set init, clear init chapter 11 fcan controller 573 user?s manual u14492ej4v1ud (21) can1 definition register (c1def) the c1def register is used to defin e the operation of the can module. this register can be read/ written in 16-bit units. cautions 1. both bitwise writing and direct writing to the c1def register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 cauti ons on bit set/clear function. 2. when writing to the c1def register, set or clear bits accord ing to the register configuration during a write operation. (1/4) address xxxxmc52h note initial value 0000h c1def (read) 14 set mom 13 set ssht 12 set pbb 2 clear valid 3 clear berr 4 clear pbb 5 clear ssht 6 clear mom 7 clear dgm 8 0 9 0 10 0 11 0 15 set dgm 1 clear wake 0 clear ovr c1def (write) 14 0 13 0 12 0 2 valid 3 berr 4 pbb 5 ssht 6 mom 7 dgm 8 0 9 0 10 0 11 0 15 0 1 wake 0 ovr (a) read (1/3) bit position bit name function 7 dgm specifies diagnostic processing mode. 0: only when receiving, valid messages received using message buffer used for diagnostic processing mode (bits mt2 to mt0 of m_conf register = 111) 1: only when receiving, valid messages received using normal operation mode. the diagnostic processing mode (mom bit = 1) is used for can baud rate detection and for diagnostic purposes. when this mode has been set, the following operations are performed. ? when the valid bit = 1, it indicates that the current receive operation is valid. ? setting the dgm bit confirms whether or not valid data has been stored in the message buffer used for diagnostic processing mode, the same as for normal operation mode. note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 574 user?s manual u14492ej4v1ud (2/4) (a) read (2/3) bit position bit name function 6 mom specifies the can module operation mode. 0: normal operating mode 1: diagnostic processing mode cautions 1. when in diagnostic processing mode (mom bit = 1), the c1brp register can be accessed only when the can module has been set to initialization mode (i.e., when the c1ctrl register?s istat bit = init bit = 1). when the can module is operating (i.e., when the c1ctrl register?s istat bit = 0), the c1brp register cannot be used, and the can1 bus diagnostic information register (refer to 11. 10 (27) can1 bus diagnostic information register (c1dinf)) can be used instead. 2. the can protocol layer does not send ack, error frame, or transmit messages, nor does it operate an error counter. the internal transmit output is fed back to the internal input due to auto baud rate detection. 5 ssht specifies single shot mode. 0: normal operating mode 1: single shot mode in single shot mode, the can module can transmit a message only one time. the m_statn register?s trq bit is then cleared (t o 0) regardless of whether or not there are any pending normal transmit operations (n = 00 to 31). also, if a bus error has occurred due to a transmission, it is handled as an incomplete transmission. cautions 1. in single shot mode, even if the can lost in arbitration, it is handled as a completed message transmission. when in this mode, the berr bit is set (to 1) but the error counter value (refer to 11.10 (23) can1 error count register (c1erc)) does not change since there are no can bus errors. 2. in single shot mode, even when transmission is stopped due to error detection or a loss in the arbitration phase, the transmission completion interrupt occurs. 3. during the time when the can module is active, the cpu switches between normal operation mode and single shot mode without causing any errors to occur on the can bus. 4 pbb specifies priority control for transmission. 0: identifier (id) based priority control 1: message number based priority control ordinarily, priority for transmission is defined based on message ids, but when the pbb bit has been set (to 1) priority becomes based instead on the position of messages, so that messages with lower message numbers have higher priority. 3 berr indicates can bus error status. 0: can bus error was not detected 1: can bus error was detected at least once after bit was cleared 2 valid indicates valid message detection status. 0: valid message was not detected 1: valid message was detected at least once after bit was cleared chapter 11 fcan controller 575 user?s manual u14492ej4v1ud (3/4) (a) read (3/3) bit position bit name function 1 wake indicates can sleep mode cancellation status. 0: normal operation 1: can sleep mode canceled cautions 1. the wake bit is set (1) only when the can sleep mode is released due to a change in the can bus and an error interrupt occurs. 2. while the wake bit is set (1), the error interrupt signal holds the active status. therefore, always clear (0) the wake bit after recognition that the wake bit is set. 0 ovr indicates overrun error status. 0: normal operation 1: overrun occurred during ram access caution when an overrun error has occurred, the ovr bit is set (to 1) and an error interrupt occurs at the same time. the source of the overrun error may be that the ram access clock is slower than the selected can baud rate. chapter 11 fcan controller 576 user?s manual u14492ej4v1ud (4/4) (b) write bit position bit name function sets/clears the dgm bit. set dgm clear dgm operation 0 1 dgm bit cleared (to 0) 1 0 dgm bit set (to 1) other than above dgm bit not changed 15, 7 set dgm, clear dgm sets/clears the mom bit. set mom clear mom operation 0 1 mom bit cleared (to 0) 1 0 mom bit set (to 1) other than above mom bit not changed 14, 6 set mom, clear mom sets/clears the ssht bit. set ssht clear ssht operation 0 1 ssht bit cleared (to 0) 1 0 ssht bit set (to 1) other than above ssht bit not changed 13, 5 set ssht, clear ssht sets/clears the pbb bit. set pbb clear pbb operation 0 1 pbb bit cleared (to 0) 1 0 pbb bit set (to 1) other than above pbb bit not changed 12, 4 set pbb, clear pbb 3 clear berr clears the berr bit. 0: no change in berr bit 1: berr bit cleared (to 0) 2 clear valid clears the valid bit. 0: no change in valid bit 1: valid bit cleared (to 0) 1 clear wake clears the wake bit. 0: no change in wake bit 1: wake bit cleared (to 0) 0 clear ovr clears the ovr bit. 0: no change in ovr bit 1: ovr bit cleared (to 0) chapter 11 fcan controller 577 user?s manual u14492ej4v1ud (22) can1 information register (c1last) the c1last register indicates the can module?s e rror information and the number of the message buffer received last. this register is read-only, in 16-bit units. 14 0 13 0 12 0 2 lrec2 3 lrec3 4 lrec4 5 lrec5 6 lrec6 7 lrec7 8 lerr0 9 lerr1 10 lerr2 11 lerr3 15 0 1 lrec1 0 lrec0 c1last address xxxxmc54h note initial value 00ffh bit position bit name function indicates the last error information. lerr3 lerr2 lerr1 lerr0 last error information 0 0 0 0 error not detected 0 0 0 1 bit error 0 0 1 0 stuff error 0 0 1 1 crc error 0 1 0 0 form error 0 1 0 1 ack error 0 1 1 0 arbitration lost (only in single shot mode (c1def register?s ssht bit = 1)) 0 1 1 1 can overrun error 1 0 0 0 wake-up from can bus other than above undefined 11 to 8 lerr3 to lerr0 caution since the lerr3 to lerr0 bits cannot be cleared, the current status is retained until the next error occurs. 7 to 0 lrec7 to lrec0 indicates the last received message number. 0 to 31: the number of the message buffer last received 32 to 255: not used note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 578 user?s manual u14492ej4v1ud (23) can1 error count register (c1erc) the c1erc register indicates the count values of the transmission/reception error counters. this register is read-only, in 16-bit units. 14 rec6 13 rec5 12 rec4 2 tec2 3 tec3 4 tec4 5 tec5 6 tec6 7 tec7 8 rec0 9 rec1 10 rec2 11 rec3 15 rec7 1 tec1 0 tec0 c1erc address xxxxmc56h note initial value 0000h bit position bit name function 15 to 8 rec7 to rec0 indicates the reception error count. 0 to 255: the number of reception errors this reflects the current status of the reception error counter. the number of counts is defined by the can protocol. 7 to 0 tec7 to tec0 indicates the transmission error count. 0 to 255: the number of transmission errors this reflects the current status of the transmission error counter. the number of counts is defined by the can protocol. note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 579 user?s manual u14492ej4v1ud (24) can1 interrupt enable register (c1ie) the c1ie register is used to enable/ disable the can module?s interrupts. this register can be read/ written in 16-bit units. cautions 1. both bitwise writing and direct writing to the c1ie register are prohibited. attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 cauti ons on bit set/clear function. 2. when writing to the c1ie register, se t or clear bits accord ing to the register configuration during a write operation. (1/3) address xxxxmc58h note initial value 0900h c1ie (read) 14 set e_int6 13 set e_int5 12 set e_int4 2 clear e_int2 3 clear e_int3 4 clear e_int4 5 clear e_int5 6 clear e_int6 7 0 8 set e_int0 9 set e_int1 10 set e_int2 11 set e_int3 15 0 1 clear e_int1 0 clear e_int0 c1ie (write) 14 0 13 0 12 0 2 e_int2 3 e_int3 4 e_int4 5 e_int5 6 e_int6 7 0 8 1 9 0 10 0 11 1 15 0 1 e_int1 0 e_int0 (a) read (1/2) bit position bit name function 6 e_int6 this is the can module error interrupt enable flag. 0: interrupt disabled 1: interrupt enabled 5 e_int5 this is the can bus error interrupt enable flag. 0: interrupt disabled 1: interrupt enabled 4 e_int4 this is the wake up from can sleep mode interrupt enable flag. 0: interrupt disabled 1: interrupt enabled 3 e_int3 this is the receive error passive interrupt enable flag. 0: interrupt disabled 1: interrupt enabled 2 e_int2 this is the transmit error passiv e or bus off interrupt enable flag. 0: interrupt disabled 1: interrupt enabled note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 580 user?s manual u14492ej4v1ud (2/3) (a) read (2/2) bit position bit name function 1 e_int1 this is the receive completion interrupt enable flag. 0: interrupt disabled 1: interrupt enabled ? when ie bit of the m_ctrln register is 1, a reception completion interrupt occurs regardless of the setting of the e_int1 bit if the transmit message buffer receives a remote frame while the auto response function is not set (rmde0 bit of the m_ctrln register = 0) (n = 00 to 31). 0 e_int0 this is the transmit completion interrupt enable flag. 0: interrupt disabled 1: interrupt enabled (b) write (1/2) bit position bit name function sets/clears the e_int6 bit. set e_int6 c lear e_int 6 operation 0 1 e_int6 interrupt cleared (to 0) 1 0 e_int6 interrupt set (to 1) other than above e_int6 interrupt not changed 14, 6 set e_int6, clear e_int6 sets/clears the e_int5 bit. set e_int5 c lear e_int 5 operation 0 1 e_int5 interrupt cleared (to 0) 1 0 e_int5 interrupt set (to 1) other than above e_int5 interrupt not changed 13, 5 set e_int5, clear e_int5 sets/clears the e_int4 bit. set e_int4 c lear e_int 4 operation 0 1 e_int4 interrupt cleared (to 0) 1 0 e_int4 interrupt set (to 1) other than above e_int4 interrupt not changed 12, 4 set e_int4, clear e_int4 sets/clears the e_int3 bit. set e_int3 c lear e_int 3 operation 0 1 e_int3 interrupt cleared (to 0) 1 0 e_int3 interrupt set (to 1) other than above e_int3 interrupt not changed 11, 3 set e_int3, clear e_int3 chapter 11 fcan controller 581 user?s manual u14492ej4v1ud (3/3) (b) write (2/2) bit position bit name function sets/clears the e_int2 bit. set e_int2 c lear e_int 2 operation 0 1 e_int2 interrupt cleared (to 0) 1 0 e_int2 interrupt set (to 1) other than above e_int2 interrupt not changed 10, 2 set e_int2, clear e_int2 sets/clears the e_int1 bit. set e_int1 c lear e_int1 operation 0 1 e_int1 interrupt cleared (to 0) 1 0 e_int1 interrupt set (to 1) other than above e_int1 interrupt not changed 9, 1 set e_int1, clear e_int1 sets/clears the e_int0 bit. set e_int0 clear e_int0 operation 0 1 e_int0 interrupt cleared (to 0) 1 0 e_int0 interrupt set (to 1) other than above e_int0 interrupt not changed 8, 0 set e_int0, clear e_int0 chapter 11 fcan controller 582 user?s manual u14492ej4v1ud (25) can1 bus active register (c1ba) the c1ba register indicates frame information output via the can bus. this register is read-only, in 16-bit units. 14 0 13 0 12 cact4 2 tmno2 3 tmno3 4 tmno4 5 tmno5 6 tmno6 7 tmno7 8 cact0 9 cact1 10 cact2 11 cact3 15 0 1 tmno1 0 tmno0 c1ba address xxxxmc5ah note initial value 00ffh bit position bit name function indicates can module status. cact4 cact3 cact2 cact1 cact0 can module status 0 0 0 0 0 reset state 0 0 0 0 1 bus idle wait 0 0 0 1 0 bus idle state 0 0 0 1 1 start of frame 0 0 1 0 0 standard identifier area 0 0 1 0 1 data length code area 0 0 1 1 0 data field area 0 0 1 1 1 crc field area 0 1 0 0 0 crc delimiter 0 1 0 0 1 ack slot 0 1 0 1 0 ack delimiter 0 1 0 1 1 end of frame area 0 1 1 0 0 intermission state 0 1 1 0 1 suspend transmission 0 1 1 1 0 error frame 0 1 1 1 1 error delimiter wait 1 0 0 0 0 error delimiter 1 0 0 1 0 extended identifier area 12 to 8 cact4 to cact0 7 to 0 tmno7 to tmno0 specifies transmit message counter. 0 to 31: message number of message awai ting transmission or being transmitted 32 to 254: not used 255: no messages awaiting transmission or being transmitted note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 583 user?s manual u14492ej4v1ud (26) can1 bit rate prescaler register (c1brp) the c1brp register is used to set the transmission baud rate for the can module. use the c1brp register to select the can protocol layer base system clock (f btl ). the baud rate is determined by the value set to the c1sync register. while in normal operation mode (c1def register?s mo m bit = 0), the c1brp register can only be accessed when the initialization mode has been set (c1ctrl register?s init bit = 1). this register can be read/ written in 16-bit units. caution while in diagnostic pro cessing mode (c1def register?s mo m bit = 1), the c1brp register can only be accessed when the initialization mode has been set (c1ctrl register?s init bit = 1) (refer to 11.10 (21) can1 definition register (c1def)). chapter 11 fcan controller 584 user?s manual u14492ej4v1ud (1/2) 14 0 13 0 12 0 2 brp2 3 brp3 4 brp4 5 brp5 6 btype 7 0 8 0 9 0 10 0 11 0 15 tlm 1 brp1 0 brp0 c1brp (tlm = 0) address xxxxmc5ch note initial value 0000h 14 0 13 0 12 0 2 brp2 3 brp3 4 brp4 5 brp5 6 brp6 7 brp7 8 btype 9 0 10 0 11 0 15 tlm 1 brp1 0 brp0 c1brp (tlm = 1) (a) when tlm = 0 bit position bit name function 15 tlm specifies transfer layer mode. 0: 6-bit prescaler mode 6 btype specifies can bus type. 0: low speed ( 125 kbps) 1: high speed (> 125 kbps) specifies can protocol la yer base system clock (f btl ) for can module. n brp5 brp4 brp3 brp2 brp1 brp0 can protocol layer base system clock (f btl ) 0 0 0 0 0 0 0 f mem /2 1 0 0 0 0 0 1 f mem /4 2 0 0 0 0 1 0 f mem /6 3 0 0 0 0 1 1 f mem /8 f mem /(n + 1) 2 60 1 1 1 1 0 0 f mem /122 61 1 1 1 1 0 1 f mem /124 62 1 1 1 1 1 0 f mem /126 63 1 1 1 1 1 1 f mem /128 5 to 0 brp5 to brp0 remark f btl = f mem /{(n + 1) 2}: can protocol layer base system clock n = 0 to 63 (set by bits brp5 to brp0) f mem = can base clock note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 585 user?s manual u14492ej4v1ud (2/2) (b) when tlm = 1 bit position bit name function 15 tlm specifies transfer layer mode. 1: 8-bit prescaler mode 8 btype specifies can bus type. 0: low speed ( 125 kbps) 1: high speed (> 125 kbps) specifies can protocol la yer base system clock (f btl ) for can module. n brp7 brp6 brp5 brp4 brp3 brp2 brp1 brp0 can protocol layer base system clock (f btl ) 0 0 0 0 0 0 0 0 0 setting prohibited 1 0 0 0 0 0 0 0 1 f mem /2 2 0 0 0 0 0 0 1 0 f mem /3 3 0 0 0 0 0 0 1 1 f mem /4 f mem /(n + 1) 252 1 1 1 1 1 1 0 0 f mem /253 253 1 1 1 1 1 1 0 1 f mem /254 254 1 1 1 1 1 1 1 0 f mem /255 255 1 1 1 1 1 1 1 1 f mem /256 7 to 0 brp7 to brp0 remark f btl = f mem /(n + 1): can protocol layer base system clock n = 0 to 255 (set by bits brp7 to brp0) f mem = can base clock chapter 11 fcan controller 586 user?s manual u14492ej4v1ud (27) can1 bus diagnostic information register (c1dinf) the c1dinf register indicates all can bus bits, includin g stuff bits, delimiters, etc. this information is used only for diagnostic purposes. because the number of bits starting fr om sof is added at each frame, the ac tual number of bits is the value obtained by subtracting the previous data. this register is read-only, in 16-bit units. cautions 1. while in diagnostic processing mode (c1def register ?s mom bit = 1) and in normal operation mode (c1ctrl register ?s init bit = 0), the c1dinf register can only be accessed. in normal operation mode (c1def register?s mom bit = 0), this register cannot be accessed. 2. storage of the last 8 bi ts is automatically stopped if an error or a valid message (ack delimiter) is detected on the can bus. reset is automatically performed each time when the sof is detected on the can bus. 14 dinf14 13 dinf13 12 dinf12 2 dinf2 3 dinf3 4 dinf4 5 dinf5 6 dinf6 7 dinf7 8 dinf8 9 dinf9 10 dinf10 11 dinf11 15 dinf15 1 dinf1 0 dinf0 c1dinf address xxxxmc5ch note initial value 0000h bit position bit name function indicates can bus diagnostic information. bit name can bus diagnostic information dinf15 to dinf8 number of bits starting from sof dinf7 to dinf0 information from last 8 bits 15 to 0 dinf15 to dinf0 note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 587 user?s manual u14492ej4v1ud (28) can1 synchronization c ontrol register (c1sync) the c1sync register controls the data bit time for transmission speed. this register can be read/written in 16-bit units. cautions 1. the cpu is able to r ead the c1sync register at any time. 2. writing to the c1sync register is enable d when in initialization mode (when c1ctrl register?s init bit = 1). 3. the limit values of the can protocol when setting the sptn bit and dbtn bit are as follows. 5 btl spt (sampling point) 17 btl [4 spt4 to spt0 set values 16] 8 btl dbt (data bit time) 25 btl [7 dbt4 to dbt0 set values 24] sjw (synchronization jump width) dbt ? spt 2 (dbt ? spt) 8 remark btl = 1/f btl (f btl : can protocol layer base system clock) (1/3) 14 0 13 0 12 samp 2 dbt2 3 dbt3 4 dbt4 5 spt0 6 spt1 7 spt2 8 spt3 9 spt4 10 sjw0 11 sjw1 15 0 1 dbt1 0 dbt0 c1sync address xxxxmc5eh note initial value 0218h bit position bit name function 12 samp specifies bit sampling. 0: receive data sampled once at the sampling point. 1: receive data sampled three times and the majority value used as the sampled value. specifies synchronization jump wi dth stipulated in the can protocol specification, ver. 2.0, partb active. sjw1 sjw0 synchroni zation jump width note 0 0 btl 0 1 btl 2 1 0 btl 3 1 1 btl 4 11, 10 sjw1, sjw0 note stipulated in can protocol specification ver. 2.0, partb active remark btl = 1/f btl (f btl : can protocol laye r base system clock) note xxxx: can message buffer registers can be a llocated to the xxxx addr esses as programmable peripheral i/o registers. note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, a, e chapter 11 fcan controller 588 user?s manual u14492ej4v1ud (2/3) bit position bit name function specifies position of sampling points. spt4 spt3 spt2 spt1 spt0 position of sampling point 0 0 0 1 0 btl 3 note 0 0 0 1 1 btl 4 note 0 0 1 0 0 btl 5 0 0 1 0 1 btl 6 0 0 1 1 0 btl 7 0 0 1 1 1 btl 8 0 1 0 0 0 btl 9 0 1 0 0 1 btl 10 0 1 0 1 0 btl 11 0 1 0 1 1 btl 12 0 1 1 0 0 btl 13 0 1 1 0 1 btl 14 0 1 1 1 0 btl 15 0 1 1 1 1 btl 16 1 0 0 0 0 btl 17 9 to 5 spt4 to spt0 other than above setting prohibited note this setting is reserved for setting sample point extension and is not compliant with the can protocol specifications. remark sampling point within bit timing is selected. chapter 11 fcan controller 589 user?s manual u14492ej4v1ud (3/3) bit position bit name function sets data bit time. dbt4 dbt3 dbt2 dbt1 dbt0 data bit time 0 0 1 1 1 btl 8 0 1 0 0 0 btl 9 0 1 0 0 1 btl 10 0 1 0 1 0 btl 11 0 1 0 1 1 btl 12 0 1 1 0 0 btl 13 0 1 1 0 1 btl 14 0 1 1 1 0 btl 15 0 1 1 1 1 btl 16 1 0 0 0 0 btl 17 1 0 0 0 1 btl 18 1 0 0 1 0 btl 19 1 0 0 1 1 btl 20 1 0 1 0 0 btl 21 1 0 1 0 1 btl 22 1 0 1 1 0 btl 23 1 0 1 1 1 btl 24 1 1 0 0 0 btl 25 4 to 0 dbt4 to dbt0 other than above setting prohibited remark 1-bit data length is set for can bus. remark btl = 1/f btl (f btl : can protocol layer base system clock) 11.11 operations 11.11.1 initialization processing figure 11-27 shows a flowchart of initialization processing. the register setting flow is shown in figures 11-28 to 11-40. chapter 11 fcan controller 590 user?s manual u14492ej4v1ud figure 11-27. initialization processing start set can main clock selection register (cgcs) : see figure 11-28 can main clock selection register (cgcs) settings : see figure 11-29 can global interrupt enable register (cgie) settings : see figure 11-30 can global status register (cgst) settings : see figure 11-31 can1 bit rate prescaler register (c1brp) settings : see figure 11-32 can1 synchronization control register (c1sync) settings : see figure 11-33 can1 interrupt enable register (c1ie) settings : see figure 11-34 can1 definition register (c1def) settings : see figure 11-35 can1 control register (c1ctrl) settings : see figure 11-36 can1 address mask a registers l and h (c1maskla and c1maskha) (a = 0 to 3) settings : see figure 11-37 message buffer settings set can global interrupt enable register (cgie) set can global status register (cgst) set can1 bit rate prescaler (c1brp) set init = 1 (c1ctrl) set can1 synchronization control register (c1sync) set can1 interrupt enable register (c1ie) set can1 definition register (c1def) set can1 control register (c1ctrl) mask required for message id? set message buffer (repeat as many times as number of messages) clear init = 1 (c1ctrl) istat = 0? (c1ctrl) end yes yes yes no no no istat = 1? (c1ctrl) set mask (c1maska) cstp = 1? (cstop) no yes cstp = 0 (cstop) chapter 11 fcan controller 591 user?s manual u14492ej4v1ud figure 11-28. can main clock sel ection register (cgcs) settings start f mem f gts1 f gts select clock for memory access controller (mcp0 to mcp3) f mem = f mem1 /(n + 1) n = 0 to 15 (set using bits mcp0 to mcp3) f gts = f gts1 /(n + 1) n = 0 to 255 (set using bits cgts0 to cgts7) gtcs1, gtcs0 = 00: f gts1 = f mem /2 gtcs1, gtcs0 = 01: f gts1 = f mem /4 gtcs1, gtcs0 = 10: f gts1 = f mem /8 gtcs1, gtcs0 = 11: f gts1 = f mem /16 select global timer clock (gtcs0, gtcs1) select system timer prescaler (cgts0 to cgts7) remark f mem = can base clock f mem1 = clock supplied to can f gts1 = global timer clock f gts = system timer prescaler figure 11-29. can global interrupt enable register (cgie) settings start no enable interrupt for g_ie1 bit yes set g_ie1 = 1 clear g_ie1 = 0 no enable interrupt for g_ie2 bit an interrupt occurs if a memory address in the undefined area is accessed. an interrupt occurs if the gom bit is not cleared (0) under the following conditions. when shutdown is disabled (efsd bit = 0) when a can module not in the initialization status (istat bit = 0) exists an interrupt occurs if an illegal write access is made to the temp buffer when the gom bit = 1. an interrupt occurs if the can module register (register starting with ?c1?) is accessed when the gom bit = 0. yes set g_ie2 = 1 clear g_ie2 = 0 remark gom: bit of can global status register (cgst) efsd: bit of can global status register (cgst) istat: bit of can1 control register (c1ctrl) chapter 11 fcan controller 592 user?s manual u14492ej4v1ud figure 11-30. can global status register (cgst) settings start no use time stamp function? yes set tsm = 1 clear tsm = 0 start fcan operation set gom = 1 clear gom = 0 figure 11-31. can1 bit rate prescaler register (c1brp) settings start no transfer speed is 125 kbps or less yes btype = 0 (low speed) f btl setting when tlm = 0 brp5 to brp0 when tlm = 1 brp7 to brp0 when tlm = 0 when tlm = 1 f btl = f mem /{(n + 1) 2} n = 0 to 63 (set using bits brp5 to brp0) f btl = f mem /(n + 1) n = 0 to 255 (set using bits brp7 to brp0) f btl btype = 1 (high speed) remark f btl = can protocol layer base system clock f mem = can base clock chapter 11 fcan controller 593 user?s manual u14492ej4v1ud figure 11-32. can1 synchronization co ntrol register (c1sync) settings start no samp = 0 set data bit time (dbt4 to dbt0) 1 bit time = btl (m + 1) m = 7 to 24 (set using bits dbt4 to dbt0) sampling point = btl (m + 1) m = 2 to 16 (set using bits spt4 to spt0) note set sampling point (spt4 to spt0) set sjw (sjw1, sjw0) samp = 1 yes set once-only (single shot) sampling set sampling for one location only set sampling for three locations sjw = btl ( m + 1) m = 0 to 3 (set using bits sjw1 and sjw0) note the setting of m = 2, 3 is reserved for setting samp le point extension, and is not compliant with the can protocol specifications. remark btl = 1/f btl (f btl : can protocol layer base system clock) chapter 11 fcan controller 594 user?s manual u14492ej4v1ud figure 11-33. can1 interrupt enab le register (c1ie) settings set e_int0 = 1 clear e_int0 = 0 start no yes yes yes yes yes yes yes clear e_int0 = 1 set e_int0 = 0 enable interrupt for e_int0? interrupt enable flag for end of transmission set e_int1 = 1 clear e_int1 = 0 no clear e_int1 = 1 set e_int1 = 0 enable interrupt for e_int1? interrupt enable flag for end of reception set e_int2 = 1 clear e_int2 = 0 no clear e_int2 = 1 set e_int2 = 0 enable interrupt for e_int2? interrupt enable flag for error passive or bus off by tec set e_int3 = 1 clear e_int3 = 0 no clear e_int3 = 1 set e_int3 = 0 enable interrupt for e_int3? interrupt enable flag for error passive by rec set e_int4 = 1 clear e_int4 = 0 no clear e_int4 = 1 set e_int4 = 0 enable interrupt for e_int4? interrupt enable flag for wake-up from can sleep mode set e_int5 = 1 clear e_int5 = 0 no clear e_int5 = 1 set e_int5 = 0 enable interrupt for e_int5? interrupt enable flag for can bus error set e_int6 = 1 clear e_int6 = 0 no clear e_int6 = 1 set e_int6 = 0 enable interrupt for e_int6? interrupt enable flag for can error chapter 11 fcan controller 595 user?s manual u14492ej4v1ud figure 11-34. can1 definition register (c1def) settings set mom = 1 clear mom = 0 start no yes yes yes yes clear mom = 1 set mom = 0 set to diagnostic processing mode? normal operation mode normal operation mode transmit priority is determined based on message numbers diagnostic processing mode transmit priority is determined based on identifiers single shot mode: transmit only once. do not retransmit. clear dgm = 1 set dgm = 0 no set dgm = 1 clear dgm = 0 store to buffer note used for diagnostic processing mode? clear pbb = 1 set pbb = 0 no set pbb = 1 clear pbb = 0 determine transmit priority based on identifiers? set ssht = 1 clear ssht = 0 no clear ssht = 1 set ssht = 0 set single shot mode? note bits 5 to 3 (mt2 to mt0) in can message configur ation register n (m_confn) (n = 00 to 31) are set as ?111? chapter 11 fcan controller 596 user?s manual u14492ej4v1ud figure 11-35. can1 control re gister (c1ctrl) settings start yes clear tmr = 1 set tmr = 0 store timer value when sof occurs? set time stamp for receiving set overwrite for receive message buffer set dominant level for transmit pins set dominant level for receive pins store timer value when eof occurs do not overwrite message in dn flag (delete new message) set dominant level to high level set dominant level to high level set ovm = 1 clear ovm = 0 yes clear ovm = 1 set ovm = 0 store message of dn flag? set dlevt = 1 clear dlevt = 0 yes clear dlevt = 1 set dlevt = 0 set dominant level to low level? set dlevr = 1 clear dlevr = 0 yes no no no no clear dlevr = 1 set dlevr = 0 set dominant level to low level? set tmr = 1 clear tmr = 0 chapter 11 fcan controller 597 user?s manual u14492ej4v1ud figure 11-36. can1 address mask a registers l and h (c1maskla and c1maskha) (a = 0 to 3) settings start standard frame mask setting for standard frame (x = 18 to 28) mask setting for extended frame (x = 0 to 28) mask setting for message id format no cmidx = 0 cmidx = 1 mask id bit? yes yes no yes cmide = 0 cmide = 1 check id type? no no cmidx = 0 cmidx = 1 mask id bit? yes cmidy = 1 (y = 0 to 17) chapter 11 fcan controller 598 user?s manual u14492ej4v1ud figure 11-37. message buffer settings start no standard frame? set message id type yes i ide = 0 (standard) (m_idhn) set message configuration see figure 11-38 can message configuration registers 00 to 31 (m_conf00 to m_conf31) settings see figure 11-39 can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) settings ide = 1 (extended) (m_idhn) set identifier (standard, extended) set message control byte set message length see figure 11-40 can message status registers 00 to 31 (m_stat00 to m_stat31) settings set message status remark n = 00 to 31 chapter 11 fcan controller 599 user?s manual u14492ej4v1ud figure 11-38. can message configuration regist ers 00 to 31 (m_conf00 to m_conf31) settings start use message buffer? release can message buffer yes yes ma = 0 ma = 1 yes no no no no no no no mt2 to mt0 = 111 (used in diagnostic processing mode) mt2 to mt0 = 000 mt2 to mt0 = 001 mt2 to mt0 = 010 mt2 to mt0 = 011 mt2 to mt0 = 100 mt2 to mt0 = 101 yes yes yes yes transmit message receive message (no mask setting) receive message (set mask 0) receive message (set mask 1) receive message (set mask 2) receive message (set mask 3) remark n = 00 to 31 chapter 11 fcan controller 600 user?s manual u14492ej4v1ud figure 11-39. can message control register s 00 to 31 (m_ctrl00 to m_ctrl31) settings start yes no no rtr = 0 rtr = 1 transmit/receive remote frame transmit/receive data frame? set remote frame auto acknowledge function yes no ie = 0 ie = 1 enable interrupt disable interrupt? yes no rmde0 = 1 rmde0 = 0 remote frame auto acknowledge? yes no rmde1 = 1 rmde1 = 0 ats = 1 ats = 0 set dn flag? yes apply time stamp? set dn flag when remote frame is received chapter 11 fcan controller 601 user?s manual u14492ej4v1ud figure 11-40. can message status registers 00 to 31 (m_stat00 to m_stat31) settings start clear dn flag clear dn = 1, set dn = 0 (sc_statm) clear trq flag clear trq = 1, set trq = 0 (sc_statm) clear rdy flag clear rdy = 1, set rdy = 0 (sc_statm) remark m = 00 to 31 chapter 11 fcan controller 602 user?s manual u14492ej4v1ud 11.11.2 transmit setting transmit messages are output from the target message buffer. figure 11-41. transmit setting start end of transmit operation note set rdy flag set rdy = 1, clear rdy = 0 (sc_statn) set data (m_datanm) select transmit message buffer set transmit request flag set trq = 1, clear trq = 0 (sc_statn) no yes trq = 0? (m_statn) note the rdy flag is not automatically cleared, so clear it by clearing the set rdy bit to 0 and set the clear rdy bit to 1. remark n = 00 to 31, m = 0 to 7 chapter 11 fcan controller 603 user?s manual u14492ej4v1ud 11.11.3 receive setting receive messages are retrieved from the target message buffer. figure 11-42. setting of receive completion interr upt and reception operati on using reception polling start receive completion interrupt occurs set rdy flag set rdy = 1, clear rdy = 0 (sc_statn) end of receive operation yes receive data frame no yes receive data frame? receive remote frame : detection methods <1> detect using can1 information register (c1last) <2> detect using can message search start/result register (cgmss/cgmsr) (see figure 11-43 can message search start/result register (cgmss/cgmsr) settings ) no dn = 0 (m_statn) detect target message buffer clear dn flag clear dn = 1, set dn = 0 (sc_statn) get data length transmit operation get time stamp get data remark n = 00 to 31 chapter 11 fcan controller 604 user?s manual u14492ej4v1ud figure 11-43. can message search start/r esult register (cgmss/cgmsr) settings start yes yes search non mask- linked messages only search all messages (regardless of mask setting) do not check message id format search standard id only check message id? no no cide = 1 (cgmss) cide = 0 (cgmss) cmsk = 0 (cgmss) get search results check dn flag (cdn = 1) check masked messages? cmsk = 1 (cgmss) set start position and start search chapter 11 fcan controller 605 user?s manual u14492ej4v1ud 11.11.4 can sleep mode in can sleep mode, the fcan controller can be set to standby mode. a wake-up occurs when there is a bus operation. figure 11-44. can sleep mode settings start end of can sleep mode settings no yes sleep = 1 (c1ctrl) set sleep = 1 clear sleep = 0 (c1ctrl) figure 11-45. clearing of can sleep mode by can bus active status start can bus active sleep = 0 (c1ctrl) wake = 1 (c1def) wake-up interrupt occurs end of can sleep mode clearing operation chapter 11 fcan controller 606 user?s manual u14492ej4v1ud figure 11-46. clearing of can sleep mode by cpu clear sleep = 1 set sleep = 0 (c1ctrl) sleep = 0 (c1ctrl) start end of can sleep mode clearing operation 11.11.5 can stop mode in can stop mode, the fcan controller can be set to st andby mode. no wake-up occurs when there is a bus operation (stop mode is controlled by cpu access only). figure 11-47. can stop mode settings start end of can stop mode settings yes sleep = 1 (c1ctrl) no set stop = 1 clear stop = 0 (c1ctrl) set can sleep mode (see figure 11-44 ) yes stop = 1 (c1ctrl) no chapter 11 fcan controller 607 user?s manual u14492ej4v1ud figure 11-48. clearing of can stop mode start end of can stop mode clearing operation clear stop = 1 set stop = 0 clear sleep = 1 set sleep = 0 (c1ctrl) stop = 0 sleep = 0 (c1ctrl) chapter 11 fcan controller 608 user?s manual u14492ej4v1ud 11.12 rules for correct setting of baud rate the can protocol limit values for ensuri ng correct operation of fcan are described below. if these limit values are exceeded, a can protocol violation may occur, which can resu lt in operation faults. always make sure that settings are within the range of limit values. (a) 5 btl spt (sampling point) 17 btl [4 spt4 to spt0 set values 16] (b) 8 btl dbt (data bit time) 25 btl [7 dbt4 to dbt0 set values 24] (c) sjw (synchronization jump width) dbt ? spt (d) 2 (dbt ? spt) 8 remark btl = 1/f btl (f btl : can protocol layer base system clock) spt4 to spt0 (bits 9 to 5 of can1 synch ronization control register (c1sync)) dbt4 to dbt0 (bits 4 to 0 of can1 syn chronization control register (c1sync)) (1) example of fcan baud rate setting (w hen c1brp register?s tlm bit = 0) the following is an example of how correct settings for the c1brp register and c1sync register can be calculated. conditions from can bus: <1> can base clock frequency (f mem ): 16 mhz <2> can bus baud rate: 83 kbps <3> sampling point: 80% or more <4> synchronization jump width: 3 btl first, calculate the ratio between the can base clock frequency and the can bus baud rate frequency as shown below. f mem /can bus baud rate = 16 mhz/83 khz 192.77 2 6 3 set an even number between 2 and 128 to the c1brp register?s bits brp5 to brp0 as the setting for the prescaler (can protocol layer base system clock: f btl ), then set a value between 8 and 25 to the c1sync register?s bits dbt4 to dbt0 as the data bit time. since it is assumed that the sjw (synchronization jump width) value is 3, the maximum setting for spt (sampling point) is 3 less than the data bit time setting and is 17. (spt dbt ? 3 and spt = 17) chapter 11 fcan controller 609 user?s manual u14492ej4v1ud given the above limit values, the following four settings are possible. prescaler dbt spt (max.) calculated spt 24 8 5 5/8 = 62.5% 16 12 9 9/12 = 75% 12 16 13 13/16 = 81% 8 24 17 17/24 = 71% 16 mhz/83 kbps ? 192 = 64 3 <1> = 48 4 <2> = 32 6 <3> = 24 8 <4> = 16 12 <5> = 12 16 <6> = 8 24 <7> = 6 32 <8> = 4 48 <9> = 3 64 <10> the settings that can actually be made for the v850e/ia1 are in the range from <4> to <7> above (the section enclosed in broken lines). among these options in the range from <4> to <7> above, option <6> is the ideal setting for the specifications when actually setting the register. (i) prescaler (can protocol layer base system clock: f btl ) setting f btl is calculated as below. ? f btl = f mem /{(a + 1) 2} : [0 a 63] value a is set using bits 5 to 0 (brp5 to brp0) of the c1brp register. f btl = 16 mhz/12 = 16 mhz/{(5 + 1) 2} thus a = 5 therefore, c1brp register = 0005h chapter 11 fcan controller 610 user?s manual u14492ej4v1ud (ii) dbt (data bit time) setting dbt is calculated as below. ? dbt = btl (a + 1) : [7 a 24] value a is set using bits 4 to 0 (dbt4 to dbt0) of the c1sync register. dbt = btl 16 = btl (a + 1) thus a = 15 therefore, c1sync register?s bits dbt4 to dbt0 = 01111b note that 1/dbt = f btl /16 ? 1333 khz/16 ? 83 kbps (nearly equal to the can bus baud rate) (iii) spt (sampling point) setting given sjw = 3: sjw dbt ? spt 3 16 ? spt spt 13 therefore, spt is set as 13 (max.) spt is calculated as below. ? spt = btl (a + 1) : [4 a 16] value a is set using bits 9 to 5 ( spt4 to spt0) of the c1sync register. spt = btl 13 = btl (12 + 1) thus a = 12 therefore, the spt4 to spt0 bits of the c1sync register = 01100b (iv) sjw (synchronization jump width) setting sjw is calculated as below. ? sjw = btl (a + 1) : [0 a 3] value a is set using bits11 and 10 (sjw1, sjw0) of the c1sync register. c1sync register?s bits sjw1 and sjw0 = btl 3 = btl (2 + 1) thus a = 2 therefore, the sjw1 and sjw0 bits of the c1sync register = 10b. the c1sync register settings based on these results are shown in figure 11-49 below. chapter 11 fcan controller 611 user?s manual u14492ej4v1ud figure 11-49. c1sync register settings 15 14 13 12 11 10 9 8 c1sync 0 0 0 samp sjw1 sjw0 spt4 spt3 setting 0 0 0 0 1 0 0 1 7 6 5 4 3 2 1 0 spt2 spt1 spt0 dbt4 dbt3 dbt2 dbt1 dbt0 setting 1 0 0 0 1 1 1 1 chapter 11 fcan controller 612 user?s manual u14492ej4v1ud 11.13 ensuring data consistency when the cpu reads data from can message buffers, it is essential for the read data to be consistent. two methods are used to ensure data consist ency: sequential data read and burst read mode. 11.13.1 sequential data read when the cpu performs sequential access of a can message buffer, data is read from the buffer in the order shown in figure 11-50 below. only the fcan internal operation can set the m_statn register?s dn bit (to 1) and only the cpu can clear it (to 0), so during the read operation the cpu must be able to check whether or not any new data has been stored in the message buffer. figure 11-50. sequential data read read cpu end of cpu?s read operation yes dn = 0 (m_statn) no clear dn flag clear dn = 1, set dn = 0 (sc_statn) read data from message buffer remark n = 00 to 31 chapter 11 fcan controller 613 user?s manual u14492ej4v1ud 11.13.2 burst read mode burst read mode is implemented in the fcan to enable faster access to complete messages and secure the synchrony of data. burst read mode starts up automatically each time the cpu reads the m_dlcn register and data is then copied from the message buffer area to a temporary read buffer. data continues to be read from the temporary buffer as lo ng as the cpu keeps directly incrementing (+1) the read address (when data is read in the following order: m_dlcn register m_ctrln register m_timen register m_datan0 to m_datan7 registers m_idln, m_idhn register). if these linear address rules are not followed or if access is attempted to an address that is lower than the m_idhn register?s address (such as the m_confn register or m_statn register), burst read mode becomes invalid. cautions 1. 16-bit read access is required for the memory buffer area wh en using the burst read mode. if 8-bit access (byte read operation) is attemp ted, burst read mode does not start up even if the address is linearly incremen ted (+1) as described above. 2. be sure to read out the value of fcan c ontrol registers other than the m_dlcn register before starting the burst read mode. remark n = 00 to 31 chapter 11 fcan controller 614 user?s manual u14492ej4v1ud 11.14 interrupt conditions 11.14.1 interrupts that are ge nerated for fcan controller when interrupts are enabled (condition <1>: m_ctrln regist er?s ie bit = 1, conditions other than <1>: c1ie register?s interrupt enable flag = 1), interrupts will be ge nerated under the following conditions (n = 00 to 31). <1> message-related operation has succeeded when a message has been received in the receive message buffer when a remote frame has been received in the transmit message buffer (when auto acknowledge mode has not been set, i. e., when the m_ctrln register?s rmde0 bit = 0) when a message has been transmitted from the transmit message buffer <2> when a can bus error has been detected bit error bit stuff error form error crc error ack error <3> when the can bus mode has been changed error passive status elapsed while fcan was transmitting bus off status was set while fcan was transmitting error passive status elapsed while fcan was receiving <4> internal error overrun error 11.14.2 interrupts that are ge nerated for global can interface interrupts are generated for the global ca n interface under the following conditions. ? an undefined area is accessed ? if the gom bit is cleared to 0 when one of the can modu les is not in the initializat ion status (istat bit of c1ctrl register = 0) with the efsd bit of the cgst register = 0 ? a can module register (register starting with ?c1?) is accessed when the gom bit of the cgst register = 0 ? a temporary buffer (in the area following the address of the c1sync register) is accessed when the gom bit of the cgst register = 1 chapter 11 fcan controller 615 user?s manual u14492ej4v1ud 11.15 how to shut down fcan controller the following procedure should be used to stop can bus oper ations in order to stop the clock supply to the can interface (to set low power mode). <1> fcan controller?s initialization mode setting set initialization mode (init bit = 1 in c1ctrl r egister (set init bit = 1, clear init bit = 0)) <2> stop time stamp counter set tsm bit = 0 in cgst register (set tsm bit = 0, clear tsm bit = 1) <3> stop can interface set gom bit = 0 in cgst register (set gom bit = 0, clear gom bit = 1) stop can clock caution if the above procedure is not performed correctly, the can interface (in active status) can cause operation faults. chapter 11 fcan controller 616 user?s manual u14492ej4v1ud 11.16 cautions on use <1> bit manipulation is prohibited for all fcan controller registers. <2> be sure to properly clear (0) all interrupt request flags note in the interrupt routine. if these flags are not cleared (0), subsequent interrupt requests may not be gener ated. note also that if an interrupt is generated at the same time as a cpu clear operation, that interr upt request flag will not be cl eared (0). it is therefore important to confirm that interrupt reques t flags have been properly cleared (0). note see 11.10 (10) can interrupt pending register (ccintp) , 11.10 (11) can global interrupt pending register (cgintp) , and 11.10 (12) can1 interrupt pending register (c1intp) . <3> when a change occurs on the can bus via a setting of the cstp bit in the cstop register while the clock supply to the cpu or peripheral function s is stopped, the cpu can be woken up. <4> do not read the same register of the fcan controller twice or more in a row. if the same register is read twice or more in a row, and even if the value of the register is changed wh ile it is being read the second or subsequent time, the new value is not reflected, and th e same value as the one read the first time is always read. example reading the c1ctrl and c1ba registers (i) correct usage: new value is reflec ted when c1ctrl is read the second time. c1ctrl read c1ba read c1ctrl read (ii) incorrect usage: the second read value of c1ctrl is the same as the first read value of c1ctrl. c1ctrl read c1ctrl read c1ba read <5> when receiving a remote frame with an extended id and storing it in the receive message buffer, the values of dlc3 to dlc0 in the message buffer are cleared to 0 regardless of the values of dlc3 to dlc0 on the can bus. chapter 11 fcan controller 617 user?s manual u14492ej4v1ud <6> if the os (osek/com) is not used, be su re to execute the following processing. [when can communication is performe d using an interrupt routine] ? clear (0) the following interrupt pending bits at t he start of the correspond ing interrupt routine. ? c1intm bit of c1intp register (m = 0 to 6) ? gint1 bit of cgintp register (m = 1 to 3) ? clear (0) the following enable bits dur ing the corresponding interrupt routine. ? e_intm bit of c1ie register (m = 0 to 6) ? g_ien bit of cgie register (n = 1, 2) [when can communication is perfo rmed by polling of bits, not using interrupt routines] ? the following interrupt mask flags and interrupt ena ble bits are used when set (1) (do not clear (0) them). ? canmkn bit of canicn register (n = 0 to 3) ? e_intm bit of c1ie register (m = 0 to 6) ? g_ien bit of cgie register (n = 1, 2) ? ie bit of m_ctrln register (n = 00 to 31) ? clear (0) the following interrupt pending bits in accordance with procedures (i) to (iii) below. ? c1intm bit of c1intp register (m = 0 to 6) ? gintn bit of cgintp register (n = 1 to 3) (i) poll the corresponding interrupt request flag. (ii) if the value of the bit in procedure (i) is 1, clear (0) the corresponding interrupt pending bit. (iii) after executing procedure (ii), clear (0) the interrupt request flag. example can reception (i) poll until the canif0 bit of the canic0 register becomes 1. (ii) clear (0) the c1int1 bit of the c1intp register. (iii) clear (0) the canif0 bit of the canic0 register. <7> when emulating the fcan controll er using the in-circuit emulator (ie-v850e-mc or ie-703116-mc-em1), perform the following settings in the configuration screen that appears when the debugger is started. ? set the start address of the programmable peripheral i/o area that is set using the bpc register to the programable i/o area field. ? maps the programmable peripheral i/o area as ?tar get? or ?emulation ram? in the memory mapping field. 618 user?s manual u14492ej4v1ud chapter 12 nbd function ( pd70f3116) the v850e/ia1 provides the non break debu g (nbd) function for on-chip data tuning. 12.1 overview the nbd function encompasse s the following functions. (1) ram monitoring function this function makes an arbitrary ram area readabl e or writable using an nbd tool via dma. [corresponding ram area] xfffc000h to xfffe7ffh if executed using an address outside the above, the function instantly returns ?ready?. output is undefined on a read, and the writ e operation is not performed on a write. (2) event detection function by having a comparator (24-bit address setting) for ma tch detection on-chip at a single point, this function outputs a match trigger (falling edge) to the nbd t ool when the address match detection shown below is performed. the lower 2 bits are masked. ? execution pc address match detection ? internal ram area address write timing match detection [detection range] rom: x0000000h to x003ffffh ram: xfffc000h to xfffe7ffh table 12-1. nbd block dedicated pin summary pin name i/o function summary clk_dbg input serial cloc k input for debugging interface sync input synchronization signal for debugging ad0_dbg to ad3_dbg i/o command data and ram data i/o (4 bits) trig_dbg output outputs trigger (falling edge) synchroni zed to timing of write to arbitrary specified ram address or to timing of execution of instruction at specified address. chapter 12 nbd function ( pd70f3116) 619 user?s manual u14492ej4v1ud figure 12-1. image of nbd space v850e/ia1 not possible cpu nbd : non break debug nbd unit nbd dedicated interface (7 ways) nbd tool caution the debug function does not opera te under the following conditions. ? during reset period ? until dma initialization termination after reset ? software stop mode/idle mode ? oscillation stabilization time (during tbc count) 12.2 nbd function register map table 12-2 shows a map of the control registers of the nbd function. nbd s pace does not exist in the internal space of the cpu but exists independent ly as nbd space. because of this, nbd space is space that cannot be read or written from within the cpu but can only be read or written from the nbd dedicated interface (refer to figure 12-1 ). table 12-2. nbd space map address register name symbol r/w after reset 000h chip id register 0 tid0 4eh 001h chip id register 1 tid1 01h 002h chip id register 2 tid2 r 01h 800h evtu_a0 to evtu_a7 undefined 801h evtu_a8 to evtu_a15 undefined 802h evtu_a16 to evtu_a23 undefined 803h user event address setting register evtu_a24 to evtu_a27 undefined 820h user event condition setting register evtu_c0 r/w undefined caution since the v850e/ia1 nbd uses dma that is on- chip in the v850e1 cpu core, settings for dma are initialized after reset. chapter 12 nbd function ( pd70f3116) 620 user?s manual u14492ej4v1ud 12.3 nbd function protocol the basic protocol of the nbd function is shown below. (1) basic protocol figure 12-2. basic protocol (1) on a read clk_dbg sync ad0_dbg to ad3_dbg n address section command packet flag sense control section nr data packet (2) on a write clk_dbg sync ad0_dbg to ad3_dbg nn r address section data section command packet flag sense control section remark n: not ready r: ready chapter 12 nbd function ( pd70f3116) 621 user?s manual u14492ej4v1ud (2) command packet nbd bus line ad3_dbg ad2_dbg ad1_dbg ad0_dbg 1st aux3 aux2 aux1 aux0 2nd siz1 siz0 r/w i/t 3rd a3 a2 a1 a0 4th a7 a6 a5 a4 5th a11 a10 a9 a8 6th a15 a14 a13 a12 7th a19 a18 a17 a16 8th a23 a22 a21 a20 9th d3 d2 d1 d0 10th d7 d6 d5 d4 11th d11 d10 d9 d8 12th d15 d14 d13 d12 13th d19 d18 d17 d16 14th d23 d22 d21 d20 15th d27 d26 d25 d24 16th d31 d30 d29 d28 caution values are for co mmand packet maximum setup. ? access to nbd space address: 12 bits (a0 to a11) [fixed] data: 8 bits (d0 to d7) ? access to target space address: 24 bits (a0 to a23) [fixed] data: 32 bits (d0 to d31) (a) aux0 to aux3: expansion bits aux0 aux1 aux2 aux3 remarks 0 0 0 0 fixed other than 0000 for future expansion (b) i/t: access address spa ce mode specification i/t remarks 0 specifies access to nbd space 1 specifies access to target space (c) r/w: access mode specification from nbd tool r/w remarks 0 read mode from nbd tool 1 write mode from nbd tool chapter 12 nbd function ( pd70f3116) 622 user?s manual u14492ej4v1ud (d) siz0, siz1: access data size specification siz1 siz0 target space access nbd space access 0 0 8-bit length note 1 8-bit length 0 1 16-bit length note 1 1 0 32-bit length 1 1 setting prohibited note 2 setting prohibited note 2 notes 1. can be set only on a read. if set on a write, ram data will be destroyed. 2. a write is invalid and read data is undefin ed in cases where ?setting prohibited? is specified. (3) flag sense packet nbd bus line ad3_dbg ad2_dbg ad1_dbg ad0_dbg 1st 0 0 0 rflg rflg 0: not ready 1: ready (4) data packet the data packet data size is the data size specified by siz1 and siz0 in a command packet (8, 16, or 32 bits). nbd bus line ad3_dbg ad2_dbg ad1_dbg ad0_dbg 1st d3 d2 d1 d0 2nd d7 d6 d5 d4 3rd d11 d10 d9 d8 4th d15 d14 d13 d12 5th d19 d18 d17 d16 6th d23 d22 d21 d20 7th d27 d26 d25 d24 8th d31 d30 d29 d28 chapter 12 nbd function ( pd70f3116) 623 user?s manual u14492ej4v1ud 12.4 nbd function 12.4.1 ram monitoring, accessing nbd space the nbd function performs read and writ e operations on internal ram data via dma (direct memory access) for addresses in internal ram. it also performs reading or writing to nbd space. (1) ram monitoring the following are the commands for reading and writi ng to internal ram areas from the nbd tool. (a) write command the target address (real address of target: lower 24 bits ) at which a write to internal ram is to be made and the data are received from the nbd tool as a command packet. after receiving the command packet shown below from the nbd tool, a ready command is output following write termination. command packets can be received once more from the nbd tool (after ready command sync inactive confirmation). table 12-3. command packet (on a write) adn_dbg ad3_dbg ad2_dbg ad1_dbg ad0_dbg 1st 0 0 0 0 2nd siz1 siz0 1 1 3rd to 8th target space write address specification (24 bits) 9th to 16th write data (data specified by siz0 and siz1) (b) read command the target address (real address of target: lower 24 bits ) at which a read of internal ram is to be made is received from the nbd tool as a command packet. after receiving the command packet from the nbd tool, a ready command is output, sync is made inacti ve, and the data at the ad dress specified by the command packet is transmitted to the nbd tool. the address (a27 to a24) during read is ?1111?. table 12-4. command packet (on a read) adn_dbg ad3_dbg ad2_dbg ad1_dbg ad0_dbg 1st 0 0 0 0 2nd siz1 siz0 0 1 3rd to 8th target space read address specification (24 bits) caution in read mode, the output data section from the nbd tool is deleted. table 12-5. data packet (on a read) adn_dbg ad3_dbg ad2_dbg ad1_dbg ad0_dbg 1st to 8th target space read data chapter 12 nbd function ( pd70f3116) 624 user?s manual u14492ej4v1ud (2) access to nbd space the following are the commands for reading and writing nbd space from the nbd tool. for nbd space, an access address is 12-bit fixed-length and the access data is 8-bit fixed-length. (a) write command the address (nbd space address: 12 bits) at which a write to nbd space is to be made and the data are received from the nbd tool as a command packet. after receiving the command packet shown in table 12-6 from the nbd tool, a ready command is output following write termination. command packets can be received once more from the nbd tool (after ready command sync inactive confirmation). table 12-6. command packet (on a write to nbd space) adn_dbg ad3_dbg ad2_dbg ad1_dbg ad0_dbg 1st 0 0 0 0 2nd 0 0 1 0 3rd a3 a2 a1 a0 4th a7 a6 a5 a4 5th a11 a10 a9 a8 6th d3 d2 d1 d0 7th d7 d6 d5 d4 caution an nbd space write addres s is 12-bit fixed-length. the write data is 8-bit fixed-length. (b) read command the target address (real address of target: 12 bits) at which to read from internal ram is received as a command packet from the nbd tool. after receiving the command packet from the nbd tool, a ready command is output, sync is made inactive, and t he data at the address specified by the command packet is transmitted to the nbd tool. table 12-7. command packet (on a read of nbd space) adn_dbg ad3_dbg ad2_dbg ad1_dbg ad0_dbg 1st 0 0 0 0 2nd 0 0 0 0 3rd a3 a2 a1 a0 4th a7 a6 a5 a4 5th a11 a10 a9 a8 caution an nbd space read addr ess is 12-bit fixed-length. in read mode, the output data secti on from the nbd tool is deleted. chapter 12 nbd function ( pd70f3116) 625 user?s manual u14492ej4v1ud table 12-8. data packet adn_dbg ad3_dbg ad2_dbg ad1_dbg ad0_dbg 1st d3 d2 d1 d0 2nd d7 d6 d5 d4 caution read data is 8-bit fixed-length. 12.4.2 event detection function by having a comparator (24-bit address setting) for match det ection on-chip at a single point, this function detects match of the address setting registers shown below and output s a match trigger (falling edge) to the nbd tool. event trigger output is low active and during the active period it is output synchronous with t he system clock of the target cpu. the active width is one cycle of the internal system clock of the cpu. (1) event detection conditions ? execution pc address match match detection range for timing of a write to a set address in the internal ram area xfffc000h to xfffe7ffh (2) event detection function control register (a) nbd event condition setti ng register (evtu_c) 7 0 evtu_c7 to evtu_c0 6 0 5 0 4 0 3 0 2 0 1 0 0 pcu/dtu nbd space address 820h initial value undefined bit position bit name function 0 pcu/dtu selects an execution pc event or ram access event. 0: internal ram access event is in valid note 1: execution pc event is in valid note if the evtu_c register is set outside the internal ram area, an event also is output when writing outside the ram. chapter 12 nbd function ( pd70f3116) 626 user?s manual u14492ej4v1ud (b) nbd event address register (evtu_a) the evtu_a register sets the value of the address that is the subject of the event. 7 evau7 evtu_a7 to evtu_a0 6 evau6 5 evau5 4 evau4 3 evau3 2 evau2 1 evau1 0 evau0 nbd space address 800h initial value undefined 15 evau15 evtu_a15 to evtu_a8 14 evau14 13 evau13 12 evau12 11 evau11 10 evau10 9 evau9 8 evau8 nbd space address 801h initial value undefined 23 evau23 evtu_a23 to evtu_a16 22 evau22 21 evau21 20 evau20 19 evau19 18 evau18 17 evau17 16 evau16 nbd space address 802h initial value undefined 31 undefined evtu_a27 to evtu_a24 30 undefined 29 undefined 28 undefined 27 evau27 note 26 evau26 note 25 evau25 note 24 evau24 note nbd space address 803h initial value undefined note set bit 27 to bit 24 to 0. cautions 1. rom address match f unctions only for internal rom. 2. this cannot be used in single-chip mode 1. 3. the lower 2 bits (evau1, evau0) are masked. 12.4.3 chip id regi sters (tid0 to tid2) the chip id registers are stored in nbd spaces 000h to 0 02h. by reading the id codes in the chip id registers from the nbd tool in nbd mode, the semiconductor manufacturer, cpu code, and specific product type can be identified. the chip id registers have fixed values for each product. the chip id registers (tid0 to tid2) are read-only registers. 7 mc7 tid0 6 mc6 mc7 to mc0: semiconductor manufacturer classification code nec electronics: 4eh 5 mc5 4 mc4 3 mc3 2 mc2 1 mc1 0 mc0 nbd space address 000h 7 fc7 tid1 6 fc6 5 fc5 4 fc4 3 fc3 2 fc2 1 fc1 0 fc0 nbd space address 001h fc7 to fc0: cpu classification code v850e1 cpu: 01h sc7 to sc0: specific product classification code v850e/ia1: 01h 7 sc7 tid2 6 sc6 5 sc5 4 sc4 3 sc3 2 sc2 1 sc1 0 sc0 nbd space address 002h chapter 12 nbd function ( pd70f3116) 627 user?s manual u14492ej4v1ud 12.5 control registers (1) ram access data buffer register l (nbdl) nbdl register operates as buffer between dma and the nbd tool when reading or writing ram via dma from the nbd tool. nbdl register can be read/written in 16-bit units. when the higher 8 bits of the nbdl register are used as the nbdlu register, and the lower 8 bits are used as the nbdll register, they c an be read/written in 8-bit units. 14 d14 13 d13 12 d12 2 d2 3 d3 4 d4 5 d5 6 d6 7 d7 8 d8 9 d9 10 d10 11 d11 15 d15 1 d1 0 d0 nbdl address fffffa60h initial value 0000h cautions 1. although nbdl, nbdlu, and nbdll register s can be used to read or write, physically separate registers are used wh en reading and when writing and values written cannot be read. 2. use both nbdl and nbdh (refer to 12. 5 (2)) registers for 32-bit access of ram. remark register values written from the nbd tool can be read by dma (cpu) and values written by dma (cpu) can be read by the nbd tool. (2) ram access data buffer register h (nbdh) nbdh register operates as buffer between dma and the nbd tool when reading or writing ram via dma from the nbd tool. nbdh register can be read/written in 16-bit units. when the higher 8 bits of the nbdh r egister are used as the nbdhu regist er, and the lower 8 bits are used as the nbdhl register, they c an be read/written in 8-bit units. 14 d30 13 d29 12 d28 2 d18 3 d19 4 d20 5 d21 6 d22 7 d23 8 d24 9 d25 10 d26 11 d27 15 d31 1 d17 0 d16 nbdh address fffffa62h initial value 0000h cautions 1. although nbdh, nbdhu, and nbdhl register s can be used to read or write, physically separate registers are used wh en reading and when writing and values written cannot be read. 2. use both nbdl (refer to 12.5 (1)) and nbdh registers for 32-bit access of ram. remark register values written from the nbd tool can be read by dma (cpu) and values written by dma (cpu) can be read by the nbd tool. chapter 12 nbd function ( pd70f3116) 628 user?s manual u14492ej4v1ud (3) dma source address setting register sl (nbdmsl) nbdmsl register specifies a dma source address. it can be written from the nbd tool and read by dma (cpu). it can be read-only, in 16-bit units. 14 ad14 13 ad13 12 ad12 2 ad2 3 ad3 4 ad4 5 ad5 6 ad6 7 ad7 8 ad8 9 ad9 10 ad10 11 ad11 15 ad15 1 ad1 0 ad0 nbdmsl address fffffa64h initial value undefined remarks 1. when reading ram using the nbd tool, an address signal from the nbd tool can be read from the nbdmsl register by dma (cpu). 2. when writing ram using the nbd tool, the nbdl register value can be read from the nbdmsl register by dma (cpu). (4) dma source address setting register sh (nbdmsh) nbdmsh register specifies a dma source address. it can be written from the nbd tool and read by dma (cpu). it can be read-only, in 16-bit units. 14 0 13 0 12 0 2 ad18 3 ad19 4 ad20 5 ad21 6 ad22 7 ad23 8 ad24 9 ad25 10 ad26 11 ad27 15 ir 1 ad17 0 ad16 nbdmsh address fffffa66h initial value undefined bit position bit name function 15 ir shows read or write status when nbd acce sses internal ram of the v850e/ia1. 0: nbd is write accessing ram 1: nbd is read accessing ram remarks 1. when reading ram using the nbd tool, an address signal from the nbd tool can be read from the nbdmsh register by dma (cpu). 2. when writing ram using the nbd tool, the nbdl register value can be read from the nbdmsh register by dma (cpu). chapter 12 nbd function ( pd70f3116) 629 user?s manual u14492ej4v1ud (5) dma destination address se tting register dl (nbdmdl) nbdmdl register specifies a dma destination address. it can be written from the nbd tool and read by dma (cpu). it can be read-only, in 16-bit units. 14 ad14 13 ad13 12 ad12 2 ad2 3 ad3 4 ad4 5 ad5 6 ad6 7 ad7 8 ad8 9 ad9 10 ad10 11 ad11 15 ad15 1 ad1 0 ad0 nbdmdl address fffffa68h initial value undefined remarks 1. when writing ram using the nbd tool, an address signal from the nbd tool can be read from the nbdmdl register by dma (cpu). 2. when reading ram using the nbd tool, the nbdl register value can be read from the nbdmdl register by dma (cpu). (6) dma destination address setting register dh (nbdmdh) nbdmdh register specifies a dma destination address. it can be written from the nbd tool and read by dma (cpu). it can be read-only, in 16-bit units. 14 0 13 0 12 0 2 ad18 3 ad19 4 ad20 5 ad21 6 ad22 7 ad23 8 ad24 9 ad25 10 ad26 11 ad27 15 ir 1 ad17 0 ad16 nbdmdh address fffffa6ah initial value undefined bit position bit name function 15 ir shows read or write status when nbd acce sses internal ram of the v850e/ia1. 0: nbd is read accessing ram 1: nbd is write accessing ram remarks 1. when writing ram using the nbd tool, an address signal from the nbd tool can be read from the nbdmdh register by dma (cpu). 2. when reading ram using the nbd tool, the nbdl register value can be read from the nbdmdh register by dma (cpu). chapter 12 nbd function ( pd70f3116) 630 user?s manual u14492ej4v1ud 12.6 restrictions on nbd 12.6.1 general restrictions (1) clk_dbg operates at less than half t he speed of the internal system clock (f xx ) and is 12.5 mhz maximum. (2) if a command packet is sent during a reset period, ?ready? is not returned afterwards. reset again. 12.6.2 restrictions related to read or write of ram by nbd (1) initialize dma in user software. (2) writes to ram are 32-bit fixed-length only. on a read-only, ram can be accessed in 32-, 16-, or 8-bit units. on a read/write, ram can be accessed in 32-bit units. (3) nbd does not function from during a reset un til dma initialization a fter the reset finishes. if a read or write of ram is performed in this interval , nbd does not return ?ready? afterwards. reset again. 12.6.3 restrictions related to nbd event trigger function (1) if a rom execution address event trigger is set to the address after a branch instruction, an event is generated due to pipeline processing even if it is not ex ecuted. the trigger must be set to an address at least 32 bits 3 words after a branch instruction. (2) since an event trigger is cleared by a reset, it must be set again after a reset. (3) unless there is a rom fetch, a trigger occurs even on a read. (4) rom address match functions only for inter nal rom. the lower 2 bits are masked. ram address match functions only for internal ram. the lower 2 bits are masked. caution rom and ram address match cannot be used in the in-circuit emulator. 12.6.4 how to detect termination of dma initialization via nbd tool set an event trigger using a ram write and send a write co mmand from nbd to the relevant address. if an event trigger occurs at this time, dm a initialization has terminated. chapter 12 nbd function ( pd70f3116) 631 user?s manual u14492ej4v1ud 12.7 initialization required for dma (2 channels) (1) the dma initialization in a setting change re quest must be performed by user software. (2) assign dma two channels in nbd. at this time, assign an nbdad in terrupt to a higher priority channel than an nbdrew interrupt. (3) initialize registers of the channel to which the nbdad interrupt is assigned. set contents so that the contents of nbdmsl/ndbmsh and nbdmdl/nbdmdh (read-only sfr) transfer to dma source address registers nl and nh (dsanl, dsanh) note and dma destination address registers nl and nh (ddanl, ddanh) note of the dma channel assigned to the nbdrew interrupt in 16 bits 4 blocks (n = 0 to 3). note dma registers are 16-bit access only. (4) set dma addressing control register n (dadcn) of the dma channel assigned to the nbdrew interrupt for 32-bit transfer (bit transfer settings of 8 bits 4, 16 bits 2, and 32 bits 1 note ) (n = 0 to 3). in addition, set the counter direction of the dma tr ansfer source address and dma transfer destination address to increment mode (sadm bit of dadcn register = 0, dadm bit = 0 (m = 0,1)) (since dma judges data transfer terminated on reading or writing the uppermost 8 bits). note bits that can be manipulated on 8 bits 4, 16 bits 2, and 32 bits 1 bit transfer are shown below. 8 bits 4: 32-, 16-, or 8-bit read is possible. 16 bits 2: 16- or 8-bit read is possible. 32 bits 1: 32-bit read is possible. this is the highest read speed. settings other than the above are prohibited. moreover, make the setting 32 bits 1 when reading or writing ram. caution in dma initialization, set the dma request selection last. chapter 12 nbd function ( pd70f3116) 632 user?s manual u14492ej4v1ud examples of dma initialization on 32-bit transfer , 16-bit transfer, and 8-bit transfer are shown below. (a) example of 32-bit transfer dma initialization -- dma initial -? mov 0x0000fa64 , r24 -- dmach0 source address ?- st.h r24 , dsal0[r0] mov 0x00000fff , r24 ?- dmach0 source address ?- st.h r24 , dsah0[r0] mov 0x0000f088 , r24 ?- dmach0 destination address ?- st.h r24 , ddal0[r0] mov 0x00000fff , r24 ?- dmach0 destination address ?- st.h r24 , ddah0[r0] mov 0x0000400c , r24 -? dmach0 block mode 16bit mode ?- st.h r24 , dadc0[r0] mov 0x0000800c , r24 -? dmach1 block mode 32bit mode ?- st.h r24 , dadc1[r0] mov 0x00000003 , r24 -? dmach0 block mode 16bit ? 4 -- st.h r24 , dbc0[r0] mov 0x00000000 , r24 -? dmach1 block mode 32bit ? 1 -- st.h r24 , dbc1[r0] mov 0x00000009 , r24 -? dmach0&1 dma ready -- st.b r24 , dchc0[r0] st.b r24 , dchc1[r0] mov 0x00000035 , r24 -? dmach0 trigger ?- st.b r24 , dtfr0[r0] mov 0x00000036 , r24 -? dmach1 trigger ?- st.b r24 , dtfr1[r0] chapter 12 nbd function ( pd70f3116) 633 user?s manual u14492ej4v1ud (b) example of 16-bit transfer dma initialization -- dma initial -? mov 0x0000fa64 , r24 -- dmach0 source address ?- st.h r24 , dsal0[r0] mov 0x00000fff , r24 ?- dmach0 source address ?- st.h r24 , dsah0[r0] mov 0x0000f088 , r24 ?- dmach0 destination address ?- st.h r24 , ddal0[r0] mov 0x00000fff , r24 ?- dmach0 destination address ?- st.h r24 , ddah0[r0] mov 0x0000400c , r24 -? dmach0 block mode 16bit mode ?- st.h r24 , dadc0[r0] mov 0x0000400c , r24 -? dmach1 block mode 16bit mode ? st.h r24 , dadc1[r0] mov 0x00000003 , r24 -? dmach0 block mode 16bit ? 4 -- st.h r24 , dbc0[r0] mov 0x00000001 , r24 -? dmach1 block mode 16bit ? 2 -- st.h r24 , dbc1[r0] mov 0x00000009 , r24 -? dmach0&1 dma ready -- st.b r24 , dchc0[r0] st.b r24 , dchc1[r0] mov 0x00000035 , r24 -? dmach0 trigger ?- st.b r24 , dtfr0[r0] mov 0x00000036 , r24 -? dmach1 trigger ?- st.b r24 , dtfr1[r0] chapter 12 nbd function ( pd70f3116) 634 user?s manual u14492ej4v1ud (c) example of 8-bit transfer dma initialization -- dma initial -? mov 0x0000fa64 , r24 -- dmach0 source address ?- st.h r24 , dsal0[r0] mov 0x00000fff , r24 ?- dmach0 source address ?- st.h r24 , dsah0[r0] mov 0x0000f088 , r24 ?- dmach0 destination address ?- st.h r24 , ddal0[r0] mov 0x00000fff , r24 ?- dmach0 destination address ?- st.h r24 , ddah0[r0] mov 0x0000400c , r24 -? dmach0 block mode 16bit mode ?- st.h r24 , dadc0[r0] mov 0x0000000c , r24 -? dmach1 block mode 8bit mode ? st.h r24 , dadc1[r0] mov 0x00000003 , r24 -? dmach0 block mode 16bit ? 4 -- st.h r24 , dbc0[r0] mov 0x00000003 , r24 -? dmach1 block mode 8bit ? 4 -- st.h r24 , dbc1[r0] mov 0x00000009 , r24 -? dmach0&1 dma ready -- st.b r24 , dchc0[r0] st.b r24 , dchc1[r0] mov 0x00000035 , r24 -? dmach0 trigger ?- st.b r24 , dtfr0[r0] mov 0x00000036 , r24 -? dmach1 trigger ?- st.b r24 , dtfr1[r0] 635 user?s manual u14492ej4v1ud chapter 13 a/d converter 13.1 features two 10-bit resolution on-chip a/d converters (a/d converter 0 and 1) simultaneous sampling by two circuits is possible. analog input: 8 channels per circuit on-chip a/d conversion result registers 0n, 1n (adcr0n, adcr1n) 10 bits 8 registers 2 a/d conversion trigger mode a/d trigger mode a/d trigger polling mode timer trigger mode external trigger mode successive approximation technique voltage detection mode remark n = 0 to 7 13.2 configuration a/d converters 0 and 1, which employ a successive a pproximation technique, perfo rm a/d conversion operation using a/d scan mode registers 00, 01, 10, and 11 (adscm00, adscm01, adscm10, and adscm11) and registers adcr0n and adcr1n (n = 0 to 7). (1) input circuit the input circuit selects an analog input (ani0n or an i1n) according to the mode set in the adscm00 or adscm10 register and sends it to the sample and hold circuit (n = 0 to 7). (2) sample and hold circuit the sample and hold circuit individually samples anal og inputs sent sequentially fr om the input circuit and sends them to the comparator. it holds sampled analog inputs during a/d conversion. (3) voltage comparator the voltage comparator compares t he analog input voltage that was i nput with the output voltage of the d/a converter. (4) d/a converter the d/a converter is used to generate a voltage that matches an analog input. the output voltage of the d/ a converter is controlled by the succe ssive approximation register (sar). (5) successive approximation register (sar) the sar is a 10-bit register that controls the output value of the d/a converter for comparing with an analog input voltage value. when an a/d conversion terminate s, the current contents of the sar (conversion result) are stored in an a/d conversion resu lt register (adcr0n, adcr1n) (n = 0 to 7). when all specified a/d conversions terminate, there also is an a/d conv ersion termination interrupt (intad0, intad1). chapter 13 a/d converter 636 user?s manual u14492ej4v1ud (6) a/d conversion result regi sters 0n, 1n (adcr0n, adcr1n) adcr0n and adcr1n are 10-bit registers that hold a/d conversion results (n = 0 to 7). whenever an a/d conversion terminates, the conversion result from t he successive approximation register (sar) is loaded. reset input sets these registers to 0000h. (7) controller the controller selects an analog input, generates samp le and hold circuit operation timing, controls conversion triggers, and specifies t he conversion operation time according to the mode set in the adscmn0 or adscmn1 register (n = 0, 1). (8) ani0n, ani1n pins (n = 0 to 7) the ani0n and ani1n pins are the 8-channel (total of 16 channels for two circuits) analog input pins to a/d converters 0 and 1. they input analog signals to be a/d converted. caution use input voltages to ani0n and ani1n th at are within the range of the ratings. in particular, if a voltage (including noise) higher than av dd or lower than av ss (even one within the range of absolute maximum ratings ) is input, the conversion value of that channel is invalid, and the c onversion values of other channels also may be affected. (9) av ref0 , av ref1 pins the av ref0 and av ref1 pins are used to input reference voltages to a/d converters 0 and 1. a signal input to the ani0n or ani1n pin is converted to a digita l signal based on the voltage applied between av ref0 and av ss or between av ref1 and av ss (n = 0 to 7). caution if not using the av ref0 or av ref1 pin, connect it to v ss5 . (10) av ss pin the av ss pin is the ground voltage pin of a/d converters 0 and 1. even if not using a/d converters 0 and 1, always make this pin have the same potential as the v ss5 pin. (11) av dd pin the av dd pin is the analog power supply pin of a/d conver ters 0 and 1. even if not using a/d converters 0 and 1, always make this pin have the same potential as the v dd5 pin. chapter 13 a/d converter 637 user?s manual u14492ej4v1ud figure 13-1. block diagram of a/d converter 0 or 1 adscmn0 (16) 15 0 adtrgn intadn sample and hold circuit anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 itrg0 16 16 16 16 adscmn1 (16) 15 0 adetm0 (16) 15 0 adetm1 (16) 15 0 90 trigger source switching circuit in timer trigger mode ( figure 13-2 ) controller 10 10 sar (10) comparator and d/a converter av dd av refn av ss intdetn adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn7 internal bus input circuit f xx /2 remark n = 0, 1 f xx : internal system clock cautions 1. noise at an analog input pin (ani 0n, ani1n) or reference voltage input pin (av ref0 , av ref1 ) may give rise to an invalid conversion result. software processing is needed in order to prevent this invalid conversion result from adversely affecting the system. the following are exam ples of software processing. ? use the average value of the results of multiple a/d conversions as the a/d conversion result. perform a/d conversion multiple consecu tive times and use conversion results with the exception of any abnormal conversi on results that are obtained. if an a/d conversion result from which it is judged that an abnormality occurred in the system is obtained, do not perform abnorma lity processing at once but perform it upon reconfirming the occurrenc e of an abnormality. 2. be sure that voltages outside the range [av ss to av ref0 , av ss to av ref1 ] are not applied to pins being used as a/d converter 0 and 1 input pins. chapter 13 a/d converter 638 user?s manual u14492ej4v1ud figure 13-2. block diagram of trigger sour ce switching circuit in timer trigger mode itrg0 a/d converter 0 adtrg0 intcm003 intcm013 itrg0 a/d converter 1 adtrg1 inttm00 inttm01 0 itrg0 itrg22 itrg21 itrg20 0 itrg12 itrg11 itrg10 internal bus selector selector selector selector caution for the selection of the tri gger source in timer tr igger mode, refer to 13. 3 (5) a/d internal trigger selection register (itrg0). chapter 13 a/d converter 639 user?s manual u14492ej4v1ud 13.3 control registers (1) a/d scan mode registers 00 and 10 (adscm00, adscm10) the adscmn0 registers are 16-bit registers that select analog input pins, specify operation modes, and control conversion operation. the adscmn0 register can be read/written in 16-bit units. when the higher 8 bits of the adscmn0 register are us ed as the adscmn0h register, and the lower 8 bits are used as the adscmn0l register, they can be read/written in 8-bit or 1-bit units. however, writing to an adscmn0 regi ster during a/d conversion operat ion initializes conversion operation and starts the conversion over from the beginning. at this time, overwrite the adscmn0 register with the same value. if writing a different value, be sure to clear the adcen bit to 0 first before overwriting. caution before changing the trigge r mode by using the adplmn and trg2 to trg0 bits, clear the adcen bit to 0 (n = 0 or 1). the operation is not guaranteed if the tr igger mode is changed and the adcen bit is cleared at the same time (by the same instruction). be sure to access the register twice. chapter 13 a/d converter 640 user?s manual u14492ej4v1ud (1/2) <14> adcs0 13 0 <12> adms0 2 anis2 3 anis3 4 sani0 5 sani1 6 sani2 7 sani3 8 trg0 9 trg1 10 trg2 <11> adplm0 <15> adce0 1 anis1 0 anis0 <14> adcs1 13 0 <12> adms1 2 anis2 3 anis3 4 sani0 5 sani1 6 sani2 7 sani3 8 trg0 9 trg1 10 trg2 <11> adplm1 <15> adce1 1 anis1 0 anis0 adscm00 address fffff200h initial value 0000h adscm10 address fffff240h initial value 0000h bit position bit name function 15 adcen specifies enabling or disabling a/d conversion. 0: disable 1: enable 14 adcsn shows status of a/d converte r 0 or 1. this bit is read-only. 0: stopped 1: operating the adcsn bit is ?0? for the duration of 6 f xx /2 immediately after the start of a/d conversion, and is then set to ?1?. in the scan mode, this operation is performed each time the analog input pin to be a/d converted is switched. 12 admsn specifies operation mode of a/d converter 0 or 1. 0: scan mode 1: select mode adplmn: specifies polling mode. trg2 to trg0: specifies trigger mode. adplmn trg2 trg1 trg0 trigger mode 0 0 0 0 a/d trigger mode 0 0 0 1 timer trigger mode 0 1 1 1 external trigger mode 1 0 0 0 a/d trigger polling mode other than above setting prohibited 11 to 8 adplmn, trg2 to trg0 remark n = 0, 1 chapter 13 a/d converter 641 user?s manual u14492ej4v1ud (2/2) bit position bit name function specifies conversion start anal og input pin in scan mode. these bits are ignored in select mode. sani3 sani2 sani1 sani0 scan start analog input pin 0 0 0 0 anin0 0 0 0 1 anin1 0 0 1 0 anin2 0 0 1 1 anin3 0 1 0 0 anin4 0 1 0 1 anin5 0 1 1 0 anin6 0 1 1 1 anin7 other than above setting prohibited caution always set the conversion st art analog input pin number that is set by bits sani3 to sani0 to a smaller pin number than the conversion termination analog input pin number that is set by bits anis3 to anis0. 7 to 4 sani3 to sani0 specifies analog input pin in select mode. in scan mode, specifies conversi on termination analog input pin. anis3 anis2 anis1 anis0 in select mode in scan mode 0 0 0 0 anin0 anin0 0 0 0 1 anin1 sani anin1 0 0 1 0 anin2 sani anin2 0 0 1 1 anin3 sani anin3 0 1 0 0 anin4 sani anin4 0 1 0 1 anin5 sani anin5 0 1 1 0 anin6 sani anin6 0 1 1 1 anin7 sani anin7 other than above setting prohibited remark sani < aninm m = 1 to 7 3 to 0 anis3 to anis0 remark n = 0, 1 chapter 13 a/d converter 642 user?s manual u14492ej4v1ud (2) a/d scan mode registers 01 and 11 (adscm01, adscm11) the adscmn1 registers are 16-bit registers that set the conversi on time of the a/d converter. the adscmn1 register can be read/written in 16-bit units. when the higher 8 bits of the adscmn1 register are us ed as the adscmn1h register, and the lower 8 bits are used as the adscmn1l register, the adscmn1h register can be read/written in 8-bit or 1-bit units, and the adscmn1l register is read-only, in 8-bit units. caution do not write to the adscmn1 registers during a/d conversion operation. if a write is performed, conversion operation is susp ended and subsequently terminates. 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 fr0 9 fr1 10 fr2 11 0 15 0 1 0 0 0 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 fr0 9 fr1 10 fr2 11 0 15 0 1 0 0 0 adscm01 address fffff202h initial value 0000h adscm11 address fffff242h initial value 0000h bit position bit name function specifies conversion time. conversion time ( s) note fr2 fr1 fr0 conversion clocks f xx = 50 mhz f xx = 40 mhz f xx = 33 mhz 0 0 0 344 6.88 8.60 ? 0 0 1 248 ? 6.20 7.51 0 1 0 176 ? ? 5.33 0 1 1 128 ? ? ? 1 0 0 104 ? ? ? 1 0 1 80 ? ? ? 1 1 0 56 ? ? ? 1 1 1 setting prohibited ? ? ? 10 to 8 fr2 to fr0 note this is the time from sampli ng until conversion termination. sampling time = (conversion clocks ? 8)/6 f xx caution be sure to secure the conversion time within a range of 5 to 10 s. conversion time = f xx conversion clocks remark f xx : internal system clock chapter 13 a/d converter 643 user?s manual u14492ej4v1ud (3) a/d voltage detection mode re gisters 0 and 1 (adetm0, adetm1) the adetmn registers are 16-bit r egisters that set voltage detection m ode. in voltage detection mode, the analog input pin for which voltage detection is being performed and a reference voltage value are compared and an interrupt is set in respon se to the comparison result. the adetmn register can be r ead/written in 16-bit units. when the higher 8 bits of the adetmn register are used as the adetmnh register, and the lower 8 bits are used as the adetmnl register, they can be read/written in 8-bit or 1-bit units. caution do not write to an adetmn register dur ing a/d conversion operation. if a write is performed, conversion is suspended and it subsequently terminates. address fffff204h initial value 0000h <14> adet lh0 13 det ani3 12 det ani2 2 det cmp2 3 det cmp3 4 det cmp4 5 det cmp5 6 det cmp6 7 det cmp7 8 det cmp8 9 det cmp9 10 det ani0 11 det ani1 <15> adet en0 1 det cmp1 0 det cmp0 adetm0 address fffff244h initial value 0000h <14> adet lh1 13 det ani3 12 det ani2 2 det cmp2 3 det cmp3 4 det cmp4 5 det cmp5 6 det cmp6 7 det cmp7 8 det cmp8 9 det cmp9 10 det ani0 11 det ani1 <15> adet en1 1 det cmp1 0 det cmp0 adetm1 bit position bit name function 15 adetenn specifies voltage detection mode. 0: operate in normal mode 1: operate in voltage detection mode 14 adetlhn sets voltage comparison detection. 0: generate intdetn interrupt if reference voltage value > analog input pin voltage. 1: generate intdetn interrupt if reference voltage value analog input pin voltage. selects analog input pin to compare to reference voltage value set by detcmp9 to detcmp0 when in voltage detection mode. detani3 detani2 detani1 detani0 voltage detection analog input pin 0 0 0 0 anin0 0 0 0 1 anin1 0 0 1 0 anin2 0 0 1 1 anin3 0 1 0 0 anin4 0 1 0 1 anin5 0 1 1 0 anin6 0 1 1 1 anin7 1 setting prohibited 13 to 10 detani3 to detani0 remark : arbitrary 9 to 0 detcmp9 to detcmp0 sets reference voltage value to compare with analog input pin selected in detani3 to detani0. remark n = 0, 1 chapter 13 a/d converter 644 user?s manual u14492ej4v1ud (4) a/d conversion result registers 00 to 07 and 10 to 17 (adcr00 to adcr07, adcr10 to adcr17) the adcr0n and adcr1n registers are 10-bit registers that hold the results of a/d conversions (n = 0 to 7). one a/d converter is equipped with eight 10-bit register s for 8 channels, and a/d converters 0 and 1 together have sixteen 10-bit registers. these registers are read-only, in 16-bit units. when reading 10 bits of data of an a/d conversion result from an adcr0n or adcr1n register, only the lower 10 bits are valid and the higher 6 bits are always read as 0. 14 0 13 0 12 0 2 adcrn2 3 adcrn3 4 adcrn4 5 adcrn5 6 adcrn6 7 adcrn7 8 adcrn8 9 adcrn9 10 0 11 0 15 0 1 adcrn1 0 adcrn0 adcr0n address see table 13-1 initial value 0000h adcr1n address see table 13-2 initial value 0000h 14 0 13 0 12 0 2 adcrn2 3 adcrn3 4 adcrn4 5 adcrn5 6 adcrn6 7 adcrn7 8 adcrn8 9 adcrn9 10 0 11 0 15 0 1 adcrn1 0 adcrn0 table 13-1. correspondence be tween adcr0n (n = 0 to 7) register names and addresses register name address adcr00 fffff210h adcr01 fffff212h adcr02 fffff214h adcr03 fffff216h adcr04 fffff218h adcr05 fffff21ah adcr06 fffff21ch adcr07 fffff21eh table 13-2. correspondence be tween adcr1n (n = 0 to 7) register names and addresses register name address adcr10 fffff250h adcr11 fffff252h adcr12 fffff254h adcr13 fffff256h adcr14 fffff258h adcr15 fffff25ah adcr16 fffff25ch adcr17 fffff25eh chapter 13 a/d converter 645 user?s manual u14492ej4v1ud the correspondence between each analog input pin a nd the adcr0n and adcr1n registers is shown below. table 13-3. correspondence be tween each analog input pin and adcr0n and adcr1n registers a/d converter analog input pin a/d conversion result register ani00 adcr00 ani01 adcr01 ani02 adcr02 ani03 adcr03 ani04 adcr04 ani05 adcr05 ani06 adcr06 a/d converter 0 ani07 adcr07 ani10 adcr10 ani11 adcr11 ani12 adcr12 ani13 adcr13 ani14 adcr14 ani15 adcr15 ani16 adcr16 a/d converter 1 ani17 adcr17 chapter 13 a/d converter 646 user?s manual u14492ej4v1ud the relationship between the analog voltage input to an anal og input pin (ani0n or ani1n) and the value of the a/d conversion result register (adcr0n or adcr1n) is as follows (n = 0 to 7): v in adcr = int ( 1,024 + 0.5) av ref or, av ref av ref (adcr ? 0.5) v in < (adcr + 0.5) 1,024 1,024 int ( ): function that returns integer of value in ( ) v in : analog input voltage av ref : av ref0 or av ref1 pin voltage adcr: value of a/d conversion result register (adcr0n or adcr1n) figure 13-3 illustrates the relationship between the analog input voltages and a/d conversion results. figure 13-3. relationship between analog input voltages and a/d conversion results 1023 1022 1021 3 2 1 0 input voltage/av refm 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 a/d conversion result (adcrn) remark m = 0, 1 n = 00 to 07, 10 to 17 chapter 13 a/d converter 647 user?s manual u14492ej4v1ud (5) a/d internal trigger selection register (itrg0) the itrg0 register is the r egister that switches the tr igger source in timer trigger mode. the timer trigger source of a/d converters 0 and 1 c an be set using the itrg0 register. this register can be read/written in 8-bit or 1-bit units. 7 0 itrg0 6 itrg22 5 itrg21 4 itrg20 3 0 2 itrg12 1 itrg11 0 itrg10 address fffff280h initial value 00h bit position bit name function sets timer trigger source of a/d converter 1. itrg22 itrg21 itrg20 itrg10 trigger source 0 0 0 select intcm003 0 0 1 select intcm013 0 1 0 select inttm00 0 1 1 select inttm01 1 0 0 select intcm003 and inttm00 1 0 1 select intcm013 and inttm00 1 1 0 select intcm003 and inttm01 1 1 1 select intcm013 and inttm01 6 to 4 itrg22 to itrg20 remark : arbitrary specifies timer trigger sour ce of a/d converter 0. itrg12 itrg11 itrg20 itrg10 trigger source 0 0 0 select intcm003 0 0 1 select intcm013 0 1 0 select inttm00 0 1 1 select inttm01 1 0 0 select intcm003 and inttm00 1 0 1 select intcm013 and inttm00 1 1 0 select intcm003 and inttm01 1 1 1 select intcm013 and inttm01 2 to 0 itrg12 to itrg10 remark : arbitrary chapter 13 a/d converter 648 user?s manual u14492ej4v1ud 13.4 interrupt requests a/d converters 0 and 1 generate two kinds of interrupts. a/d conversion termination interrupts (intad0, intad1) voltage detection interrupts (intdet0, intdet1) (1) a/d conversion terminati on interrupts (intad0, intad1) in a/d conversion enabled status, an a/d conversion te rmination interrupt is generated when a specified number of a/d conversions have terminated. a/d converter a/d conversion termination interrupt signal 0 generate intad0 1 generate intad1 (2) voltage detection interrupts (intdet0, intdet1) in voltage detection mode (adeten0 or adeten1 bi t of adetm0 or adetm1 = 1), the value of the adcr0n or adcr1n register of the relevant analog input pin is compared to the reference voltage set in the detcmp9 to detcmp0 bits of the adetm0 or adetm1 register and a voltage detection interrupt is generated in response to the value of the adetlh0 or adetlh1 bit of t he adetm0 or adetm1 register (n = 0 to 7). a/d converter voltage detection interrupt signal 0 generate intdet0 1 generate intdet1 chapter 13 a/d converter 649 user?s manual u14492ej4v1ud 13.5 a/d converter operation 13.5.1 a/d converter basic operation a/d conversion is performed us ing the following procedure. (1) set the analog input selection and the operation mode and trigger mode specifications using the adscm00 or adscm10 register note 1 . setting (1) the adce0 or adce1 bit of the adscm00 or adscm10 register when in a/d trigger mode or a/d trigger polling mode starts a/d conversion. in timer trigger mode or external trigger mode, the status becomes trigger standby note 2 . (2) when a/d conversion starts, compare the analog input to the voltage generated by the d/a converter. (3) when 10-bit comparison terminates, store the conver sion result in the adcr0n or adcr1n register. when the specified number of a/d conversions have terminated, generate an a/d conversion termination interrupt (intad0, intad1) (n = 0 to 7). notes 1. if the adscm00 or adscm10 register is overwri tten with the same value during a/d conversion, the a/d conversion operation preceding the overwrite stops and the conver sion result is not stored in the adcr0n or adcr1n register. the conversion operati on is initialized and conversion starts from the beginning. 2. in timer trigger mode or external trigger mode, ther e is a transition to trigger standby status when the adce0 or adce1 bit of the adscm00 or adscm10 regi ster is set to 1. a/d conversion operation is activated by a trigger signal and there is a return to trigger standby status when a/d conversion operation terminates. the timer trigger is selected by the itrg0 register. chapter 13 a/d converter 650 user?s manual u14492ej4v1ud 13.5.2 operation modes and trigger modes diverse conversion operations can be specified for a/d co nverters 0 and 1 by specifying operation modes and trigger modes. operation modes and trigger modes are set using the adscm00 or adscm10 register. the relationship between operation modes and trigger modes is shown below. setting trigger mode operation mode adscm00 adscm10 select xx010000xxxxxxxxb xx010000xxxxxxxxb ad trigger scan xx000000xxxxxxxxb xx000000xxxxxxxxb select xx011000xxxxxxxxb xx011000xxxxxxxxb ad trigger polling scan xx001000xxxxxxxxb xx001000xxxxxxxxb select xx010001xxxxxxxxb xx010001xxxxxxxxb timer trigger scan xx000001xxxxxxxxb xx000001xxxxxxxxb select xx010111xxxxxxxxb xx010111xxxxxxxxb external trigger scan xx000111xxxxxxxxb xx000111xxxxxxxxb (1) trigger modes the four trigger modes that serve as the start timing of a/d conversion processing are available: a/d trigger mode, a/d trigger polling mode, timer tr igger mode, and external trigger mode. these trigger modes are set using the adscm00 and adscm10 registers. (a) a/d trigger mode a/d trigger mode, which starts the conversion timing of the analog input set for the ani0n or ani1n pin (n = 0 to 7), is a mode that starts a/d conversion by setting the adce0 or adce1 bit of the adscm00 or adscm10 register to 1. in this mode, it is neces sary to set the adce0 or adce1 bit to 1 as an a/d conversion restart operation after an intad0 or intad1 interrupt (adcs0 or adcs1 = 0). (b) a/d trigger polling mode a/d trigger polling mode, which st arts the conversion timing of the analog input set for the ani0n or ani1n pin (n = 0 to 7), is a mode that starts a/d conversion by setting the adce0 or adce1 bit of the adscm00 or adscm10 register to 1. in this mode, it is not necessary to set the adce0 or adce1 bit to 1 as an a/d conversion restart operation after an inta d0 or intad1 interrupt (adcs0 or adcs1 = 1). the specified analog input is converted serially until the adce0 or adce1 bit is set to 0. an intad0 or intad1 interrupt occurs each time a conversion terminates. (c) timer trigger mode timer trigger mode, which starts the conversion timing of the analog input set for the ani0n or ani1n pin (n = 0 to 7), is a mode governed by a trigger specif ied in the a/d internal trigger selection register 0 (itrg0). (d) external trigger mode external trigger mode, which starts the conversion ti ming of the analog input set for the ani0n or ani1n pin, is a mode specified using the adtrg0 or adtrg1 pin. chapter 13 a/d converter 651 user?s manual u14492ej4v1ud (2) operation modes the two operation modes, which are the modes that se t the ani00 to ani07 and ani10 to ani17 pins, are select mode and scan mode. these modes are set using the adscm00 and adscm10 registers. (a) select mode select mode a/d converts one analog input specifie d in the adscm00 or adscm10 register. it stores the conversion result in the adcr0n or adcr1n regist er corresponding to the analog input (ani1n or ani0n) (n = 0 to 7). figure 13-4. example of select mode op eration timing (ani01): for a/d converter 0 ani01 (input) a/d conversion data 1 (ani01) data 2 (ani01) data 3 (ani01) data 4 (ani01) data 5 (ani01) data 6 (ani01) data 7 (ani01) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 (ani01) data 2 (ani01) data 3 (ani01) data 4 (ani01) data 6 (ani01) adcr01 register intad0 interrupt conversion start (adscm0 register setting) adce0 bit set adce0 bit set adce0 bit set adce0 bit set adce0 bit set conversion start (adscm0 register setting) ani00 ani01 ani02 ani03 ani04 ani05 ani06 ani07 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr06 adcr07 ad converter 0 adcr0n register analog input chapter 13 a/d converter 652 user?s manual u14492ej4v1ud (b) scan mode scan mode sequentially selects and a/d converts pins from the a/d conversion start analog input pin through the a/d conversion termination analog input pin specified in the adscm00 or adscm10 register. it stores the a/d conversion result in t he adcr0n or adcr1n register corresponding to the analog input (n = 0 to 7). when the specified anal og input conversion terminates, there is an a/d conversion termination interrupt (intad0 or intad1). figure 13-5. example of scan mode operation timing: for a/d converter 0 (4-channel scan (ani00 to ani03)) ani00 (input) ani01 (input) ani02 (input) ani03 (input) a/d conversion data 1 (ani00) data 2 (ani01) data 3 (ani02) data 4 (ani03) data 5 (ani00) data 6 (ani01) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani00) adcr00 data 2 (ani01) adcr01 data 3 (ani02) adcr02 data 4 (ani03) adcr03 data 5 (ani00) adcr00 adcr0n register intad0 interrupt conversion start (adscm00 register setting) conversion start (adscm00 register setting) ani00 ani01 ani02 ani03 ani04 ani05 ani06 ani07 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr06 adcr07 a/d converter 0 adcr0n register analog input chapter 13 a/d converter 653 user?s manual u14492ej4v1ud 13.6 operation in a/d trigger mode setting the adce0 or adce1 bit of the adscm00 or adscm10 register to 1 starts a/d conversion. 13.6.1 operation in select mode one analog input specified in the adsc m00 or adscm10 register is a/d conv erted at a time and the result is stored in an adcr0n or adcr1n register. analog inputs correspond one-to-one with adcr0n or adcr1n registers (n = 0 to 7). an a/d conversion termination interrupt (intad0, intad1 ) is generated for each a/d conversion termination, which terminates a/d conversion (adcs0 or adcs1 bit = 0). analog input a/d conversion result register anix adcrx remark x = 00 to 07, 10 to 17 to restart a/d conversion, write 1 in the adce0 or adce1 bit of the adscm00 or adscm10 register. this is optimal for an application that reads a result for each a/d conversion. figure 13-6. example of select mode (a/d tri gger select) operation (ani02): for a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 ani06 ani07 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr06 adcr07 a/d converter 0 adscm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) a/d conversion of ani02 (3) store conversion result in adcr02 (4) generate intad0 interrupt chapter 13 a/d converter 654 user?s manual u14492ej4v1ud 13.6.2 operation in scan mode pins from the conversion start analog input pin through the conversion termination analog input pin specified in the adscm00 or adscm10 register are sequentially selected and a/d converted. an a/d conv ersion result is stored in the adcr0n or adcr1n register corresponding to the analog input (n = 0 to 7). when conversion terminates for all analog inputs through the conversion termination analog input pin, an a/d conversion term ination interrupt (intad0, intad1) is generated, which terminates a/d conversion (adcs 0 or adcs1 bit of adscm0 or adscm1 register = 0). analog input a/d conversion result register anix note 1 adcrx | | anix note 2 adcrx notes 1. set using sani3 to sani0 bits of adscm00 or adscm10 register. be sure to set a pin number that is smaller than the conversion termination analog input pin number set according to note 2. 2. set using anis3 to anis0 bits of adscm00 or adscm10 register. remark x = 00 to 07, 10 to 17 to restart a/d conversion, write 1 in the adce0 or adce 1 bit of the adscm00 or adscm10 register. this is optimal for an application that regular ly monitors multiple analog inputs. figure 13-7. example of scan mode (a/d trigger scan) operation (ani02 to ani05): for a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 ani06 ani07 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr06 adcr07 a/d converter 0 adscm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) a/d conversion of ani02 (3) store conversion result in adcr02 (4) a/d conversion of ani03 (5) store conversion result in adcr03 (6) a/d conversion of ani04 (7) store conversion result in adcr04 (8) a/d conversion of ani05 (9) store conversion result in adcr05 (10) generate intad0 interrupt chapter 13 a/d converter 655 user?s manual u14492ej4v1ud 13.7 operation in a/d trigger polling mode setting the adce0 or adce1 bit of the adscm00 or adscm10 register to 1 starts a/d conversion. both select mode and scan mode are available in a/d trig ger polling mode. since the adcs0 or adcs1 bit of the adscm00 or adscm10 register remains 1 after an intad0 or intad1 interrupt in this mode, it is not necessary to write 1 in the adce0 or adce1 bit as an a/d conversion restart operation. 13.7.1 operation in select mode the analog input specified in the adscm00 or adscm10 re gister is a/d converted. the conversion result is stored in the adcr0n or adcr1n register (n = 0 to 7). one analog input is a/d conv erted at a time and the result is stored in one adcr0n or adcr1n register. analog inputs correspond one-to-one with adcr0n or adcr1n register. an a/d conversion termination interrupt (intad0 or inta d1) is generated for each a/d conversion termination. a/d conversion operation is repeated until the adce 0 or adce1 bit = 0 (adcs0 or adcs1 bit = 1). analog input a/d conversion result register anix adcrx remark x = 00 to 07, 10 to 17 in a/d trigger polling mode, it is not necessary to wr ite 1 in the adce0 or adce1 bit of the adscm00 or adscm10 register as an a/d conversion restart operation note . this is optimal for applications that regularly read a/d conversion values. note in a/d trigger polling mode, the fact that the adce 0 or adce1 bit of the adscm00 or adscm10 register is 0 means that a/d conversion operation does not stop as long as the adcs0 or adcs1 bit is not 0. therefore, if the adcr0n or adcr1n register is not read before the ne xt a/d conversion, it is overwritten. figure 13-8. example of select mode (a/d trigger polling select) operation (ani02): for a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 ani06 ani07 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr06 adcr07 a/d converter 0 adscm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) a/d conversion of ani02 (3) store conversion result in adcr02 (4) generate intad0 interrupt (5) return to (2) chapter 13 a/d converter 656 user?s manual u14492ej4v1ud 13.7.2 operation in scan mode pins from the conversion start analog input pin through the conversion termination analog input pin specified in the adscm00 or adscm10 register are sequentially selected and a/d converted. an a/d conv ersion result is stored in the adcr0n or adcr1n register corresponding to the analog input (n = 0 to 7). when conversion terminates for all analog inputs through the conversion termination analog input pin, an a/d conversion term ination interrupt (intad0, intad1) is generated. a/d conversion operation repeats un til the adce0 or adce1 bit = 0 (adcs0 or adcs1 bit = 1). analog input a/d conversion result register anix note 1 adcrx | | anix note 2 adcrx notes 1. set using sani3 to sani0 bits of adscm00 or adscm10 register. be sure to set a pin number that is smaller than the conversion termination analog input pin number set according to note 2. 2. set using anis3 to anis0 bits of adscm00 or adscm10 register. remark x = 00 to 07, 10 to 17 it is not necessary to write 1 in the adce0 or adce1 bit of the adscm00 or adscm10 register as an a/d conversion restart operation in a/d trigger polling mode note . this is optimal for applications that regularly read a/d conversion values. note in a/d trigger polling mode, the fact that the adce 0 or adce1 bit of the adscm00 or adscm10 register is 0 means that a/d conversion operation does not stop as long as the adcs0 or adcs1 bit is not 0. therefore, if the adcr0n or adcr1n register is not read before the ne xt a/d conversion, it is overwritten. figure 13-9. example of scan mode (a/d tr igger polling scan) oper ation (ani02 to ani05) : for a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 ani06 ani07 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr06 adcr07 a/d converter 0 adscm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) a/d conversion of ani02 (3) store conversion result in adcr02 (4) a/d conversion of ani03 (5) store conversion result in adcr03 (6) a/d conversion of ani04 (7) store conversion result in adcr04 (8) a/d conversion of ani05 (9) store conversion result in adcr05 (10) generate intad0 interrupt (11) return to (2) chapter 13 a/d converter 657 user?s manual u14492ej4v1ud 13.8 operation in timer trigger mode the a/d converter can set an interrupt si gnal specified by the a/d internal tri gger selection register 0 (itrg0) as a conversion trigger for up to 8 channels (a total of 16 channels in 2 circuits) of analog input (ani00 to ani07, ani10 to ani17). the four interrupt signals that can be selected as triggers are the tm0n timer 0 register underflow interrupt signals (inttm00 and inttm01) and the cm003 and cm013 match inte rrupt signals (intcm003 and intcm013) (n = 0, 1). 13.8.1 operation in select mode taking the interrupt signal specified by the a/d internal tr igger selection register 0 (itrg0) as a trigger, one analog input (ani00 to ani07, ani10 to ani17) specified by the adscm00 or adscm10 register is a/d converted once. the conversion result is stored in the adcr 0n or adcr1n register corresponding to the analog input (n = 0 to 7). an a/d conversion termination interrupt (intad0 or intad1) is generated for each a/d conversion, which terminates a/d conversion (adcs0 or adcs1 = 0). this is optimal for applications that read a/d c onversion values synchronized to a timer trigger. trigger analog input a/d conversion result register interrupt specified by itrg0 register anix adcrx remark x = 00 to 07, 10 to 17 after a/d conversion termination, a/d converter 0 or 1 cha nges to trigger wait status (adce0 or adce1 = 1). it performs a/d conversion operation again when the interr upt signal specified in the itrg0 register occurs. figure 13-10. example of timer trigger select mode operation (ani04): for a/d converter 0 (a) when selecting inttm00 by itrg0 register ani00 ani01 ani02 ani03 ani04 ani05 ani06 ani07 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr06 adcr07 a/d converter 0 inttm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) inttm00 interrupt generation (3) a/d conversion of ani04 (4) store conversion result in adcr04 (5) intad0 interrupt generation chapter 13 a/d converter 658 user?s manual u14492ej4v1ud 13.8.2 operation in scan mode using the interrupt signal specified by the a/d internal trigger selection register 0 (itrg0) as a trigger, the conversion start analog input pin through the conversion termination analog input pin specified by the adscm00 or adscm10 register are sequentially sele cted and a/d converted. conversion results are stored in the adcr0n or adcr1n registers corresponding to the analog inputs. when all of the specified a/d co nversions terminate, an a/d conversion termination interrupt (intad0 or intad1) is generated, which terminates a/d conversion (adcs0 or adcs1 = 0). this is optimal for applications that regularly monitor mu ltiple analog inputs in synchronization with a timer trigger. trigger analog input a/d conversion result register anin0 adcrn0 anin1 adcrn1 anin2 adcrn2 anin3 adcrn3 anin4 adcrn4 anin5 adcrn5 anin6 adcrn6 interrupt specified by itrg0 register anin7 adcrn7 remark n = 0, 1 after all of the specified a/d conversi ons terminate, the a/d converter changes to trigger wait status (adce0 or adce1 = 1). it performs a/d conversion operation again wh en the interrupt signal specif ied in the itrg0 register occurs. figure 13-11. example of timer trigger scan mode operation (for a/d converter 0) : inttm00 selected by itrg0 register (a) set to scan ani01 to ani04 ani00 ani01 ani02 ani03 ani04 ani05 ani06 ani07 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr06 adcr07 a/d converter 0 intm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) inttm00 interrupt generation (3) a/d conversion of ani01 (4) store conversion result in adcr01 (5) a/d conversion of ani02 (6) store conversion result in adcr02 (7) a/d conversion of ani03 (8) store conversion result in adcr03 (9) a/d conversion of ani04 (10) store conversion result in adcr04 (11) intad0 interrupt generation chapter 13 a/d converter 659 user?s manual u14492ej4v1ud 13.9 operation in external trigger mode in external trigger mode, analog input (ani00 to ani07, ani10 to ani17) is a/d converted on adtrg0 or adtrg1 pin input timing. the valid edge of an external input signal in external tr igger mode can be specified as a rising edge, a falling edge, or a rising or falling edge in the es21 or es20 bit of the intm1 register for a/d converter 0 and in the es31 or es30 bit of the intm1 register for a/d converter 1. 13.9.1 operation in select mode one analog input (ani00 to ani07, an i10 to ani17) specified by the ad scm00 or adscm10 register is a/d converted. the conversion result is stored in the adcr0n or adcr1n register (n = 0 to 7). using an adtrg0 or adtrg1 signal as a trigger, one analog input at a time is a/d c onverted and the result is stored in one adcr0n or adcr1n register. analog input s correspond one-to-one with a/d conversion result registers. for each a/d conversion, an a/d conversion termination interrupt (intad0 or intad1) is generated, which terminates a/d conversion (adcs0 or adcs1 bit = 0). trigger analog input a/d conversion result register adtrgm signal animn adcrmn remark m = 0, 1 n = 0 to 7 to restart a/d conversion, a trigger must be input again from the adtrgn pin (n = 0, 1). this is optimal for applications that read results each ti me there is an a/d conversion in synchronization with an external trigger. figure 13-12. example of select mode (external tr igger select) operation (ani02): for a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 ani06 ani07 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr06 adcr07 a/d converter 0 adtrg0 (1) adce0 bit of adscm00 = 1 (enabled) (2) external trigger generation (3) a/d conversion of ani02 (4) store conversion result in adcr02 (5) intad0 interrupt generation chapter 13 a/d converter 660 user?s manual u14492ej4v1ud 13.9.2 operation in scan mode using an adtrg0 or adtrg1 signal as a trigger, pins from the conversion start analog input pin through the conversion termination analog input pin specified by the adscm00 or adscm10 register are sequentially selected and a/d converted. a/d conversion results are stored in the adcr0n or adcrn1n registers corresponding to the analog inputs (n = 0 to 7). when conversion terminates for all of the specified analog inputs, an intad0 or intad1 interrupt is generated, which terminates a/d conversion (adcs0 or adcs1 = 0). trigger analog input a/d conversion result register anin0 adcrn0 anin1 adcrn1 anin2 adcrn2 anin3 adcrn3 anin4 adcrn4 anin5 adcrn5 anin6 adcrn6 adtrgn signal anin7 adcrn7 remark n = 0, 1 after all specified a/d conversions terminate, a/d conversion is restarted when an external trigger signal occurs. this is optimal for applications that regularly monitor mult iple analog inputs in synchronization with an external trigger. figure 13-13. example of scan mode (external trigger scan) operation: for a/d converter 0 (a) when setting to scan ani01 to ani04 ani00 ani01 ani02 ani03 ani04 ani05 ani06 ani07 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 adcr06 adcr07 a/d converter 0 adtrg0 (1) adce0 bit of adscm00 = 1 (enabled) (2) external trigger generation (3) a/d conversion of ani01 (4) store conversion result in adcr01 (5) a/d conversion of ani02 (6) store conversion result in adcr02 (7) a/d conversion of ani03 (8) store conversion result in adcr03 (9) a/d conversion of ani04 (10) store conversion result in adcr04 (11) intad0 interrupt generation chapter 13 a/d converter 661 user?s manual u14492ej4v1ud 13.10 precautions on operation 13.10.1 stopping a/d conversion operation if 0 is written in the adce0 or adce1 bit of the adscm0 0 or adscm10 register during a/d conversion operation, it stops a/d conversion operation and an a/d conversion resu lt is not stored in the adcr0n or adcr1n register (n = 0 to 7). 13.10.2 trigger input during a/d conversion operation if a trigger is input during a/d conversion op eration, that trigger input is ignored. 13.10.3 external or timer trigger interval make the trigger interval (input time interval) in external or timer trigger mode longer than the conversion time specified by the fr2 to fr0 bits of the adscm01 or adscm11 register. (1) when interval = 0 if multiple triggers are input simultaneously, they are processed as one trigger signal. (2) when 0 < interval < conversion time if an external or timer trigger is input during a/d c onversion operation, that trigger input is ignored. (3) when interval = conversion time if an external or timer trigger is input at the same time as a/d conversion termination (comparison termination signal and trigger contention), interrupt generation and adcr0n or adcr1n register storage of the value with which conversion terminated are performed correctly (n = 0 to 7). 13.10.4 operation in standby modes (1) halt mode a/d conversion operation is suspended. if released by nmi or maskable interrupt input, the adscm00, adscm10, adscm01, or adscm11 register and adcr0n or adcr1n register maintain their values (n = 0 to 7). if released by reset input, the adcr0n or adcr1n register is initialized. (2) idle mode, software stop mode since clock supply to a/d converter 0 or 1 st ops, a/d conversion operation is not performed. if released by nmi or maskable interrupt input, the adscm00, adscm10, adscm 01, or adscm11 register and adcr0n or adcr1n register maintain their values (n = 0 to 7). however, if idle mode or software stop mode is set during a/d conversion oper ation, a/d conversion operation stops. if released by reset input, the adcr0n or adcr1n register is initialized. chapter 13 a/d converter 662 user?s manual u14492ej4v1ud 13.10.5 compare match interrupt in timer trigger mode a tm0n timer 0 register underflow interrupt (inttm00 or inttm01) and cm003 or cm013 interrupt (intcm003 or intcm013) is an a/d conversion start trigger that starts conv ersion operation (n = 0, 1). at this time, the cm003 or cm013 match interrupt (intcm003 or intcm013) also functions as a compare register match interrupt for the cpu. in order not to generate these match interrupts for the cpu, disable inte rrupts using the mask bits (tm0mk0, tm0mk1, cm03mk0, cm03mk1) of the interrupt contro l registers (tm0ic0, tm0ic1, cm03ic0, cm03ic1). 13.10.6 timing that makes the a/ d conversion result undefined if the timing of the end of a/d conversion and the timing of the stop of operation of the a/d converter conflict, the a/d conversion value may be undefined. because of this , be sure to read the a/d conversion result while the a/d converter is in operation. furthermore, when reading an a/d conversion result after the a/d converter operation has stopped, be sure to have done so by the ti me the next conversion result is complete. the conversion result read timing is shown in figures 13-14 and 13-15 below. figure 13-14. conversion result read timi ng (when conversion resu lt is undefined) a/d conversion end a/d conversion end adcrnm intadn adcen normal conversion result read normal conversion result undefined value a/d operation stopped undefined value read remark n = 0, 1, m = 0 to 7 figure 13-15. conversion result read ti ming (when conversion result is normal) a/d conversion end adcrnm intadn adcen a/d operation stopped normal conversion result read normal conversion result remark n = 0, 1, m = 0 to 7 chapter 13 a/d converter 663 user?s manual u14492ej4v1ud 13.11 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltage that can be identified. that is, the per centage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). %fsr indicates the ratio of analog input voltage that can be converted as a percentage, and is always repr esented by the following formula regardless of the resolution. 1%fsr = (max. value of analog input voltage that can be converted ? min. value of analog input voltage that can be converted)/100 = (av refn ? 0)/100 = av refn /100 remark n = 0, 1 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098 %fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. it is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. note that the quantization error is not included in the overall erro r in the characteristics table. figure 13-16. overall error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av refn (n = 0, 1) 0 chapter 13 a/d converter 664 user?s manual u14492ej4v1ud (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is convert ed to the same digital code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 13-17. quan tization error 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av refn (n = 0, 1) (4) zero-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (1/2lsb) when the digital output changes from 0??000 to 0??001. figure 13-18. zero-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av refn (n = 0, 1) digital output (lower 3 bits) analog input (lsb) ?1 100 chapter 13 a/d converter 665 user?s manual u14492ej4v1ud (5) full-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (full scale ? 3/2lsb) when the digital output changes from 1??110 to 1??111. figure 13-19. full-scale error 100 011 010 000 ?0 av refn av refn ?1 av refn ?2 av refn ?3 digital output (lower 3 bits) analog input (lsb) full-scale error 111 (n = 0, 1) (6) differential linearity error while the ideal width of code output is 1lsb, this in dicates the difference between the actual measurement value and the ideal value. figure 13-20. differential linearity error 0 av refn (n = 0, 1) digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width chapter 13 a/d converter 666 user?s manual u14492ej4v1ud (7) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. figure 13-21. integral linearity error 0 av refn (n = 0, 1) digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 (8) conversion time this expresses the time from when a trigger was gener ated to the time when the digital output was obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. figure 13-22. sampling time sampling time conversion time 667 user?s manual u14492ej4v1ud chapter 14 port functions 14.1 features input dedicated ports : 8 i/o ports: 75 ports alternate as i/o pins of other peripheral functions input or output can be specified in bit units 14.2 basic configuration of ports the v850e/ia1 has a total of 83 on-chip input/output ports (ports 0 to 4, dh, dl, cs, ct, cm), of which 8 are input-only ports. the port c onfiguration is shown below. port dh p00 p07 p10 p15 p20 p27 p30 p37 p40 p47 pdh0 pdh7 pdl0 pdl15 pcs0 pcs7 pct0 pct7 pcm0 pcm4 port dl port cs port ct port cm port 0 port 1 port 2 port 3 port 4 (1) functions of each port the v850e/ia1 has the ports shown below. any port can operate in 8-bit or 1-bit un its and can provide a variety of controls. moreover, besides its function as a port, each has functions as the i/o pins of on-chip peripheral i/o in control mode. refer to (3) port block diagrams for a block diagram of the block type of each port. chapter 14 port functions 668 user?s manual u14492ej4v1ud port name pin name port function function in control mode block type port 0 p00 to p07 8-bit input nmi inpu t, real-time pulse unit (rpu) output stop signal input, external interrupt input, a/d converter (adc) external trigger input f port 1 p10 to p15 6-bit i/o real-time pulse unit (rpu) i/o external interrupt input b, n port 2 p20 to p27 8-bit i/o real-time pulse unit (rpu) i/o external interrupt input b, n port 3 p30 to p37 8-bit i/o serial interface i/o (uart0 to uart2) a, c, g, h, m port 4 p40 to p47 8-bit i/o serial interface i/o (csi0, csi1, fcan) a, c, m port dh pdh0 to pdh7 8-bit i/o external address bus (a16 to a23) p port dl pdl0 to pdl15 16-bit i/o external address/data bus (ad0 to ad15) o port cs pcs0 to pcs7 8-bit i/o exter nal bus interface control signal output j port ct pct0 to pct7 8-bit i/o external bus interface control signal output e, j port cm pcm0 to pcm4 5-bit i/o wait inse rtion signal input, in ternal system clock output, external bus interface control signal i/o d, e, j cautions 1. when switching to the control mode, be sure to set ports that operate as output pins or i/o pins in the control mode using the following procedure. <1> set the inactive level for the signal outpu t in the control mode in the corresponding bits of port n (n = 0 to 4, cm, cs, ct, dh, and dl). <2> switch to the control mode using the port n mode control register (pmcn). if <1> above is not performed, the conten ts of port n may be output for a moment when switching from the port mode to the control mode. 2. when port manipulation is performed by a bit manipulation instruction (set1, clr1, or not1), perform byte data read for the port a nd process the data of only the bits to be manipulated, and write the byte data after conversion back to the port. for example, in ports in which input and output are mixed , because the contents of the output latch are overwritten to bits other than the bits for manipulation, the output latch of the input pin becomes undefined (in the input mode, however, the pin status does not change because the output buffer is off). therefore, when switching the port from input to output, set the output expected value to the corresponding bit, and then switch to the output port. this is the same as when the control mode and output port are mixed. 3. the state of the port pin can be read by se tting the port n mode register (pmn) to the input mode regardless of the settings of the pmcn register. when th e pmn register is set to the output mode, the value of the port n register (p n) can be read in the port mode while the output state of the alternate function can be read in the control mode. chapter 14 port functions 669 user?s manual u14492ej4v1ud (2) functions of each port pin after reset and registers that set port or control mode pin function after reset port name pin name single-chip mode 0 single-chip mode 1 romless mode 0 romless mode 1 mode-setting register p00/nmi p00 (input mode) p01/eso0/intp0 p01 (input mode) p02/eso1/intp1 p02 (input mode) p03/adtrg0/intp2 p03 (input mode) p04/adtrg1/intp3 p04 (input mode) p05/intp4 p05 (input mode) p06/intp5 p06 (input mode) port 0 p07/intp6 p07 (input mode) ? p10/tiud10/to10 p10 (input mode) pmc1, pfc1 p11/tcud10/intp100 p11 (input mode) p12/tclr10/intp101 p12 (input mode) pmc1 p13/tiud11/to11 p13 (input mode) pmc1, pfc1 p14/tcud11/intp110 p14 (input mode) port 1 p15/tclr11/intp111 p15 (input mode) pmc1 p20/ti2/intp20 p20 (input mode) pmc2 p21/to21/intp21 p21 (input mode) p22/to22/intp22 p22 (input mode) p23/to23/intp23 p23 (input mode) p24/to24/intp24 p24 (input mode) pmc2, pfc2 p25/tclr2/intp25 p25 (input mode) p26/ti3/tclr3/intp30 p26 (input mode) pmc2 port 2 p27/to3/intp31 p27 (input mode) pmc2, pfc2 p30/rxd0 p30 (input mode) p31/txd0 p31 (input mode) p32/rxd1 p32 (input mode) p33/txd1 p33 (input mode) p34/asck1 p34 (input mode) p35/rxd2 p35 (input mode) p36/txd2 p36 (input mode) port 3 p37/asck2 p37 (input mode) pmc3 chapter 14 port functions 670 user?s manual u14492ej4v1ud pin function after reset port name pin name single-chip mode 0 single-chip mode 1 romless mode 0 romless mode 1 mode-setting register p40/si0 p40 (input mode) p41/so0 p41 (input mode) p42/sck0 p42 (input mode) p43/si1 p43 (input mode) p44/so1 p44 (input mode) p45/sck1 p45 (input mode) p46/crxd p46 (input mode) port 4 p47/ctxd p47 (input mode) pmc4 pcm0/wait pcm0 (input mode) wait pcm1/clkout pcm1 (input mode) clkout pcm2/hldak pcm2 (input mode) hldak pcm3/hldrq pcm3 (input mode) hldrq pmccm port cm pcm4 pcm4 (input mode) ? pct0/lwr pct0 (input mode) lwr pct1/uwr pct1 (input mode) uwr pmcct pct2 pct2 (input mode) pct3 pct3 (input mode) ? pct4/rd pct4 (input mode) rd pmcct pct5 pct5 (input mode) ? pct6/astb pct6 (input mode) astb pmcct port ct pct7 pct7 (input mode) ? port cs pcs0/cs0 to pcs7/cs7 pcs0 to pcs7 (input mode) cs0 to cs7 pmccs port dh pdh0/a16 to pdh7/a23 pdh0 to pdh7 (input mode) a16 to a23 pmcdh port dl pdl0/ad0 to pdl15/ad15 pdl0 to pdl15 (input mode) ad0 to ad15 pmcdl chapter 14 port functions 671 user?s manual u14492ej4v1ud (3) port block diagrams figure 14-1. type a block diagram wr pmc wr pm wr port rd in pmcmn pmmn pmn output signal in control mode pmn address internal bus selector selector selector remark m: port number n: bit number chapter 14 port functions 672 user?s manual u14492ej4v1ud figure 14-2. type b block diagram wr pmc wr pm wr port rd in pmcmn pmmn pmn pmn address noise elimination edge detection input signal in control mode internal bus selector selector remark m: port number n: bit number chapter 14 port functions 673 user?s manual u14492ej4v1ud figure 14-3. type c block diagram wr pmc wr pm wr port rd in pmcmn pmmn pmn pmn address input signal in control mode internal bus selector selector remark m: port number n: bit number chapter 14 port functions 674 user?s manual u14492ej4v1ud figure 14-4. type d block diagram wr pm wr port rd in pmmn wr pmc pmcmn pmn pmn mode0 to mode2 address input signal in control mode selector selector internal bus remark m: port number n: bit number figure 14-5. type e block diagram wr port rd in wr pm pmn pmn pmmn address selector selector internal bus remark m: port number n: bit number chapter 14 port functions 675 user?s manual u14492ej4v1ud figure 14-6. type f block diagram rd in pmn address noise elimination edge detection 1 input signal in control mode internal bus selector figure 14-7. type g block diagram wr pmc wr pm wr port rd in pmcmn pmmn pmn output signal in control mode pmn address internal bus selector selector selector remark m: port number n: bit number chapter 14 port functions 676 user?s manual u14492ej4v1ud figure 14-8. type h block diagram internal bus selector selector wr pmc wr pm wr port rd in pmcmn pmmn pmn pmn address input signal in control mode remark m: port number n: bit number chapter 14 port functions 677 user?s manual u14492ej4v1ud figure 14-9. type j block diagram wr pmc wr pm wr port rd in pmcmn pmmn pmn output signal in control mode pmn address internal bus selector selector selector mode0 to mode2 remark m: port number n: bit number chapter 14 port functions 678 user?s manual u14492ej4v1ud figure 14-10. type m block diagram wr pmc wr pm wr port rd in pmcmn pmmn pmn pmn address input signal in control mode output signal in control mode sckx, ascky output enable signal internal bus selector selector selector remark mn: 34, 37, 42, 45 x: 0 (when mn = 42) 1 (when mn = 45) y: 1 (when mn = 34) 2 (when mn = 37) chapter 14 port functions 679 user?s manual u14492ej4v1ud figure 14-11. type n block diagram wr pfc wr pmc wr pm wr port rd in pfcmn pmcmn pmmn pmn pmn address input signal in control mode output signal in control mode noise elimination edge detection internal bus selector selector selector remark m: port number n: bit number chapter 14 port functions 680 user?s manual u14492ej4v1ud figure 14-12. type o block diagram wr pm wr port rd in pmmn wr pmc pmcmn pmn pmn output signal in control mode mode0 to mode2 i/o control i/o control address input signal in control mode selector selector internal bus selector remark m: port number n: bit number chapter 14 port functions 681 user?s manual u14492ej4v1ud figure 14-13. type p block diagram wr pm wr port rd in pmmn wr pmc pmcmn pmn pmn mode0 to mode2 output signal in control mode i/o control address selector selector internal bus selector remark m: port number n: bit number chapter 14 port functions 682 user?s manual u14492ej4v1ud 14.3 pin functions of each port 14.3.1 port 0 port 0 is an 8-bit input dedicated port in which all pins are fixed for input. 7 p07 p0 6 p06 5 p05 4 p04 3 p03 2 p02 1 p01 0 p00 address fffff400h initial value undefined besides functioning as an input port, in control mode, it al so can operate as the real-t ime pulse unit (rpu) output stop signal input, external interrupt request input, and a/d converter (adc) external trigger input. although this port also serves as nmi, eso0/intp0, eso1/intp1, adtrg0/intp2, adtrg1/intp3, and intp4 to intp6, nmi, eso0/intp0, eso1 /intp1, adtrg0/intp2, adtrg1/intp3, and intp4 to intp6 cannot be switched with input port. the status of each pin is read by reading the port. (1) operation in control mode port alternate pin name remarks block type p00 nmi non-maskable interrupt request input p01 eso0/intp0 p02 eso1/intp1 real-time pulse unit (rpu) ou tput stop signal input or external interrupt request input p03 adtrg0/intp2 p04 adtrg1/intp3 a/d converter (adc) external trigger input or external interrupt request input port 0 p05 to p07 intp4 to intp6 external interrupt request input f chapter 14 port functions 683 user?s manual u14492ej4v1ud 14.3.2 port 1 port 1 is a 6-bit i/o port in which input or output can be specified in 1-bit units. 7 ? p1 6 ? 5 p15 4 p14 3 p13 2 p12 1 p11 0 p10 address fffff402h initial value undefined bit position bit name function 5 to 0 p1n (n = 5 to 0) i/o port besides functioning as a port, in control mode, it al so can operate as the real-time pulse unit (rpu) i/o and external interrupt request input. (1) operation in control mode port alternate pin name remarks block type p10 tiud10/to10 real-time pulse unit (rpu) i/o n p11 tcud10/intp100 p12 tclr10/intp101 real-time pulse unit (rpu) i nput or external interrupt request input b p13 tiud11/to11 real-time pulse unit (rpu) i/o n p14 tcud11/intp110 port 1 p15 tclr11/intp111 real-time pulse unit (rpu) i nput or external interrupt request input b (2) setting in i/o mode and control mode port 1 is set in i/o mode using the port 1 mode register (pm1). in control mode, it is set using the port 1 mode control register (pmc1) and port 1 function control register (pfc1). (a) port 1 mode register (pm1) this register can be read/written in 8-bit or 1-bit units. write 1 in bits 6 and 7. 7 1 pm1 6 1 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 address fffff422h initial value ffh bit position bit name function 5 to 0 pm1n (n = 5 to 0) specifies input/output mode of p1n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions 684 user?s manual u14492ej4v1ud (b) port 1 mode control register (pmc1) this register can be read/written in 8-bit or 1-bit units. write 0 in bits 6 and 7. caution the pmc11, pmc12, pmc14, and pmc15 bits also serve as external interrupts (intp100, intp101, intp110, and intp111). when not using them as external interrupts, mask interrupt requests (refer to 7.3.4 interrupt control register (xxicn)). 7 0 pmc1 6 0 5 pmc15 4 pmc14 3 pmc13 2 pmc12 1 pmc11 0 pmc10 address fffff442h initial value 00h bit position bit name function 5 pmc15 specifies operation mode of p15 pin. 0: i/o port mode 1: tclr11 input mode or external interrupt request (intp111) input mode 4 pmc14 specifies operation mode of p14 pin. 0: i/o port mode 1: tcud11 input mode or external interrupt request (intp110) input mode 3 pmc13 specifies operation mode of p13 pin. 0: i/o port mode 1: tiud11 input mode or to11 output mode 2 pmc12 specifies operation mode of p12 pin. 0: i/o port mode 1: tclr10 input mode or external interrupt request (intp101) input mode 1 pmc11 specifies operation mode of p11 pin. 0: i/o port mode 1: tcud10 input mode or external interrupt request (intp100) input mode 0 pmc10 specifies operation mode of p10 pin. 0: i/o port mode 1: tiud10 input mode or to10 output mode chapter 14 port functions 685 user?s manual u14492ej4v1ud (c) port 1 function control register (pfc1) this register can be read/written in 8-bit or 1- bit units. write 0 in bits other than 0 and 3. caution when port mode is specified by the port 1 mode control register (pmc1), the setting of this register is invalid. 7 0 pfc1 6 0 5 0 4 0 3 pfc13 2 0 1 0 0 pfc10 address fffff462h initial value 00h bit position bit name function 3 pfc13 specifies operation mode of p13 pin in control mode. 0: tiud11 input mode 1: to11 output mode 0 pfc10 specifies operation mode of p10 pin in control mode. 0: tiud10 input mode 1: to10 output mode chapter 14 port functions 686 user?s manual u14492ej4v1ud 14.3.3 port 2 port 2 is an 8-bit i/o port in which input or output can be specified in 1-bit units. 7 p27 p2 6 p26 5 p25 4 p24 3 p23 2 p22 1 p21 0 p20 address fffff404h initial value undefined bit position bit name function 7 to 0 p2n (n = 7 to 0) i/o port besides functioning as a port, in control mode, it al so can operate as the real-time pulse unit (rpu) i/o and external interrupt request input. (1) operation in control mode port alternate pin name remarks block type p20 ti2/intp20 real-time pulse unit (r pu) input or external interrupt request input b p21 to p24 to21/intp21 to to24/intp24 real-time pulse unit (rpu) output or external interrupt request input n p25 tclr2/intp25 p26 ti3/tclr3/intp30 real-time pulse unit (rpu) i nput or external interrupt request input b port 2 p27 to3/intp31 real-time pulse unit (rpu) output or external interrupt request input n (2) setting in i/o mode and control mode port 2 is set in i/o mode using the port 2 mode register (pm2). in control mode, it is set using the port 2 mode control register (pmc2) and port 2 function control register (pfc2). (a) port 2 mode register (pm2) this register can be read/written in 8-bit or 1-bit units. 7 pm27 pm2 6 pm26 5 pm25 4 pm24 3 pm23 2 pm22 1 pm21 0 pm20 address fffff424h initial value ffh bit position bit name function 7 to 0 pm2n (n = 7 to 0) specifies input/output mode of p2n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions 687 user?s manual u14492ej4v1ud (b) port 2 mode control register (pmc2) this register can be read/written in 8-bit or 1-bit units. caution the pmc20, pmc25, and pm c26 bits also serve as extern al interrupts (intp20, intp25, and intp30). when not using them as ext ernal interrupts, mask interrupt requests (refer to 7.3.4 interrupt control register (xxicn)). 7 pmc27 pmc2 6 pmc26 5 pmc25 4 pmc24 3 pmc23 2 pmc22 1 pmc21 0 pmc20 address fffff444h initial value 00h bit position bit name function 7 pmc27 specifies operation mode of p27 pin. 0: i/o port mode 1: to3 output mode or external interrupt request (intp31) input mode 6 pmc26 specifies operation mode of p26 pin. 0: i/o port mode 1: rpu (ti3, tclr3) input mode or external interrupt request (intp30) input mode 5 pmc25 specifies operation mode of p25 pin. 0: i/o port mode 1: tclr2 input mode or external interrupt request (intp25) input mode 4 to 1 pmc24 to pmc21 specify operation mode of p24 to p21 pins. 0: i/o port mode 1: to24 to to21 output mode or external interrupt request (intp24 to intp21) input mode 0 pmc20 specifies operation mode of p20 pin. 0: i/o port mode 1: ti2 input mode or external interrupt request (intp20) input mode chapter 14 port functions 688 user?s manual u14492ej4v1ud (c) port 2 function control register (pfc2) this register can be read/written in 8-bit or 1-bit units. write 0 in bits 0, 5, and 6. caution when port mode is specified by the port 2 mode control register (pmc2), the setting of this register is invalid. 7 pfc27 pfc2 6 0 5 0 4 pfc24 3 pfc23 2 pfc22 1 pfc21 0 0 address fffff464h initial value 00h bit position bit name function 7 pfc27 specifies operation mode of p27 pin in control mode. 0: external interrupt request (intp31) input mode 1: to3 output mode 4 to 1 pfc24 to pfc21 specify operation mode of p24 to p21 pins in control mode. 0: external interrupt request (intp24 to intp21) input mode 1: to24 to to21 output mode chapter 14 port functions 689 user?s manual u14492ej4v1ud 14.3.4 port 3 port 3 is an 8-bit i/o port in which input or output can be specified in 1-bit units. 7 p37 p3 6 p36 5 p35 4 p34 3 p33 2 p32 1 p31 0 p30 address fffff406h initial value undefined bit position bit name function 7 to 0 p3n (n = 7 to 0) i/o port besides functioning as a port, in control mode, it also c an operate as the serial interface (uart0 to uart2) i/o. (1) operation in control mode port alternate pin name remarks block type p30 rxd0 h p31 txd0 g p32 rxd1 c p33 txd1 a p34 asck1 m p35 rxd2 c p36 txd2 a port 3 p37 asck2 serial interface (uart0 to uart2) i/o m (2) setting in i/o mode and control mode port 3 is set in i/o mode using the port 3 mode register (pm3). in control mode, it is set using the port 3 mode control register (pmc3). (a) port 3 mode register (pm3) this register can be read/written in 8-bit or 1-bit units. 7 pm37 pm3 6 pm36 5 pm35 4 pm34 3 pm33 2 pm32 1 pm31 0 pm30 address fffff426h initial value ffh bit position bit name function 7 to 0 pm3n (n = 7 to 0) specifies input/output mode of p3n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions 690 user?s manual u14492ej4v1ud (b) port 3 mode control register (pmc3) this register can be read/written in 8-bit or 1-bit units. 7 pmc37 pmc3 6 pmc36 5 pmc35 4 pmc34 3 pmc33 2 pmc32 1 pmc31 0 pmc30 address fffff446h initial value 00h bit position bit name function 7 pmc37 specifies operation mode of p37 pin. 0: i/o port mode 1: asck2 i/o mode 6 pmc36 specifies operation mode of p36 pin. 0: i/o port mode 1: txd2 output mode 5 pmc35 specifies operation mode of p35 pin. 0: i/o port mode 1: rxd2 input mode 4 pmc34 specifies operation mode of p34 pin. 0: i/o port mode 1: asck1 i/o mode 3 pmc33 specifies operation mode of p33 pin. 0: i/o port mode 1: txd1 output mode 2 pmc32 specifies operation mode of p32 pin. 0: i/o port mode 1: rxd1 input mode 1 pmc31 specifies operation mode of p31 pin. 0: i/o port mode 1: txd0 output mode 0 pmc30 specifies operation mode of p30 pin. 0: i/o port mode 1: rxd0 input mode chapter 14 port functions 691 user?s manual u14492ej4v1ud 14.3.5 port 4 port 4 is an 8-bit i/o port in which input or output can be specified in 1-bit units. 7 p47 p4 6 p46 5 p45 4 p44 3 p43 2 p42 1 p41 0 p40 address fffff408h initial value undefined bit position bit name function 7 to 0 p4n (n = 7 to 0) i/o port besides functioning as a port, in contro l mode, it also can operate as the se rial interface (csi0, csi1, fcan) i/o. (1) operation in control mode port alternate pin name remarks block type p40 si0 c p41 so0 a p42 sck0 m p43 si1 c p44 so1 a p45 sck1 m p46 crxd c port 4 p47 ctxd serial interface (csi0, csi1, fcan) i/o a (2) setting in i/o mode and control mode port 4 is set in i/o mode using the port 4 mode register (pm4). in control mode, it is set using the port 4 mode control register (pmc4). (a) port 4 mode register (pm4) this register can be read/written in 8-bit or 1-bit units. 7 pm47 pm4 6 pm46 5 pm45 4 pm44 3 pm43 2 pm42 1 pm41 0 pm40 address fffff428h initial value ffh bit position bit name function 7 to 0 pm4n (n = 7 to 0) specifies input/output mode of p4n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions 692 user?s manual u14492ej4v1ud (b) port 4 mode control register (pmc4) this register can be read/written in 8-bit or 1-bit units. 7 pmc47 pmc4 6 pmc46 5 pmc45 4 pmc44 3 pmc43 2 pmc42 1 pmc41 0 pmc40 address fffff448h initial value 00h bit position bit name function 7 pmc47 specifies operation mode of p47 pin. 0: i/o port mode 1: ctxd output mode 6 pmc46 specifies operation mode of p46 pin. 0: i/o port mode 1: crxd input mode 5 pmc45 specifies operation mode of p45 pin. 0: i/o port mode 1: sck1 i/o mode 4 pmc44 specifies operation mode of p44 pin. 0: i/o port mode 1: so1 output mode 3 pmc43 specifies operation mode of p43 pin. 0: i/o port mode 1: si1 input mode 2 pmc42 specifies operation mode of p42 pin. 0: i/o port mode 1: sck0 i/o mode 1 pmc41 specifies operation mode of p41 pin. 0: i/o port mode 1: so0 output mode 0 pmc40 specifies operation mode of p40 pin. 0: i/o port mode 1: si0 input mode chapter 14 port functions 693 user?s manual u14492ej4v1ud 14.3.6 port dh port dh is an 8-bit i/o port in which input or output can be specif ied in 1-bit units. 7 pdh7 pdh 6 pdh6 5 pdh5 4 pdh4 3 pdh3 2 pdh2 1 pdh1 0 pdh0 address fffff006h initial value undefined bit position bit name function 7 to 0 pdhn (n = 7 to 0) i/o port besides functioning as a port, in c ontrol mode, this can operate as an address bu s when memory is expanded externally. (1) operation in control mode port alternate pin name remarks block type port dh pdh7 to pdh0 a23 to a16 memory expansion address bus p (2) setting in i/o mode and control mode port dh is set in i/o mode using the port dh mode register (pmdh). in control mode, it is set using the port dh mode control register (pmcdh). (a) port dh mode register (pmdh) this register can be read/written in 8-bit or 1-bit units. 7 pmdh7 pmdh 6 pmdh6 5 pmdh5 4 pmdh4 3 pmdh3 2 pmdh2 1 pmdh1 0 pmdh0 address fffff026h initial value ffh bit position bit name function 7 to 0 pmdhn (n = 7 to 0) specifies input/output mode of pdhn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions 694 user?s manual u14492ej4v1ud (b) port dh mode control register (pmcdh) this register can be read/written in 8-bit or 1-bit units. 7 pmcdh7 pmcdh 6 pmcdh6 5 pmcdh5 4 pmcdh4 3 pmcdh3 2 pmcdh2 1 pmcdh1 0 pmcdh0 address fffff046h initial value note 00h/ffh note 00h: single-chip mode 0 ffh: single-chip mode 1, romless mode 0 or 1 bit position bit name function 7 to 0 pmcdhn (n = 7 to 0) specifies operation mode of pdhn pin. 0: i/o port mode 1: a23 to a16 output mode chapter 14 port functions 695 user?s manual u14492ej4v1ud 14.3.7 port dl port dl is a 16-bit or 8-bit i/o port in which input or output can be spec ified in 1-bit units. when using the higher 8 bits of pdl as pdlh and the lower 8 bits as pdll, it can be used as an 8-bit i/o port that can specify input or output in 1-bit units. 15 pdl15 pdl 14 pdl14 13 pdl13 12 pdl12 11 pdl11 10 pdl10 9 pdl9 8 pdl8 7 pdl7 6 pdl6 5 pdl5 4 pdl4 3 pdl3 2 pdl2 1 pdl1 0 pdl0 address fffff005h initial value undefined address fffff004h bit position bit name function 15 to 0 pdln (n = 15 to 0) i/o port besides functioning as a port, in control mode, this c an operate as an address/data bus when memory is expanded externally. (1) operation in control mode port alternate pin name remarks block type port dl pdl15 to pdl0 ad15 to ad0 memory expansion address/data bus o (2) setting in i/o mode and control mode port dl is set in i/o mode using the port dl mode register (pmdl). in control mode, it is set using the port dl mode control register (pmcdl). chapter 14 port functions 696 user?s manual u14492ej4v1ud (a) port dl mode register (pmdl) the pmdl register can be read/written in 16-bit units. when using the higher 8 bits of t he pmdl register as the pmdlh regi ster and the lower 8 bits as the pmdll register, it can be read/written in 8-bit or 1-bit units. 15 pmdl15 pmdl 14 pmdl14 13 pmdl13 12 pmdl12 11 pmdl11 10 pmdl10 9 pmdl9 8 pmdl8 7 pmdl7 6 pmdl6 5 pmdl5 4 pmdl4 3 pmdl3 2 pmdl2 1 pmdl1 0 pmdl0 address fffff025h initial value ffffh address fffff024h bit position bit name function 15 to 0 pmdln (n = 15 to 0) specifies input/output mode of pdln pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port dl mode control register (pmcdl) the pmcdl register can be r ead/written in 16-bit units. when using the higher 8 bits of the pmcdl register as the pmcdlh register and the lower 8 bits as the pmcdll register, it can be read/wri tten in 8-bit or 1-bit units. 15 pmcdl15 pmcdl 14 pmcdl14 13 pmcdl13 12 pmcdl12 11 pmcdl11 10 pmcdl10 9 pmcdl9 8 pmcdl8 7 pmcdl7 6 pmcdl6 5 pmcdl5 4 pmcdl4 3 pmcdl3 2 pmcdl2 1 pmcdl1 0 pmcdl0 address fffff045h initial value note 0000h/ffffh address fffff044h note 0000h : single-chip mode 0 ffffh : single-chip mode 1, romless mode 0 or 1 bit position bit name function 15 to 0 pmcdln (n = 15 to 0) specifies operation mode of pdln pin. 0: i/o port mode 1: ad15 to ad0 i/o mode chapter 14 port functions 697 user?s manual u14492ej4v1ud 14.3.8 port cs port cs is an 8-bit i/o port in which input or output can be specif ied in 1-bit units. 7 pcs7 pcs 6 pcs6 5 pcs5 4 pcs4 3 pcs3 2 pcs2 1 pcs1 0 pcs0 address fffff008h initial value undefined bit position bit name function 7 to 0 pcsn (n = 7 to 0) i/o port besides functioning as a port, in control mode, this can op erate as the chip select signal output when memory is expanded externally. (1) operation in control mode port alternate pin name remarks block type port cs pcs7 to pcs0 cs0 to cs7 chip select signal output j chapter 14 port functions 698 user?s manual u14492ej4v1ud (2) setting in i/o mode and control mode port cs is set in i/o mode using the port cs mode register (pmcs). in control mode, it is set using the port cs mode control register (pmccs). (a) port cs mode register (pmcs) this register can be read/written in 8-bit or 1-bit units. 7 pmcs7 pmcs 6 pmcs6 5 pmcs5 4 pmcs4 3 pmcs3 2 pmcs2 1 pmcs1 0 pmcs0 address fffff028h initial value ffh bit position bit name function 7 to 0 pmcsn (n = 7 to 0) specifies input/output mode of pcsn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port cs mode control register (pmccs) this register can be read/written in 8-bit or 1-bit units. 7 pmccs7 pmccs 6 pmccs6 5 pmccs5 4 pmccs4 3 pmccs3 2 pmccs2 1 pmccs1 0 pmccs0 address fffff048h initial value note 00h/ffh note 00h: single-chip mode 0 ffh: single-chip mode 1, romless mode 0 or 1 bit position bit name function 7 to 0 pmccsn (n = 7 to 0) specifies operation mode of pcsn pin. 0: i/o port mode 1: cs7 to cs0 output mode chapter 14 port functions 699 user?s manual u14492ej4v1ud 14.3.9 port ct port ct is an 8-bit i/o port in which input or output can be specif ied in 1-bit units. 7 pct7 pct 6 pct6 5 pct5 4 pct4 3 pct3 2 pct2 1 pct1 0 pct0 address fffff00ah initial value undefined bit position bit name function 7 to 0 pctn (n = 7 to 0) i/o port besides functioning as a port, in control mode, this can operate as control signal outputs when memory is expanded externally. (1) operation in control mode port alternate pin name remarks block type pct0 lwr pct1 uwr write strobe signal output j pct2 pct3 ? fixed in port mode e pct4 rd read strobe signal output j pct5 ? fixed in port mode e pct6 astb address strobe signal output j port ct pct7 ? fixed in port mode e (2) setting in i/o mode and control mode port ct is set in i/o mode using the port ct mode register (pmct). in control mode, it is set using the port ct mode control register (pmcct). (a) port ct mode register (pmct) this register can be read/written in 8-bit or 1-bit units. 7 pmct7 pmct 6 pmct6 5 pmct5 4 pmct4 3 pmct3 2 pmct2 1 pmct1 0 pmct0 address fffff02ah initial value ffh bit position bit name function 7 to 0 pmctn (n = 7 to 0) specifies input/output mode of pctn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions 700 user?s manual u14492ej4v1ud (b) port ct mode control register (pmcct) this register can be read/written in 8-bit or 1-bit units. 7 0 pmcct 6 pmcct6 5 0 4 pmcct4 3 0 2 0 1 pmcct1 0 pmcct0 address fffff04ah initial value note 00h/53h note 00h: single-chip mode 0 53h: single-chip mode 1, romless mode 0 or 1 bit position bit name function 6 pmcct6 specifies operation mode of pct6 pin. 0: i/o port mode 1: astb output mode 4 pmcct4 specifies operation mode of pct4 pin. 0: i/o port mode 1: rd output mode 1 pmcct1 specifies operation mode of pct1 pin. 0: i/o port mode 1: uwr output mode 0 pmcct0 specifies operation mode of pct0 pin. 0: i/o port mode 1: lwr output mode chapter 14 port functions 701 user?s manual u14492ej4v1ud 14.3.10 port cm port cm is a 5-bit i/o port in which input or output can be spec ified in 1-bit units. 7 ? pcm 6 ? 5 ? 4 pcm4 3 pcm3 2 pcm2 1 pcm1 0 pcm0 address fffff00ch initial value undefined bit position bit name function 4 to 0 pcmn (n = 4 to 0) i/o port besides functioning as a port, in contro l mode, this can operate as the wait insertion sig nal input, internal system clock output, and bus hold control signal output. (1) operation in control mode port alternate pin name remarks block type pcm0 wait note wait insertion signal input d pcm1 clkout internal system clock output j pcm2 hldak bus hold acknowledge signal output j pcm3 hldrq note bus hold request signal input d port cm pcm4 ? fixed in port mode e note the wait and hldrq signals are set to control mode by default in romless mode 0, 1 or single-chip mode 1. be sure to fix these pins to the inactive level when not used. these pins function in control mode until port mode is set using the port cm mode control regi ster (pmccm), so be sure to set these pins to the inactive level before setting pmccm. (2) setting in i/o mode and control mode port cm is set in i/o mode using the port cm mode register (pmcm). in control mode, it is set using the port cm mode control register (pmccm). (a) port cm mode register (pmcm) this register can be read/written in 8-bit or 1-bit units. 7 1 pmcm 6 1 5 1 4 pmcm4 3 pmcm3 2 pmcm2 1 pmcm1 0 pmcm0 address fffff02ch initial value ffh bit position bit name function 4 to 0 pmcmn (n = 4 to 0) specifies input/output mode of pcmn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) chapter 14 port functions 702 user?s manual u14492ej4v1ud (b) port cm mode control register (pmccm) this register can be read/written in 8-bit or 1-bit units. 7 0 pmccm 6 0 5 0 4 0 3 pmccm3 2 pmccm2 1 pmccm1 0 pmccm0 address fffff04ch initial value note 00h/0fh note 00h: single-chip mode 0 0fh: single-chip mode 1, romless mode 0 or 1 bit position bit name function 3 pmccm3 specifies operation mode of pcm3 pin. 0: i/o port mode 1: hldrq input mode 2 pmccm2 specifies operation mode of pcm2 pin. 0: i/o port mode 1: hldak output mode 1 pmccm1 specifies operation mode of pcm1 pin. 0: i/o port mode 1: clkout output mode 0 pmccm0 specifies operation mode of pcm0 pin. 0: i/o port mode 1: wait input mode chapter 14 port functions 703 user?s manual u14492ej4v1ud 14.4 operation of port function the operation of a port differs depending on whether it is set in the input or output mode, as follows. 14.4.1 writing to i/o port (1) in output mode a value can be written to the output latch (pn) by writi ng it to the port n register (pn). the contents of the output latch are output from the pin. once data is written to the output latch, it is hel d until new data is written to the output latch. (2) in input mode a value can be written to the output latch (pn) by writing it to the port n regi ster (pn). however, the status of the pin does not change because the output buffer is off. once data is written to the output latch, it is hel d until new data is written to the output latch. caution a bit manipulation instruction (clr1, set 1, not1) manipulates 1 bit but accesses a port in 8-bit units. if this instruction is executed to manipulate a port with a mixture of input and output bits, the contents of the output latch of a pin set in the input mode, in addition to the bit to be manipulated, ar e overwritten to the current input pin status and become undefined. 14.4.2 reading from i/o port (1) in output mode the contents of the output latch (pn) can be read by reading the port n register (pn). the contents of the output latch do not change. (2) in input mode the status of the pin can be read by re ading the port n register (pn). t he contents of the output latch (pn) do not change. 14.4.3 output status of altern ate function in control mode the status of a port pin is not dependent upon the setting of the pmcn register and can be read by setting the port n mode register (pmn) to the input mode. if the pmn register is set to the output mode, the value of the port n register (pn) can be read in the port mode, and the output status of the al ternate function can be read in the control mode. chapter 14 port functions 704 user?s manual u14492ej4v1ud 14.5 noise eliminator 14.5.1 interrupt pins a timing controller to guarantee the noise elimination time s shown below is added to the pins that operate as nmi and valid edge inputs in port control mode. signal input that changes in less than these elimination times is not accepted internally. pin noise elimination time p00/nmi p01/eso0/intp0, p02/eso1/intp1 p03/adtrg0/intp2, p04/adtrg1/intp3 p05/intp4 to p07/intp6 analog delay (approx. 10 ns) cautions 1. the above non-maskable /maskable interrupt pins are used to release standby mode . a clock control timing circuit is not used since the internal system clock is stopped in standby mode. 2. the noise eliminator is valid only in control mode. chapter 14 port functions 705 user?s manual u14492ej4v1ud 14.5.2 timer 10, timer 11, timer 3 input pins noise filtering using the clock sampling shown below is added to the pins that operate as valid edge inputs to timer 10, timer 11, and timer 3. a signal input that changes in less than these elimination times is not accepted internally. pin noise elimination time sampling clock timer 10 p10/tiud10/to10 p11/tcud10/intp100 p12/tclr10/intp101 timer 11 p13/tiud11/to11 p14/tcud11/intp110 p15/tclr11/intp111 select from f xxtm10,11 f xxtm10,11 /2 f xxtm10,11 /4 f xxtm10,11 /8 p26/ti3/intp30/tclr3 select from f xxtm3 /2 f xxtm3 /4 f xxtm3 /8 f xxtm3 /16 timer 3 p27/to3/intp31 4 to 5 clocks select from f xxtm3 /32 f xxtm3 /64 f xxtm3 /128 f xxtm3 /256 cautions 1. since the above pin no ise filtering uses clock sampling, in put signals are not received when the cpu clock is stopped. 2. the noise eliminator is valid only in control mode. remark f xxtm10,11 : clock of tm10 and tm11 selected by prm02 register f xxtm3 : clock of tm3 selected by prm03 register chapter 14 port functions 706 user?s manual u14492ej4v1ud figure 14-14. example of noise elimination timing noise elimination clock input signal internal signal timers 1 to 3 rising edge detection timers 1 to 3 falling edge detection 2 clocks 2 clocks 5 clocks 5 clocks 4 clocks 4 clocks 3 clocks 3 clocks caution if there are three or less noise eliminat ion clocks while the timers 1 to 3 input signals are high level (or low level), th e input pulse is eliminated as noise. if it is sampled at least four times, the edge is detected as valid input. chapter 14 port functions 707 user?s manual u14492ej4v1ud (1) timer 10 noise elimination ti me selection register (nrc10) the nrc10 register is used to set the clock source of timer 10 input pin noise elimination times. this register can be read/written in 8-bit or 1-bit units. 7 0 nrc10 6 0 5 0 4 0 3 0 2 0 1 nrc101 0 nrc100 address fffff5f8h initial value 00h bit position bit name function selects the tiud10/to10, tcud10/intp100, and tclr10/intp101 pin noise elimination clocks. nrc101 nrc100 noise elimination clock 0 0 f xxtm10 /8 0 1 f xxtm10 /4 1 0 f xxtm10 /2 1 1 f xxtm10 1, 0 nrc101, nrc100 remark f xxtm10 : clock of tm10 selected by prm02 register (2) timer 11 noise elimination ti me selection register (nrc11) the nrc11 register is used to set the clock source of timer 11 input pin noise elimination times. this register can be read/written in 8-bit or 1-bit units. 7 0 nrc11 6 0 5 0 4 0 3 0 2 0 1 nrc111 0 nrc110 address fffff618h initial value 00h bit position bit name function selects the tiud11/to11, tcud11/intp110, and tclr11/intp111 pin noise elimination clocks. nrc111 nrc110 noise elimination clock 0 0 f xxtm11 /8 0 1 f xxtm11 /4 1 0 f xxtm11 /2 1 1 f xxtm11 1, 0 nrc111, nrc110 remark f xxtm11 : clock of tm11 selected by prm02 register chapter 14 port functions 708 user?s manual u14492ej4v1ud (3) timer 3 noise elimination ti me selection register (nrc3) the nrc3 register is used to set the clock source of timer 3 input pin noise elimination times. this register can be read/written in 8-bit or 1-bit units. 7 0 nrc3 6 0 5 0 4 0 3 nrc33 2 nrc32 1 nrc31 0 nrc30 address fffff698h initial value 00h bit position bit name function selects the to3/intp31 pin noise elimination clock. nrc33 nrc32 noise elimination clock 0 0 f xxtm3 /256 0 1 f xxtm3 /128 1 0 f xxtm3 /64 1 1 f xxtm3 /32 3, 2 nrc33, nrc32 remark f xxtm3 : clock selected by prm03 register selects the ti3/intp30/tclr3 pin noise elimination clock. nrc31 nrc30 noise elimination clock 0 0 f xxtm3 /16 0 1 f xxtm3 /8 1 0 f xxtm3 /4 1 1 f xxtm3 /2 1, 0 nrc31, nrc30 remark f xxtm3 : clock selected by prm03 register chapter 14 port functions 709 user?s manual u14492ej4v1ud 14.5.3 timer 2 input pins a noise eliminator using analog filtering and digital filt ering using clock sampling are added to the timer 2 input pins. a signal input that changes in less than t hese elimination times is not accepted internally. digital filter pin analog filter noise elimination time noise elimination time sampling clock p20/ti2/intp20 p21/to21/intp21 to p24/to24/intp24 p25/tclr2/intp25 10 to 100 ns 4 to 5 clocks f xxtm2 cautions 1. since digital filteri ng uses clock sampling, if it is sel ected, input signals are not received when the cpu clock is stopped. 2. the noise eliminator is valid only in control mode. 3. refer to figure 14-14 for an example of a noise eliminator. remark f xxtm2 : clock of tm20 and tm21 selected by prm02 register chapter 14 port functions 710 user?s manual u14492ej4v1ud (1) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) the femn registers are used to specify timer 2 input pin filtering and to set the clock source of noise elimination times and the input valid edge. these registers can be read/written in 8-bit or 1-bit units. cautions 1. even when using the ti2/in tp20, to21/intp21, to22/intp22, to23/intp23, to24/intp24, and tclr2/intp25 pins as intp20, intp21, intp22, intp23, intp24, and intp25 without using timer 2, be sure to clear the stfte bit of timer 2 clock stop register 0 (stopte0) to 0. 2. before setting the intp2n pi n to the trigger mode, set the pmc2 register. if the pmc2 register is set after the femn register h as been set, an illegal in terrupt may occur as soon as the pmc2 register is set (n = 0 to 5). (1/2) 7 dfen00 fem0 6 0 5 0 4 0 3 edge010 2 edge000 1 tms010 0 tms000 address fffff630h initial value 00h address fffff631h initial value 00h address fffff632h initial value 00h address fffff633h initial value 00h address fffff634h initial value 00h address fffff635h initial value 00h intp20 7 dfen01 6 0 5 0 4 0 3 edge011 2 edge001 1 tms011 0 tms001 intp21 7 dfen02 6 0 5 0 4 0 3 edge012 2 edge002 1 tms012 0 tms002 intp22 7 dfen03 6 0 5 0 4 0 3 edge013 2 edge003 1 tms013 0 tms003 intp23 7 dfen04 6 0 5 0 4 0 3 edge014 2 edge004 1 tms014 0 tms004 intp24 7 dfen05 6 0 5 0 4 0 3 edge015 2 edge005 1 tms015 0 tms005 intp25 fem1 fem2 fem3 fem4 fem5 bit position bit name function 7 dfen0n specifies the intp2n pin filter. 0: analog filter 1: digital filter caution when the dfen0n bit = 1, the sa mpling clock of the digital filter is f xxtm2 (clock of tm20 and tm21 selected by prm02 register). remark n = 0 to 5 chapter 14 port functions 711 user?s manual u14492ej4v1ud (2/2) bit position bit name function specifies the intp2n pin valid edge. edge01n edge00n operation 0 0 interrupt due to intcc2n note 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges 3, 2 edge01n, edge00n note specify when selecting intcc2n according to match of tm20, tm21 and sub-channel compare registers (tms01n, tms00n bit settings) (n = 0 to 5). selects capture input note . tms01n tms00n operation 0 0 use as pin 0 1 digital filter (noise eliminator specification) 1 0 capture to sub-channel 1 according to timer 1 1 capture to sub-channel 2 according to timer 1, 0 tms01n, tms00n note capture input according to intcm100 and intcm101 can be selected only for the fem1 and fem2 registers. set the values of the tms01m and tms00m bits in the femm register to 00b or 01b. settings other than these are prohibited (m = 1, 3 to 5). capture according to intp21, intp22 and intcm100, intcm101 is possible for sub-channel 1 and sub-channel 2 of timer 2. examples are shown below. (a) capture sub-channel 1 on intcm101 fem1 register = xxxxxx10b tmic0 register = 00000010b (b) capture sub-channel 2 on intcm101 fem2 register = xxxxxx11b tmic0 register = 00001000b remark n = 0 to 5 712 user?s manual u14492ej4v1ud chapter 15 reset function when a low level is input to the reset pin, there is a system reset and each hardware item of the v850e/ia1 is initialized to its initial status. when the reset pin changes from low level to high level, reset status is released and the cpu starts program execution. initialize the contents of va rious registers as needed within the program. 15.1 features noise elimination using analog delay (approx. 60 ns) in reset pin (reset) 15.2 pin functions during a system reset period, most pin output is high impedance (all pins except clkout note , reset, x2, v dd5 , v ss5 , v dd3 , v ss3 , cv dd , cv ss , av dd , av ref0 , av ref1 , and av ss pins). thus, if for example memory is extended externally, a pu ll-up (or pull-down) resistor must be attached to each pin of ports dh, dl, cs, ct, and cm. if there are no resistors, the external memory that is connected may be destroyed when these pins become high impedance. similarly, perform pin processing so th at on-chip peripheral i/o function signal output and output ports are not affected. note in romless mode 0 or 1 and single-chip mode 1, clkout signals also are output during a reset period. in single-chip mode 0, clkout signals are not output until the pmccm register is set. table 15-1 shows the operation status of each pin during a reset period. table 15-1. operation status of each pin during reset period pin status pin name in single-chip mode 0 in single-chip mode 1 in romless mode 0 in romless mode 1 a16 to a23, ad0 to ad15, cs0 to cs7, lwr, uwr, rd, astb, wait, hldak, hldrq (port mode) high impedance clkout (port mode) operation ports 0 to 4 (input) port pins ports cm, cs, ct, dh, dl (input) (control mode) chapter 15 reset function 713 user?s manual u14492ej4v1ud (1) reset signal acknowledgment reset internal system reset signal elimination as noise reset acknowledgment reset release analog delay analog delay analog delay note note the internal system reset signal continues in active status for a period of at least 4 system clocks after the timing of a reset release by the reset pin. (2) reset at power-on a reset operation at power-on (power supply application) must guarantee oscillation stabilization time from power-on until reset acknowledgment due to the low level width of the reset signal. reset (input) v dd3 , v dd5 reset release analog delay oscillation stabilization time chapter 15 reset function 714 user?s manual u14492ej4v1ud 15.3 initialization initialize the contents of each regi ster as needed within a program. table 15-2 shows the initial val ues of the cpu, internal ram, and on-chip peripheral i/o after reset. table 15-2. initial values of cpu, internal ram, and on-chip periphera l i/o after reset (1/6) on-chip hardware register name initial value after reset general-purpose register (r0) 00000000h general-purpose registers (r1 to r31) undefined program registers program counter (pc) 00000000h status saving register during interrupt (eipc, eipsw) undefined status saving register during nmi (fepc, fepsw) undefined interrupt source register (ecr) 00000000h program status word (psw) 00000020h status saving register during callt execution (ctpc, ctpsw) undefined status saving register during e xception/debug trap (dbpc, dbpsw) undefined cpu system registers callt base pointer (ctbp) undefined internal ram ? undefined chip area selection control register n (cscn) (n = 0, 1) 2c11h peripheral area selection control register (bpc) 0000h bus size configurat ion register (bsc) 0000h/5555h bus control function system wait control register (vswc) 77h bus cycle type configuration regi ster n (bctn) (n = 0, 1) cccch data wait control register n (dwcn) (n = 0, 1) 3333h address wait control register (awc) 0000h memory control function bus cycle control register (bcc) aaaah dma source address register nl (dsanl) (n = 0 to 3) undefined dma source address register nh (dsanh) (n = 0 to 3) undefined dma destination address register nl (ddanl) (n = 0 to 3) undefined dma destination address register nh (ddanh) (n = 0 to 3) undefined dma transfer count register n (dbcn) (n = 0 to 3) undefined dma addressing control register n (dadcn) (n = 0 to 3) 0000h dma channel control register n (dchcn) (n = 0 to 3) 00h dma disable status register (ddis) 00h dma restart register (drst) 00h dma function dma trigger factor register n (dtfrn) (n = 0 to 3) 00h in-service priority register (ispr) 00h external interrupt mode register n (intmn) (n = 0 to 2) 00h interrupt mask register n (imrn) (n = 0 to 3) ffffh interrupt mask register nl (imrnl) (n = 0 to 3) ffh on-chip peripheral i/o interrupt/exception control function interrupt mask register nh (imrnh) (n = 0 to 3) ffh chapter 15 reset function 715 user?s manual u14492ej4v1ud table 15-2. initial values of cpu, internal ram, and on-chip periphera l i/o after reset (2/6) on-chip hardware register name initial value after reset signal edge selection register n (sesa1n) (n = 10, 11) 00h valid edge selection register (sesc) 00h timer 2 input filter mode register n (femn) (n = 0 to 5) 00h interrupt/exception control function interrupt control registers (p0ic0 to p0ic6, detic0, detic1, tm0ic0, cm03ic0, tm0ic1, cm03ic1, cc10ic0, cc10ic1, cm10ic0, cm10ic1, cc11ic0, cc11ic1, cm11ic0, cm11ic1, tm2ic0, tm2ic1, cc2ic0 to cc2ic5, tm3ic0, cc3ic0, cc3ic1, cm4ic0, dmaic0 to dmaic3, canic0 to canic3, csiic0, csiic1, sric0 to sric2, stic0 to stic2, seic0, adic0, adic1) 47h command register (prcmd) undefined power save control register (psc) 00h clock control register (ckc) 00h power save mode register (psmr) 00h power save control function lock register (lockr) 0000000xb peripheral command register (phcmd) undefined system control peripheral status register (phs) 00h dead-time timer reload register n (dtrrn) (n = 0, 1) 0fffh buffer registers cm0n, cm1n (bfcm0n, bfcm1n) (n = 0 to 3) ffffh timer control register 0n (tmc0n) (n = 0, 1) 0508h timer control register 0nl (tmc0nl) (n = 0, 1) 08h timer control register 0nh (tmc0nh) (n = 0, 1) 05h timer unit control register 0n (tuc0n) (n = 0, 1) 01h timer output mode register n (tomrn) (n = 0, 1) 00h pwm software timing output register n (pston) (n = 0, 1) 00h pwm output enable register n (poern) (n = 0, 1) 00h tomr write enable register n (specn) (n = 0, 1) 0000h timer 0 timer 0 clock selection register (prm01) 00h timer 1n (tm1n) (n = 0, 1) 0000h compare register 1n (cm1n) (n = 00, 01, 10, 11) 0000h capture/compare register 1n (cc1n) (n = 00, 01, 10, 11) 0000h capture/compare control register n (ccrn) (n = 0, 1) 00h timer unit mode register n (tumn) (n = 0, 1) 00h timer control register 1n (tmc1n) (n = 0, 1) 00h signal edge selection register 1n (sesa1n) (n = 0, 1) 00h prescaler mode register 1n (prm1n) (n = 0, 1) 07h status register n (statusn) (n = 0, 1) 00h timer connection selection register 0 (tmic0) 00h timer 1/timer 2 clock select ion register (prm02) 00h cc1n1 capture input selection register (csl1n) (n = 0, 1) 00h on-chip peripheral i/o timer 1 timer 1n noise elimination time selecti on register (nrc1n) (n = 0, 1) 00h chapter 15 reset function 716 user?s manual u14492ej4v1ud table 15-2. initial values of cpu, internal ram, and on-chip periphera l i/o after reset (3/6) on-chip hardware register name initial value after reset timer 2 clock stop regi ster 0 (stopte0) 0000h timer 2 clock stop register 0l (stopte0l) 00h timer 2 clock stop register 0h (stopte0h) 00h timer 2 count clock/control edge selection register 0 (cse0) 0000h timer 2 count clock/control edge se lection register 0l (cse0l) 00h timer 2 count clock/control edge selection register 0h (cse0h) 00h timer 2 sub-channel input event edge selection register 0 (sese0) 0000h timer 2 sub-channel input event edge selection register 0l (sese0l) 00h timer 2 sub-channel input event edge selection register 0h (sese0h) 00h timer 2 time base control register 0 (tcre0) 0000h timer 2 time base control register 0l (tcre0l) 00h timer 2 time base control register 0h (tcre0h) 00h timer 2 output control register 0 (octle0) 0000h timer 2 output control register 0l (octle0l) 00h timer 2 output control register 0h (octle0h) 00h timer 2 sub-channel 0, 5 capt ure/compare control register (cmse050) 0000h timer 2 sub-channel 1, 2 capt ure/compare control register (cmse120) 0000h timer 2 sub-channel 3, 4 capt ure/compare control register (cmse340) 0000h timer 2 sub-channel n sub capture/compare register (cvsen0) (n = 1 to 4) 0000h timer 2 sub-channel n main capture/compare register (cvpen0) (n = 1 to 4) 0000h timer 2 sub-channel n capture/compare register (cvsen0) (n = 0, 5) 0000h timer 2 time base status register 0 (tbstate0) 0101h timer 2 time base status register 0l (tbstate0l) 01h timer 2 time base status register 0h (tbstate0h) 01h timer 2 capture/compare 1 to 4 st atus register 0 (ccstate0) 0000h timer 2 capture/compare 1 to 4 status register 0l (ccstate0l) 00h timer 2 capture/compare 1 to 4 status register 0h (ccstate0h) 00h timer 2 output delay register 0 (odele0) 0000h timer 2 output delay register 0l (odele0l) 00h timer 2 output delay register 0h (odele0h) 00h timer 2 timer 2 software event capture register (osce0) 0000h timer 3 (tm3) 0000h capture/compare register 3n (cc3n) (n = 0, 1) 0000h timer control register 30 (tmc30) 00h on-chip peripheral i/o timer 3 timer control register 31 (tmc31) 20h chapter 15 reset function 717 user?s manual u14492ej4v1ud table 15-2. initial values of cpu, internal ram, and on-chip periphera l i/o after reset (4/6) on-chip hardware register name initial value after reset valid edge selection register (sesc) 00h timer 3 clock selection register (prm03) 00h timer 3 timer 3 noise elimination time selection register (nrc3) 00h timer 4 (tm4) 0000h compare register 4 (cm4) 0000h timer 4 timer control register 4 (tmc4) 00h clocked serial interfac e mode register n (csimn) (n = 0, 1) 00h clocked serial interface clock selection register n (csicn) (n = 0, 1) 00h clocked serial interface reception buffer register n (sirbn) (n = 0, 1) 0000h clocked serial interface reception buffer register ln (sirbln) (n = 0, 1) 00h clocked serial interfac e transmission buffer register n (sotbn) (n = 0, 1) 0000h clocked serial interface transmis sion buffer register ln (sotbln) (n = 0, 1) 00h clocked serial interface read- only reception buffer register n (sirben) (n = 0, 1) 0000h clocked serial interface read- only reception buffer register ln (sirbeln) (n = 0, 1) 00h clocked serial interface initia l transmission buffer register n (sotbfn) (n = 0, 1) 0000h clocked serial interface initia l transmission buffer register ln (sotbfln) (n = 0, 1) 00h serial i/o shift register n (sion) (n = 0, 1) 0000h serial i/o shift register ln (sioln) (n = 0, 1) 00h prescaler mode register (prsm3) 00h serial interface function (csi0, csi1) prescaler compare register (prscm3) 00h asynchronous serial interface mode register 0 (asim0) 01h reception buffer register 0 (rxb0) ffh asynchronous serial interface st atus register 0 (asis0) 00h transmission buffer register 0 (txb0) ffh asynchronous serial interface transmis sion status register 0 (asif0) 00h baud rate generator control register 0 (brgc0) ffh serial interface function (uart0) clock selection register 0 (cksr0) 00h asynchronous serial interface mode regi ster n0 (asimn0) (n = 1, 2) 81h asynchronous serial interface mode regi ster n1 (asimn1) (n = 1, 2) 00h asynchronous serial interface status re gister n (asisn) (n = 1, 2) 00h 2-frame continuous reception buffer regi ster n (rxbn) (n = 1, 2) undefined reception buffer register ln (rxbln) (n = 1, 2) undefined on-chip peripheral i/o serial interface function (uart1, uart2) 2-frame continuous transmission shift r egister n (txsn) (n = 1, 2) undefined chapter 15 reset function 718 user?s manual u14492ej4v1ud table 15-2. initial values of cpu, internal ram, and on-chip periphera l i/o after reset (5/6) on-chip hardware register name initial value after reset transmission shift register ln (txsln) (n = 1, 2) undefined prescaler mode register n (prsmn) (n = 1, 2) 00h serial interface function (uart1, uart2) prescaler compare register n (prscmn) (n = 1, 2) 00h can message data length register n (m_dlcn) (n = 00 to 31) undefined can message control register n (m_ctrln) (n = 00 to 31) undefined can message time stamp register n (m_timen) (n = 00 to 31) undefined can message data register nm (m_datanm) (n = 00 to 31, m = 0 to 7) undefined can message id register ln, hn (m_idln, m_idhn) (n = 00 to 31) undefined can message configuration register n (m_confn) (n = 00 to 31) undefined can message status register n (m_statn) (n = 00 to 31) undefined can status set/clear register n (sc_statn) (n = 00 to 31) 0000h can interrupt pending register (ccintp) 0000h can global interrupt pending register (cgintp) 00h can1 interrupt pending register (c1intp) 00h can stop register (cstop) 0000h can global status register (cgst) 0100h can global interrupt enable register (cgie) 0a00h can main clock selection register (cgcs) 7f05h can time stamp count register (cgtsc) 0000h can message search start/result register (cgmss on write; cgmsr on read) 0000h can1 address mask n register l, h (c1maskln, c1maskhn) (n = 0 to 3) undefined can1 control register (c1ctrl) 0101h can1 definition register (c1def) 0000h can1 information register (c1last) 00ffh can1 error count register (c1erc) 0000h can1 interrupt enable register (c1ie) 0900h can1 bus active register (c1ba) 00ffh can1 bit rate prescaler register (c1brp) 0000h can1 bus diagnostic information register (c1dinf) 0000h can1 synchronization contro l register (c1sync) 0218h serial interface function (fcan) fcan clock selection register (prm04) 00h a/d scan mode register n0 (adscmn0) (n = 0, 1) 0000h a/d scan mode register n0l (adscmn0l) (n = 0, 1) 00h a/d scan mode register n0h (adscmn0h) (n = 0, 1) 00h a/d scan mode register n1 (adscmn1) (n = 0, 1) 0000h a/d scan mode register n1l (adscmn1l) (n = 0, 1) 00h on-chip peripheral i/o a/d converter a/d scan mode register n1h (adscmn1h) (n = 0, 1) 00h chapter 15 reset function 719 user?s manual u14492ej4v1ud table 15-2. initial values of cpu, internal ram, and on-chip periphera l i/o after reset (6/6) on-chip hardware register name initial value after reset a/d voltage detection mode register n (adetmn) (n = 0, 1) 0000h a/d voltage detection mode register nl (adetmnl) (n = 0, 1) 00h a/d voltage detection mode register nh (adetmnh) (n = 0, 1) 00h a/d conversion result register 0n (adcr0n) (n = 0 to 7) 0000h a/d conversion result register 1n (adcr1n) (n = 0 to 7) 0000h a/d converter a/d internal trigger selection register (itrg0) 00h ports (p0 to p4, pdh, pcs, pct, pcm) undefined port (pdl) undefined port (pdll) undefined port (pdlh) undefined mode registers (pm1 to pm4, pmdh, pmcs, pmct, pmcm) ffh mode register (pmdl) ffffh mode register (pmdll) ffh mode register (pmdlh) ffh mode control registers (pmc1 to pmc4) 00h mode control registers (pmcdh, pmccs) 00h/ffh mode control register (pmcdl) 0000h/ffffh mode control register (pmcdll) 00h/ffh mode control register (pmcdlh) 00h/ffh mode control register (pmcct) 00h/53h mode control register (pmccm) 00h/0fh port function function control registers (pfc1, pfc2) 00h ram access data buffer register l (nbdl) 0000h ram access data buffer register ll (nbdll) 00h ram access data buffer register lu (nbdlu) 00h ram access data buffer register h (nbdh) 0000h ram access data buffer register hl (nbdhl) 00h ram access data buffer register hu (nbdhu) 00h dma source address setting register sl (nbdmsl) undefined dma source address setting register sh (nbdmsh) undefined dma destination address setting regi ster dl (nbdmdl) undefined nbd function dma destination address setting regi ster dh (nbdmdh) undefined on-chip peripheral i/o flash memory flash programming mode c ontrol register (flpmc) 08h/0ch/00h caution in the table above, ?unde fined? means either undefined at the time of a power-on reset or undefined due to data destruction when reset input and data write ti ming are synchronized. on a reset other than this, data is main tained in its previous status. 720 user?s manual u14492ej4v1ud chapter 16 flash memory ( pd70f3116) the pd70f3116 is the flash memory version of the v850e/ia1 and it has an on-chip 256 kb flash memory configured as two 128 kb areas. caution there are differences in noi se immunity and noise radiation be tween the flash memory and mask rom versions. when pre-producing an applicatio n set with the flash memory version and then mass producing it with the mask rom version, be sure to cond uct sufficient evaluations on the commercial samples (cs) (not engineeri ng samples (es)) of the mask rom versions. writing to a flash memory can be performed with memory mounted on the target system (on board). the dedicated flash programmer is connected to the target system to perform writing. the following can be considered as the development envir onment and the applications using a flash memory. software can be changed after the v850e/ia1 is solder mounted on the target system. small scale production of various models is made easier by differentiating software. data adjustment in starting mass production is made easier. 16.1 features all area batch erase, or erase in area units (128 kb) communication through serial interface from the dedicated flash programmer erase/write voltage: v pp = 7.8 v on-board programming flash memory programming is possible by the self-programming in area units (128 kb) 16.2 writing by flash programmer writing can be performed either on-board or off-board by the dedicated flash programmer. caution when writing data with the flash progra mmer, the operation is always performed at the frequency multiplied by 5 in the pll mode. (1) on-board programming the contents of the flash me mory is rewritten after the v850e/ia1 is mounted on the target system. mount connectors, etc., on the target system to connect the dedicated flash programmer. (2) off-board programming writing to a flash memory is performed by the dedica ted program adapter (fa seri es), etc., before mounting the v850e/ia1 on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. chapter 16 flash memory ( pd70f3116) 721 user?s manual u14492ej4v1ud when the flash programming adapter (f a-144gj-8eu) is used for writing, connect the pins as follows. table 16-1. connection of v850e/ia1 fl ash programming adapter (fa-144gj-8eu) v850e/ia1 uart0 csi0 fa-144gj-8eu silk name pin name pin no. pin name pin no. si txd0/p31 38 so0/p41 30 so rxd0/p30 37 si0/p40 29 sck ? sck0/p42 31 x1 x1 23 note 1 x1 23 note 1 x2 x2 24 note 1 x2 24 note 1 /reset reset 20 reset 20 v pp v pp /ic5 89 v pp /ic5 89 reserve/hs ? a16/pdh0 note 2 73 v dd3 53, 128 v dd3 53, 128 lvdd note 3 cv dd 21 cv dd 21 v dd5 56, 91, 125 v dd5 56, 91, 125 av ref0 137 av ref0 137 av ref1 4 av ref1 4 mode1 27 mode1 27 vdd av dd 2, 135 av dd 2, 135 v ss3 54, 127 v ss3 54, 127 v ss5 55, 90, 126 v ss5 55, 90, 126 av ss 3, 136 av ss 3, 136 cv ss 22 cv ss 22 mode0 26 mode0 26 mode2 28 mode2 28 gnd nmi/p00 111 nmi/p00 111 note 4 cksel 25 cksel 25 notes 1. configure the oscillator on the fa-144gj-8eu board using a resonator and a capacitor. the following figure shows an example of the oscillator. example cv ss x1 x2 2. connection is not required for this pin when not using handshakes. 3. the option of dual-power-supply adapter (f a-tvc) for generating 3.3 v is available. 4. in pll mode: gnd in direct mode: v dd5 remark ? : leave open chapter 16 flash memory ( pd70f3116) 722 user?s manual u14492ej4v1ud 16.3 programming environment the following shows the environment required for writi ng programs to the flash memory of the v850e/ia1. figure 16-1. environment for wr iting program to flash memory v850e/ia1 dedicated flash programmer rs-232c host machine v pp1 v dd v pp v dd3 v dd5 v ss5 v ss3 gnd regulator regulator uart0 csi0 reset pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve usb a host machine is required for controlling the dedicated flash programmer. uart0 or csi0 is used for the inte rface between the dedicated flash programmer and the v850e/ia1 to perform writing, erasing, etc. a dedicated pr ogram adapter (fa series) is required for off-board writing. supply the operating clock of the v850e/ia1 via the oscillator configured on the v850e/ia1 board using a resonator and a capacitor. 16.4 communication mode (1) uart0 transfer rate: 4,800 bps to 76,800 bps (lsb first) figure 16-2. communication with de dicated flash programmer (uart0) v850e/ia1 v pp1 v dd v pp v dd3 v dd5 v ss5 v ss3 gnd reset regulator regulator so si dedicated flash programmer txd0 rxd0 reset pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve caution supply the operating cl ock of the v850e/ia1 via the oscillator configured on the v850e/ia1 board using a resonator and a capacitor. chapter 16 flash memory ( pd70f3116) 723 user?s manual u14492ej4v1ud (2) csi0 transfer rate: up to 2 mhz (msb first) figure 16-3. communication with de dicated flash programmer (csi0) v850e/ia1 reset so si sck dedicated flash programmer sck0 so0 si0 reset v pp1 v dd v pp v dd3 v dd5 v ss5 v ss3 gnd regulator regulator pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y s tat v e caution supply the operating cl ock of the v850e/ia1 via the oscillator configured on the v850e/ia1 board using a resonator and a capacitor. the dedicated flash programmer out puts transfer clocks and the v8 50e/ia1 operates as a slave. (3) handshake-supported csi communication transfer rate: up to 2 mhz (msb first) figure 16-4. communication with dedicated flash programmer (hands hake-supported csi communication) v850e/ia1 dedicated flash programmer reset reset so si so0 si0 pdh0 sck sck0 hs v pp1 v dd v pp v dd3 v dd5 v ss5 v ss3 gnd regulator regulator pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve caution supply the operating cl ock of the v850e/ia1 via the oscillator configured on the v850e/ia1 board using a resonator and a capacitor. chapter 16 flash memory ( pd70f3116) 724 user?s manual u14492ej4v1ud 16.5 pin connection when performing on-board writing, instal l a connector on the target system to connect to the dedicated flash programmer. also, install a function on-board to switch from the normal operation mode (single-chip modes 0, 1 or romless modes 0, 1) to the flash memory programming mode. in the flash memory programming mode, all the pins not used for flash memory programming become the same status as they were immediately after reset in single-chip mode 0. therefore, all t he ports enter the output high- impedance status, so that pin handling is required when th e external device does not acknowledge the output high- impedance status. 16.5.1 v pp pin in the normal operation mode, 0 v is input to the v pp pin. in the flash memory programming mode, 7.8 v writing voltage is supplied to the v pp pin. the following shows an exam ple of the connection of the v pp pin. figure 16-5. connection example of v pp pin v850e/ia1 v pp pull-down resistor (r vpp = 4.7 to 47 k ? ) dedicated flash programmer connection pin 16.5.2 serial interface pin the following shows the pins used by each serial interface. table 16-2. pins used by each serial interface serial interface pins used csi0 so0, si0, sck0 csi0 + hs so0, si0, sck0, pdh0 uart0 txd0, rxd0 when connecting a dedicated flash programmer to a serial interface pin that is connected to other devices on- board, care should be taken to avoid the conflict of signals and the malfunction of other devices, etc. (1) conflict of signals when connecting a dedicated flash programmer (output) to a serial interface pin (input) which is connected to another device (output), a conflict of signals occurs. to av oid the conflict of signals, isolate the connection to the other device or set the other dev ice to the output high-impedance status. chapter 16 flash memory ( pd70f3116) 725 user?s manual u14492ej4v1ud figure 16-6. conflict of signals (serial interface input pin) v850e/ia1 input pin output pin other device dedicated flash programmer connection pin conflict of signals in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs. therefore, isolate the signals on the other device side. (2) malfunction of the other device when connecting a dedicated flash programmer (output or input) to a serial interface pin (input or output) connected to another device (input), the signal output to the other device may cause the device to malfunction. to avoid this, isolate the connection to the other device or make the setting so that the input signal to the other device is ignored. figure 16-7. malfunction of other device v850e/ia1 pin input pin other device dedicated flash programmer connection pin in the flash memory programming mode, if the signal the v850e/ia1 outputs affects the other device, isolate the signal on the other device side. v850e/ia1 pin input pin other device dedicated flash programmer connection pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. chapter 16 flash memory ( pd70f3116) 726 user?s manual u14492ej4v1ud 16.5.3 reset pin when connecting the reset signals of the dedicated flash progr ammer to the reset pin, which is connected, to the reset signal generator on-board, a conflict of signals occurs. to avoid the conflict of signal s, isolate the connection to the reset signal generator. when the reset signal is input from the user system in flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 16-8. conflict of signals (reset pin) v850e/ia1 reset output pin reset signal generator dedicated flash programmer connection pin conflict of signals in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. 16.5.4 nmi pin do not change the input signal to the nmi pin in flash me mory programming mode. if it is changed in flash memory programming mode, programming may not be performed correctly. 16.5.5 mode0 to mode2 pins to shift to the flash memory programming mode, set mode0 to high-level or low-level input, mode1 to high-level input, and mode2 to low-level input, apply the writing voltage (7.8 v) to the v pp pin, and release reset. 16.5.6 port pins when the flash memory programming mode is set, all the port pins except the pins which communicate with the dedicated flash programmer become output high-impedance status. nothing need be done to these port pins. if problems such as disabling output high-im pedance status should occur to the external devices connected to the ports, connect them to v dd5 or v ss5 via resistors. 16.5.7 other signal pins connect x1 and x2 to the same status as in the normal operation mode. the amplitude is 3.3 v. chapter 16 flash memory ( pd70f3116) 727 user?s manual u14492ej4v1ud 16.5.8 power supply supply the power supply (v dd3 , v ss3 , v dd5 , v ss5 , av dd , av ref0 , av ref1 , av ss , cv dd , and cv ss ) the same as in normal operation mode. connect v dd note and gnd of the dedicated flash programmer to v dd3 , v ss3 , v dd5 , and v ss5 (v dd of the dedicated flash programmer is provided with a power supply monitoring function). note connect v dd after converting the power supply to 3.3 v using a regulator. 16.6 programming method 16.6.1 flash memory control the following shows the procedure for manipulating the flash memory. figure 16-9. flash memory manipulating procedure start switch to flash memory programming mode supply reset pulse select communication mode manipulate flash memory end? end no yes chapter 16 flash memory ( pd70f3116) 728 user?s manual u14492ej4v1ud 16.6.2 flash memory programming mode when rewriting the contents of flash memory using the dedi cated flash programmer, set the v850e/ia1 in the flash memory programming mode. to switch to this mode, set the mode0, mode1, mode2, and v pp pins before canceling reset. when performing on-board writing, cha nge modes using a jumper, etc. ? mode0: high-level or low-level input ? mode1: high-level input ? mode2: low-level input ? v pp : 7.8 v figure 16-10. flash memory programming mode ... n 1 flash memory programming mode mode0 to mode2 010 011 7.8 v v pp 3.3 v 0 v reset 2 16.6.3 selection of communication mode in the v850e/ia1, a communication mode is selected by inputting pulses (16 pulses max.) to v pp pin after switching to the flash memory programming mode. the v pp pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. table 16-3. list of communication mode v pp pulse communication mode remarks 0 csi0 3 handshake-supported csi v850e/ia1 performs slave operation, msb first 8 uart0 communication rate: 9600 bps (after reset), lsb first others rfu (reserved) setting prohibited chapter 16 flash memory ( pd70f3116) 729 user?s manual u14492ej4v1ud 16.6.4 communication commands the v850e/ia1 communicates with the dedicated flash programmer by means of commands. a command sent from the dedicated flash programmer to the v850e/ia1 is called a ?command?. the response signal sent from the v850e/ia1 to the dedicated flash programmer is called the ?response command?. figure 16-11. communication commands v850e/ia1 dedicated flash programmer command response command pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve the following shows the commands for controlling flash me mory of the v850e/ia1. all of these commands are issued from the dedicated flash programmer, and the v850 e/ia1 performs the various processing corresponding to the commands. table 16-4. commands for controlling flash memory category command name function batch verify command compares the contents of the entire memory and the input data. verify area verify command compares the contents of the specified area and the input data. batch erase command erases the c ontents of the entire memory. area erase command erases the contents of the specified area. erase write back command writes back the contents which were erased. batch blank check command checks the erase state of the entire memory. blank check area blank check command checks the erase state of the specified area. high-speed write command writes data by the specification of the write address and the number of bytes to be written, and executes verify check. data write continuous write command writes data from the address following the high- speed write command executed immediately before, and executes verify check. status read out command acquires the status of operations. oscillation frequency setting command sets the oscillation frequency. erasing time setting command sets the erasing time of batch erase. writing time setting command sets the writing time of data write. write back time setting command sets the write back time. silicon signature command reads outs the silicon signature information. system setting and control reset command escapes from each state. chapter 16 flash memory ( pd70f3116) 730 user?s manual u14492ej4v1ud the v850e/ia1 sends back response commands for the co mmands issued from the dedicated flash programmer. the following shows the response commands the v850e/ia1 sends out. table 16-5. response commands response command name function ack (acknowledge) acknowledges command/data, etc. nak (not acknowledge) acknowledges illegal command/data, etc. 16.7 flash memory programming by self-programming the pd70f3116 supports a self-programming function to rewr ite the flash memory using a user program. by using this function, the flash memory can be rewritten with a user application. this se lf-programming function can be also used to upgrade the program in the field. 16.7.1 outline of self-programming self-programming implements erasure and writing of the flash memory by calling the self-programming function (device?s internal processi ng) on the program placed in the block 0 space (000000h to 1fffffh) and areas other than internal rom area. to place the program in the bl ock 0 space and internal rom area, copy the program to areas other than 000000h to 1fffffh (e.g. internal ram area) and execute the program to call the self- programming function. to call the self-programming function, change the operating mode from normal operation mode to self- programming mode using the flash programmi ng mode control register (flpmc). figure 16-12. outline of self-programming 256 kb flash memory 00000h 3ffffh erase area note (128 kb) erase area note (128 kb) flash memory normal operation mode self-programming mode 00000h 3ffffh flpmc 02h flpmc 00h self-programming function (erase/write routine incorporated) note data is erased in area units (128 kb). chapter 16 flash memory ( pd70f3116) 731 user?s manual u14492ej4v1ud 16.7.2 self-programming function the pd70f3116 provides self-programming functions, as s hown in table 16-6. by combining these functions, erasing/writing flash memory becomes possible. table 16-6. function list type function name function erase area erase erases the specified area. continuous write in word units continuously writes the specified memory contents from the specified flash memory address, for the number of words specified in 4-byte units. write pre-write writes 0 to flash memory before erasure. erase verify checks whether an ov er erase occurred after erasure. erase byte verify checks whether erasure is complete. check internal verify checks whether the signal level of the post-write data in flash memory is appropriate. write back area write back writes back th e flash memory area in which an over erase occurred. acquire information flash memory information read reads out information about flash memory. 16.7.3 outline of sel f-programming interface to execute self-programming using t he self-programming interface, the envi ronmental conditions of the hardware and software for manipulating the flash memory must be satisfied. it is assumed that the self-programming interface is used in an assembly language. (1) entry program this program is to call the inter nal processing of the device. it is a part of the application program, and must be executed in memory other than the block 0 space and internal rom area (flash memory). (2) device internal processing this is manipulation of the flash memory executed inside the device. this processing manipulates the flash memory after it has been called by the entry program. (3) ram parameter this is a ram area to which the parameters necessary for self-programming, such as write time and erase time, are written. it is set by the application pr ogram and referenced by the device internal processing. chapter 16 flash memory ( pd70f3116) 732 user?s manual u14492ej4v1ud the self-programming interface is outlined below. figure 16-13. outline of self-programming interface application program entry program ram parameter device internal processing flash memory self-programming interface flash-memory manipulation 16.7.4 hardware environment to write or erase the flash memory, a high voltage must be applied to the v pp pin. to execute self-programming, a circuit that can generate a write voltage (v pp ) and that can be controlled by software is necessary on the application system. an example of a circuit that can select a voltage to be applied to the v pp pin by manipulating a port is shown below. figure 16-14. example of self-p rogramming circuit configuration v dd = 3.3 v 0.3 v pd70f3116 v dd5 , av dd v ss3 , v ss5 , cv ss v pp output port ic for power supply output input on/off v ss 10 k ? 10 k ? v in v pp = 7.8 v 0.3 v v dd3 , cv ss v dd = 5.0 v 0.5 v chapter 16 flash memory ( pd70f3116) 733 user?s manual u14492ej4v1ud the voltage applied to the v pp pin must satisfy the following conditions: ? hold the voltage applied to the v pp pin at 0 v in the normal operation mode and hold the v pp voltage only while the flash memory is being manipulated. ? the v pp voltage must be stable from before manipulation of the flash memory star ts until manipulation is complete. cautions 1. apply 0 v to the v pp pin when reset is released. 2. implement self-programming in single-chip mode 0 or 1. 3. apply the voltage to the v pp pin in the entry program. 4. if both writing and erasing are executed by using the self-programming function and flash memory programmer on the target board, be sure to communicate with the programmer using csi0 (do not use the handshake-supported csi). figure 16-15. timing to apply voltage to v pp pin flash memory manipulation reset signal v pp signal v pp 0 v v dd3 or v dd5 0 v chapter 16 flash memory ( pd70f3116) 734 user?s manual u14492ej4v1ud 16.7.5 software environment the following conditions must be satisfie d before using the entry program to call the device internal processing. table 16-7. software en vironmental conditions item description location of entry program execute the entry program in memory other than the block 0 space and flash memory area. the device internal processing cannot be directly ca lled by the program that is executed on the flash memory. execution status of program the device internal processing cannot be called while an interrupt is being serviced (np bit of psw = 0, id bit of psw = 1). masking interrupts mask all the maskable interrupts used. mask each interrupt by using the corresponding interrupt control register. to mask a maskable interrupt, be sure to specif y masking by using the corresponding interrupt control register. mask the maskable interrupt ev en when the id bit of the psw = 1 (interrupts are disabled). manipulation of v pp voltage stabilize the voltage applied to the v pp pin (v pp voltage) before starting manipulation of the flash memory. after completion of the manipulation, return the voltage of the v pp pin to 0 v. initialization of internal timer do not use the internal timer while the flash memory is being manipulated. because the internal timer is initialized after the fl ash memory has been used, initialize the timer with the application program to use the timer again. stopping reset signal input do not input the reset signal while t he flash memory is being manipulated. if the reset signal is input while the flash memory is being manipulated, the contents of the flash memory under manipulation become undefined. stopping nmi signal input do not input the nmi signal while the flash memory is being manipulated. if the nmi signal is input while the flash memory is being manipulated, the flash memory may not be correctly manipulated by the device internal processing. if an nmi occurs while the device internal processing is in progress, the occurrence of the nmi is reflected in the nmi flag of the ram parameter. if manipulation of the flash memory is affected by the occurrence of the nmi, the function of each self-programming function is reflected in the return value. reserving stack area the device internal processing takes over the stack used by t he user program. it is necessary that an area of 300 bytes be reserved for the stack size of the user program when the device internal processing is called. r3 is used as the stack pointer. saving general-purpose registers the device internal processing rewrites the co ntents of r6 to r14, r20, and r31 (lp). save and restore these register contents as necessary. chapter 16 flash memory ( pd70f3116) 735 user?s manual u14492ej4v1ud 16.7.6 self-programming function number to identify a self-programming function, the following numbers are assigned to the respective functions. these function numbers are used as parameters when the device internal processing is called. table 16-8. self-programming function number function no. function name 0 acquiring flash information 1 erasing area 2 to 4 rfu 5 area write back 6 to 8 rfu 9 erase byte verify 10 erase verify 11 to 15 rfu 16 continuous write in word units 17 to 19 rfu 20 pre-write 21 internal verify other prohibited remark rfu: reserved for future use chapter 16 flash memory ( pd70f3116) 736 user?s manual u14492ej4v1ud 16.7.7 calling parameters the arguments used to call the self-programming function are shown in the table below. in addition to these arguments, parameters such as the write time and erase ti me are set to the ram parameters indicated by ep (r30). table 16-9. calling parameters function name first argument (r6) function no. second argument (r7) third argument (r8) fourth argument (r9) return value (r10) acquiring flash information 0 option number note 1 ? ? note 1 erasing area 1 area erase start address ? ? 0: normal completion other than 0: error area write back 5 none (acts on erase manipulation area immediately before) ? ? none erase byte verify 9 verify star t address number of bytes to be verified ? 0: normal completion other than 0: error erase verify 10 none (acts on erase manipulation area immediately before) ? ? 0: normal completion other than 0: error continuous write in word units note 2 16 write start address note 3 start address of write source data note 3 number of words to be written (word units) 0: normal completion other than 0: error pre-write 20 write start address number of bytes to be written ? 0: normal completion other than 0: error internal verify 21 verify star t address number of bytes to be verified ? 0: normal completion other than 0: error notes 1. see 16.7.10 flash information for details. 2. prepare write source data in memory other than the flash memory when data is written continuously in word units. 3. this address must be at a 4-byte boundary. caution for all the functions, ep (r30) must in dicate the first address of the ram parameter. chapter 16 flash memory ( pd70f3116) 737 user?s manual u14492ej4v1ud 16.7.8 contents of ram parameters reserve the following 48-byte area in the internal ram or external ram for the ram parameters, and set the parameters to be input. set the base addresses of these parameters to ep (r30). table 16-10. description of ram parameter address size i/o description ep+0 4 bytes ? for internal operations ep+4:bit 5 note 1 1 bit input operation flag (be sure to set this fl ag to 1 before calling the device internal processing.) 0: normal operation in progress 1: self-programming in progress ep+4:bit 7 notes 2, 3 1 bit output nmi flag 0: nmi not detected 1: nmi detected ep+8 4 bytes input erase time (unsigned 4 bytes) expressed as 1 count value in units of the internal operation unit time (100 s). set value = erase time ( s)/internal operation unit time ( s) example: if erase time is 0.4 s 0.4 1,000,000/100 = 4,000 (integer operation) ep+0xc 4 bytes input write bac k time (unsigned 4 bytes) expressed as 1 count value in units of the internal operation unit time (100 s). set value = write back time ( s)/internal operation unit time ( s) example: if write back time is 1 ms 1 1,000/100 = 10 (integer operation) ep+0x10 2 bytes input timer set value for creating internal operation unit time (unsigned 2 bytes) write a set value that makes the value of timer 4 the internal operation unit time (100 s). set value = operating frequency (hz)/1,000,000 internal operation unit time ( s)/ timer division ratio (4) + 1 note 4 example: if the operating frequency is 50 mhz 50,000,000/1,000,000 100/4 + 1 = 1,251 (integer operation) ep+0x12 2 bytes input timer set value for creating write time (unsigned 2 bytes) write a set value that makes the value of timer 4 the write time. set value = operating frequency (hz)/write time ( s)/timer division ratio (4) + 1 note 4 example: if the operating frequency is 50 mhz and the write time is 20 s 50,000,000/1,000,000 20/4 + 1 = 251 (integer operation) ep+0x14 28 bytes ? for internal operations notes 1. fifth bit of address of ep+4 (least significant bit is bit 0.) 2. seventh bit of address of ep+4 (least significant bit is bit 0.) 3. clear the nmi flag by the user program because it is not cleared by the device internal processing. 4. the device internal processing sets this value minus 1 to the timer. because th e fraction is rounded up, add 1 as indicated by the ex pression of the set value. caution be sure to reserve the ram parameter area at a 4-byte boundary. chapter 16 flash memory ( pd70f3116) 738 user?s manual u14492ej4v1ud 16.7.9 errors during self-programming the following errors related to manipulation of the flas h memory may occur during self-programming. an error occurs if the return value (r10) of each function is not 0. table 16-11. errors during self-programming error function description overerase error erase verify excessive erasure occurs. undererase error (blank check error) erase byte verify erasure is insuffic ient. additional erase operation is needed. verify error continuous write in word units the written data cannot be correctly read. either an attempt has been made to write to flash memory that has not been erased, or writing is not sufficient. internal verify error internal verify the wr itten data is not at the correct signal level. caution the overerase error and undererase error may simultaneously occur in the entire flash memory. 16.7.10 flash information for the flash information acquisition function (function no. 0), the option number (r7) to be specified and the contents of the return value (r10) are as follows. to acqui re all flash information, call the function as many times as required in accordance with the format shown below. table 16-12. flash information option no. (r7) return value (r10) 0 specification prohibited 1 specification prohibited 2 bit representation of return value (msb: bi t 31) fffffffffff fffffaaaaaaaaffffffff (lsb: bit 0) bits 31 to 16: ffffffffffffffff (reserved for future use) mask bits 31 to 16 because they are not normally 0. bits 15 to 8: aaaaaaaa (number of areas) (unsigned 8 bits) bits 7 to 0: ffffffff (reserved for future use) mask bits 7 to 0 because they are not normally 0. 3+0 end address of area 0 3+1 end address of area 1 cautions 1. the start address of area 0 is 0. the ?end address + 1? of the preceding area is the start address of the next area. 2. the flash information acquisition functi on does not check values su ch as the maximum number of areas specified by the argument of an option. if an illegal value is specified, an undefined value is returned. chapter 16 flash memory ( pd70f3116) 739 user?s manual u14492ej4v1ud 16.7.11 area number the area numbers and memory map of the pd70f3116 are shown below. figure 16-16. area configuration area 1 (128 kb) area 0 (128 kb) 0 x 3 f f f f (end address of area 1) 0 x 0 0 0 0 0 (start address of area 0) 0 x 2 0 0 0 0 (start address of area 1) 0 x 1 f f f f (end address of area 0) chapter 16 flash memory ( pd70f3116) 740 user?s manual u14492ej4v1ud 16.7.12 flash programming mode control register (flpmc) the flash programming mode control regist er (flpmc) is a register used to en able/disable writing to flash memory and to specify the self-programming mode. this register can be read/written in 8-bit or 1- bit units (the vpp bit (bit 2) is read-only). cautions 1. be sure to transfer control to th e internal ram or external memory beforehand to manipulate the flspm bit. however, in on- board programming mode set by the flash programmer, the specification of flspm bit is ignored. 2. do not change the initial value of bits 0 and 4 to 7. flpmc address fffff8d4h initial value note 08h/0ch/00h 7 6 5 4 <3> <2> <1> 0 0 flspm vpp vppdis 0 0 0 0 note 08h: when writing voltage is not applied to the v pp pin 0ch: when writing voltage is applied to the v pp pin 00h: product not provided with flash memory ( pd703116) bit position bit name function 3 vppdis enables/disables writing/erasing on-chip flash memory. when this bit is 1, writing/erasing on-chip flash memory is disabled even if a high voltage is applied to the v pp pin. 0: enables writing/erasing flash memory 1: disables writing/erasing flash memory 2 vpp indicates the voltage applied to the v pp pin reaches the writing-enabled level (read- only). this bit is used to check whether writing is possible or not in the self- programming mode. 0: indicates high-voltage application to v pp pin is not detected (the voltage has not reached the writing voltage enable level) 1: indicates high-voltage application to v pp pin is detected (the voltage has reached the writing voltage enable level) 1 flspm controls switching between internal rom and the self-programming interface. this bit can switch the mode between the normal mode set by the mode pin on the application system and the self-programming mo de. the setting of this bit is valid only if the voltage applied to the v pp pin reaches the writing voltage enable level. 0: normal mode (for all addresses, instruction fetch is performed from on-chip flash memory) 1: self-programming mode (device internal processing is started) chapter 16 flash memory ( pd70f3116) 741 user?s manual u14492ej4v1ud setting data to the flash programming mode control regist er (flpmc) is performed in the following sequence. <1> disable interrupts (set the np bit and id bit of the psw to 1). <2> prepare the data to be set in the specif ic register in a general-purpose register. <3> write data to the peripheral command register (phcmd). <4> set the flash programming mode control register (flpmc) by executing the following instructions. ? store instruction (st/sst instructions) ? bit manipulation instruction (set1/clr1/not1 instructions) <5> insert nop instructions (5 instructions (<5> to <9>)). <10> cancel the interrupt disabled stat e (reset the np bit of the psw to 0). [description example] <1> ldsr rx, 5 <2> mov 0x02, r10 <3> st.b r10, phcmd[r0] <4> st.b r10, flpmc[r0] <5> nop <6> nop <7> nop <8> nop <9> nop <10> ldsr ry, 5 remark rx: value written to the psw ry: value returned to the psw no special sequence is required for reading a specific register. cautions 1. if an interrupt is acknowledged between when phcmd is issued (<3>) and writing to a specific register (<4>) immediat ely after issuing phcmd, writi ng to the specific register may not be performed and a protection error may occu r (the prerr bit of the phs register = 1). therefore, set the np bit of the psw to 1 (<1>) to disable interrupt acknowledgement. similarly, disable acknowledgement of interr upts when a bit manipulation instruction is used to set a specific register. 2. use the same general-purpose register used to set a specific register (<3>) for writing to the phcmd register (<4>) even though the data wri tten to the phcmd register is dummy data. this is the same as when a general-purpo se register is used for addressing. 3. before executing this processing, complete all dma transfer operations. chapter 16 flash memory ( pd70f3116) 742 user?s manual u14492ej4v1ud 16.7.13 calling device internal processing this section explains the procedure to call the dev ice internal processing from the entry program. before calling the device internal processing, make sure that all the conditions of the hardware and software environments are satisfied and that the necessary argum ents and ram parameters have been set. call the device internal processing by setting the flspm bit of the flas h programming mode control register (flpmc) to 1 and then executing the trap 0x1f instruction. th e processing is always called using the same procedure. it is assumed that the program of this interface is described in an assembly language. <1> set the flpmc register as follows: ? vppdis bit = 0 (to enable writing/erasing flash memory) ? flspm bit = 1 (to select self-programming mode) <2> clear the np bit of the psw to 0 (to enable nmis (only when nmis are used on the application)). <3> execute trap 0x1f to transfer the cont rol to the device?s internal processing. <4> set the np bit and id bit of the psw to 1 (to disable all interrupts). <5> set the value to the peripheral command register (phcmd) that is to be set to the flpmc register. <6> set the flpmc register as follows: ? vppdis bit = 1 (to disable writing/erasing flash memory) ? flspm bit = 0 (to select normal operation mode) <7> wait for the internal manipulation setup time (see 16.7.13 (5) internal ma nipulation setup parameter ). (1) parameter r6: first argument (sets a self-programming function number) r7: second argument r8: third argument r9: fourth argument ep: first address of ram parameter (2) return value r10: return value (return value from device internal processing of 4 bytes) ep+4:bit 7: nmi flag (flag indicating whether an nmi occurred while the device internal processing was being executed) 0: nmi did not occur while device internal processing was being executed. 1: nmi occurred while device internal processing was being executed. if an nmi occurs while control is being transfe rred to the device internal processing, the nmi request may never be reflected. because the nmi flag is not internally reset, this bit must be cleared before calling the device internal processi ng. after the control returns from the device internal processing, nmi dummy processing can be executed by checking the status of this flag using software. (3) description transfer control to the device internal processing specif ied by a function number using the trap instruction. to do this, the hardware and software environmental conditi ons must be satisfied. even if trap 0x1f is used in the user application program, trap 0x1f is treated as another operation afte r the flpmc register has been set. therefore, use of the tr ap instruction is not rest ricted on the application. chapter 16 flash memory ( pd70f3116) 743 user?s manual u14492ej4v1ud (4) program example an example of a program in which the entry program is executed as a subroutine is shown below. in this example, the return address is saved to the stack and then the device internal processing is called. this program must be located in memory other th an the block 0 space and flash memory area. isetup 130 -- internal manipulation setup parameter entryprogram: add -4, sp -- prepare st.w lp, 0[sp] -- save return address movea lo(0x00a0), r0, r10 -- ldsr r10, 5 -- psw = np, id mov lo(0x0002), r10 -- st.b r10, phcmd[r0] -- phcmd = 2 st.b r10, flpmc[r0] -- vppdis = 0, flspm = 1 nop nop nop nop nop movea lo(0x0020), r0, r10 -- ldsr r10, 5 -- psw = id trap 0x1f -- device internal process movea lo(0x00a0), r0, r6 -- ldsr r6, 5 -- psw = np, id mov lo(0x08), r6 st.b r6, phcmd[r0] -- phcmd = 8 st.b r6, flpmc[r0] -- vppdis = 1, flspm = 0 nop nop nop nop nop mov isetup, lp -- loop time = 130 loop: divh r6, r6 -- to kill time add -1, lp -- decrement counter jne loop -- ld.w 0[sp], lp -- reload lp add 4, sp -- dispose jmp [lp] -- return to caller chapter 16 flash memory ( pd70f3116) 744 user?s manual u14492ej4v1ud (5) internal manipulation setup parameter if the self-programming mode is switch ed to the normal operation mode, the pd70f3116 must wait for 100 s before it accesses the flash memory. in the program exam ple in (4) above, the elapse of this wait time is ensured by setting isetup to ?130? (@ 50 mhz operatio n). the total number of execution clocks in this example is 39 clocks (divh instruction (35 clocks) + add instruction (1 clo ck) + jne instruction (3 clocks)). ensure that a wait time of 100 s elapses by using the following expression. 39 clocks (total number of execution clocks) 20 ns (@ 50 mhz operation) 130 (isetup) = 101.4 s (wait time) chapter 16 flash memory ( pd70f3116) 745 user?s manual u14492ej4v1ud 16.7.14 erasing flash memory flow the procedure to erase the flash memory is illustrated bel ow. the processing of each function number must be executed in accordance with the specified calling procedure. figure 16-17. erasing flash memory flow ... function no. 20 ... function no. 1 ... function no. 9 ... function no. 10 ... function no. 5 ... function no. 10 ... function no. 9 erase write error undererase error set ram parameter. mask interrupts. pre-write erase area erase byte verify erase verify area write back erase verify clear number of times write-back is repeated. erase byte verify write error? undererase? maximum number of times of repeating erasure is exceeded? maximum number of times of repeating write-back is exceeded? overerase? overerase? undererase? set v pp voltage. clear v pp voltage. unmask interrupts. clear v pp voltage. unmask interrupts. normal completion clear v pp voltage. unmask interrupts. overerase error clear v pp voltage. unmask interrupts. normal completion clear v pp voltage. unmask interrupts. yes yes yes yes no no no yes no no no yes no yes chapter 16 flash memory ( pd70f3116) 746 user?s manual u14492ej4v1ud 16.7.15 continuous writing flow the procedure to write data all at once to the flash memory by using the fu nction to continuously write data in word units is illustrated below. the processing of each functi on number must be executed in accordance with the specified calling procedure. figure 16-18. continuous writing flow ... function no. 16 yes no continuous writing mask interrupts. set v pp voltage. continuous writing error? clear v pp voltage. unmask interrupts. write error clear v pp voltage. unmask interrupts. normal completion set ram parameter. chapter 16 flash memory ( pd70f3116) 747 user?s manual u14492ej4v1ud 16.7.16 internal verify flow the procedure of internal verificati on is illustrated below. the processing of each function number must be executed in accordance with the specified calling procedure. figure 16-19. internal verify flow ... function no. 21 yes no internal verify mask interrupts. set v pp voltage. internal verify error? clear v pp voltage. unmask interrupts. internal verify error clear v pp voltage. unmask interrupts. normal completion set ram parameter. chapter 16 flash memory ( pd70f3116) 748 user?s manual u14492ej4v1ud 16.7.17 acquiring flash information flow the procedure to acquire the flash info rmation is illustrated below. the proce ssing of each function number must be executed in accordance with t he specified calling procedure. figure 16-20. acquiring flash information flow ... function no. 0 acquiring flash information mask interrupts. set v pp voltage. acquiring flash information clear v pp voltage. unmask interrupts. end set ram parameter. chapter 16 flash memory ( pd70f3116) 749 user?s manual u14492ej4v1ud 16.7.18 self-programming library v850 series flash memory self-programming user?s manual is available for reference when executing self- programming. in this manual, the library uses the self-programming inte rface of the v850 series and can be used in c as a utility and as part of the application program . to use the library, thoroughly evaluate it on the application system. (1) functional outline figure 16-21 outlines the function of the self-programming library. in this figure, a rewriting module is located in area 0 and the data in area 1 is rewritten or erased. the rewriting module is a user program to rewrite the flash memory. the other areas can be also rewritten by using the flash functions included in this self-progr amming library. the flash functions expand the entry program in the external memory or internal ram and call the device internal processing. when using the self-programming library, make sure that the hardware conditions, such as the write voltage, and the software conditions, such as interrupts, are satisfied. figure 16-21. functional outlin e of self-programming library rewriting module flash rewriting program self-programming library flash function flash environment erase/write flash memory rewriting module area 1 area 0 chapter 16 flash memory ( pd70f3116) 750 user?s manual u14492ej4v1ud the configuration of the self-programming library is outlined below. figure 16-22. outline of self-p rogramming library configuration application program entry program ram parameter device internal processing flash memory self-programming interface self-programming library flash memory manipulation c interface chapter 16 flash memory ( pd70f3116) 751 user?s manual u14492ej4v1ud 16.8 how to distinguish flash memory and mask rom versions it is possible to distinguish a flash memory version ( pd70f3116) and a mask rom version ( pd703116) by means of software, using the methods shown below. <1> disable interrupts (set the np bit of psw to 1). <2> write data to the peripheral command register (phcmd). <3> set the vppdis bit of the flash progra mming mode control register (flpmc) to 1. <4> insert nop instructions (5 instructions (<4> to <8>)). <9> cancel the interrupt disabled state (reset the np bit of the psw to 0). <10> read the vppdis bit of the flash prog ramming mode control register (flpmc). ? if the value read is 0: mask rom version ( pd703116) ? if the value read is 1: flash memory version ( pd70f3116) [description example] <1> ldsr rx, 5 <2> st.b r10, phcmd[r0] <3> set1 3, flpmc[r0] <4> nop <5> nop <6> nop <7> nop <8> nop <9> ldsr ry, 5 <10> tst1 3, flpmc[r0] bnz 752 user?s manual u14492ej4v1ud chapter 17 turning on/off power the v850e/ia1 has three types of power supply pins : 3.3 v power supply pins for internal units (v dd3 and cv dd ), 5 v power supply pins for external pins (v dd5 and av dd ), and a flash programming power supply pin (v pp ) note . this chapter explains the i/o pin st atus when power is turned on/off. note pd70f3116 only [recommended timing of turning on/off power] ? to turn on keep the voltage on the v dd5 and av dd pins at 0 v until the voltage on the v dd3 pin rises to the level at which the operation is guaranteed (3.0 to 3.6 v). ? to turn off keep the voltage on the v dd3 pin at the level at which the operation is guaranteed (3.0 to 3.6 v), until the voltage on the v dd5 and av dd pins has dropped to 0 v. ? when releasing reset status by reset pin release the reset status by the reset pin after both t he 3.3 v power supply and 5 v power supply have risen. figure 17-1. recommended timing of turning on/off power depends on program setting i/o pin v dd3 v dd5 , av dd 0 v 3.0 v 4.5 v 3.0 v 4.5 v 0 v 0 v 0 v reset (input) remark the broken line indicate s a high-impedance state. chapter 17 turning on/off power 753 user?s manual u14492ej4v1ud [other timing] ? if power is supplied to the v dd5 and av dd pins before the voltage on the v dd3 pins rises to the level at which the operation is guaranteed (3.0 to 3.6 v), the status of the i/o pin is undefined note until the voltage on the v dd3 pin reaches 3.0 v. ? if the voltage on the v dd3 pin drops below the level at which the operat ion is guaranteed (3.0 to 3.6 v) before the voltage on the v dd5 and av dd pins drops to 0 v, the stat us of the i/o pin is undefined note . note this means that the input or out put mode of an i/o pin, or the outpu t level of an out put pin is not determined. figure 17-2. other timing depends on program setting undefined i/o pin v dd3 v dd5 , av dd 0 v 0 v 0 v 0 v reset (input) undefined 3.0 v 4.5 v 3.0 v 4.5 v remark the broken line indicate s a high-impedance state. 754 user?s manual u14492ej4v1ud chapter 18 electrical specifications 18.1 normal operation mode absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd3 v dd3 pin ? 0.5 to +4.6 v v dd5 v dd5 pin ? 0.5 to +7.0 v cv dd cv dd pin ? 0.5 to +4.6 v cv ss cv ss pin ? 0.5 to +0.5 v av dd av dd pin ? 0.5 to v dd5 + 0.5 note 1 v power supply voltage av ss av ss pin ? 0.5 to +0.5 v v i1 other than x1 pin and pins for nbd note 2 ? 0.5 to v dd5 + 0.5 note 1 v v i2 v pp pin, pd70f3116 note 3 ? 0.5 to +8.5 v v i3 pins for nbd note 2 ? 0.5 to v dd3 + 0.5 note 1 v input voltage v i4 reset pin (when v dd3 is supplied) ? 0.5 to +6.0 v clock input voltage v k x1 pin ? 0.5 to v dd3 + 1.0 note 1 v av dd > v dd5 ? 0.5 to v dd5 + 0.5 note 1 v analog input voltage v ian ani00 to ani07 pins, ani10 to ani17 pins v dd5 av dd ? 0.5 to av dd + 0.5 note 1 v av dd > v dd5 ? 0.5 to v dd5 + 0.5 note 1 v analog reference input voltage av ref av ref0 pin, av ref1 pin v dd5 av dd ? 0.5 to av dd + 0.5 note 1 v per pin for to000 to to005 and to010 to to015 pins 15 ma per pin other than for to000 to to005 and to010 to to015 pins 4.0 ma output current, low i ol total for all pins 210 ma per pin ? 4.0 ma output current, high i oh total for all pins ? 100 ma pd703116, 703116(a), pd70f3116, 70f3116(a) ? 40 to +85 c operating ambient temperature t a pd703116(a1), 70f3116(a1) ? 40 to +110 c storage temperature t stg ? 65 to +150 c chapter 18 electrical specifications 755 user?s manual u14492ej4v1ud notes 1. be sure not to exceed the absolute maximum rati ngs (max. value) of each power supply voltage. 2. clk_dbg, sync, ad0_dbg to ad3_dbg pins ( pd70f3116 only) 3. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when power supply voltage rises v pp must exceed v dd3 and v dd5 10 s or more after v dd3 and v dd5 have reached the lower-limit value (v dd3 : 3.0 v, v dd5 : 4.5 v) of the operating voltage range (see a in the figure below). ? when power supply voltage drops v dd3 and v dd5 must be lowered 10 s or more after v pp falls below the lower-limit value (v dd3 : 3.0 v, v dd5 : 4.5 v) of the operati ng voltage range of v dd3 and v dd5 (see b in the figure below). 0 v 0 v 4.5 v 4.5 v v pp v dd3 v dd5 v pp 0 v 3.0 v 3.0 v a ab b cautions 1. do not directly connect output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open drain pins or open collector pins , however, can be directly connected to each other. direct connection of the output pins be tween an ic product and an external circuit is possible, if the output pins can be set to th e high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute ma ximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are ra ted values at which the product is on the verge of suffering ph ysical damage, and therefore th e product must be used under conditions that ensure that the absolu te maximum ratings are not exceeded. the ratings and conditions shown below for dc characteristics and ac characteristics are within the range for normal ope ration and quality assurance. chapter 18 electrical specifications 756 user?s manual u14492ej4v1ud capacitance (t a = 25 c, v dd3 = v dd5 = v ss3 = v ss5 = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v. 15 pf operating conditions power supply voltage operation mode internal system clock frequency (f xx ) operating ambient temperature (t a ) v dd3 v dd5 pd703116, 703116(a), 70f3116, 70f3116(a) 4 to 25 mhz ? 40 to +85 c 3.3 v 0.3 v 5.0 v 0.5 v direct mode pd703116(a1), 70f3116(a1) 4 to 16 mhz ? 40 to +110 c 3.3 v 0.3 v 5.0 v 0.5 v pd703116, 703116(a), 70f3116, 70f3116(a) 4 to 50 mhz ? 40 to +85 c 3.3 v 0.3 v 5.0 v 0.5 v pll mode pd703116(a1), 70f3116(a1) 4 to 32 mhz ? 40 to +110 c 3.3 v 0.3 v 5.0 v 0.5 v caution when interfacing to the external devices using the clkout signal, make the internal system clock frequency (f xx ) 32 mhz or lower. chapter 18 electrical specifications 757 user?s manual u14492ej4v1ud clock oscillator characteristics (t a = ? 40 to +85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ? 40 to +110 c: pd703116(a1), 70f3116(a1)) (a) ceramic resonator or crystal resonator connection parameter symbol conditions min. typ. max. unit oscillation frequency f x 4 6.4 mhz remarks 1. connect the oscillator as close to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. for the resonator selection and oscillator const ant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (b) external clock input cautions 1. connect the high-speed cmos inverter as closely to the x1 pin as possible. 2. thoroughly evaluate th e matching between the v850e/ia1 and the high-speed cmos inverter. open external clock high-speed cmos inverter x2 x1 x2 x1 c1 c2 r d chapter 18 electrical specifications 758 user?s manual u14492ej4v1ud recommended oscillator constant (a) ceramic resonator (i) murata mfg. co., ltd (t a = ? 40 to +85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ? 40 to +110 c: pd703116(a1), 70f3116(a1)) oscillation frequency recommended circuit constant recommended voltage range type product name f x (mhz) c1 (pf) c2 (pf) r d ( ? ) min. (v) max. (v) cstcr4m00g55-r0 4.0 on-chip on-chip 0 3.0 3.6 surface mount cstcr6m00g55-r0 6.0 on-chip on-chip 0 3.0 3.6 caution this oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is ne cessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only oscilla tor characteristics. use the v850e/ia1 so that the internal operating conditi ons are within the specifications of the dc and ac characteristics. chapter 18 electrical specifications 759 user?s manual u14492ej4v1ud dc characteristics (t a = ?40 to +85c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to +110c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 pins for bus control note 1 2.2 v dd5 v v ih2 pins for nbd note 2 0.8v dd3 v dd3 v v ih3 port pins note 3 0.7v dd5 v dd5 v v ih4 port pins other than notes 1, 2, 3 0.8v dd5 v dd5 v v ih5 x1 pin 0.8v dd3 v dd3 +0.3 v input voltage, high v ih6 reset pin 0.8v dd3 5.5 v v il1 pins for bus control note 1 0 0.8 v v il2 pins for nbd note 2 0 0.2v dd3 v v il3 port pins note 3 0 0.3v dd5 v v il4 port pins other than notes 1, 2, 3 0 0.2v dd5 v v il5 x1 pin ?0.5 0.15v dd3 v input voltage, low v il6 reset pin 0 0.2v dd3 v v oh1 pins other than note 4 i oh = ?2.5 ma v dd5 ?1.0 v output voltage, high v oh2 pins for nbd note 4 i oh = ?2.5 ma v dd3 ?1.0 v i ol = 15 ma 2.0 v v ol1 pwm output note 5 i ol = 2.5 ma 0.4 v v ol2 pins other than notes 4, 5 i ol = 2.5 ma 0.4 v output voltage, low v ol3 pins for nbd note 4 i ol = 2.5 ma 0.4 v input leakage current, high i lih v i = v dd5 10 a input leakage current, low i lil v i = 0 v ?10 a output leakage current, high i loh v o = v dd5 10 a output leakage current, low i lol v o = 0 v ?10 a analog pin input leakage current i lian ani00 to ani07, ani10 to ani17 pins 10 a notes 1. ad0/pdl0 to ad15/pdl15, a16/pdh0 to a23/pdh7, lwr/pct0, uwr/pct1, pct2, pct3, rd/pct4, pct5, astb/pct6, pc t7, wait/pcm0, clkout/pcm1, hldak/pcm2, hldrq/pcm3, pcm4, cs0/pcs0 to cs7/pcs7 pins 2. clk_dbg, sync, ad0_dbg to ad3_dbg pins ( pd70f3116 only) 3. p31/txd0, p33/txd1, p36/txd2, p41/ so0, p44/so1, p47/ctxd pins 4. ad0_dbg to ad3_dbg, trig_dbg pins ( pd70f3116 only) 5. to000 to to005, to010 to to015 pins chapter 18 electrical specifications 760 user?s manual u14492ej4v1ud dc characteristics (t a = ?40 to +85c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to +110c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit v dd3 + cv dd note 2 1.9f xx + 2.8 2.5f xx + 5.0 ma pd703116 v dd5 note 3 0.8f xx + 0.8 1.0f xx ma v dd3 + cv dd note 2 2.4f xx + 12 3.6f xx + 18 ma in normal mode i dd1 pd70f3116 v dd5 note 3 30 50 ma v dd3 + cv dd note 2 0.9f xx + 6.8 1.8f xx + 4.0 ma pd703116 v dd5 note 3 20 40 ma v dd3 + cv dd note 2 1.2f xx 2.3f xx ma in halt mode i dd2 pd70f3116 v dd5 note 3 20 40 ma v dd3 + cv dd 3.0 10 ma in idle mode i dd3 v dd5 note 3 0.5 2.0 ma ? 40 c t a +85 c 20 1200 a v dd3 + cv dd ? 40 c t a +110 c 20 3500 a power supply current note 1 in stop mode i dd4 v dd5 note 3 10 120 a notes 1. value in the pll mode 2. determine the value by calculating f xx from the operating conditions. 3. the current of the to000 to to005 an d to010 to to015 pins is not included. remarks 1. f xx : internal system clock frequency (mhz) 2. an example of calculating the pow er supply current is shown below. ? power supply current (typ.) of the v850e/ia1 in normal mode when f xx = 32 mhz v dd3 + cv dd : i dd1 = 2.4f xx + 12 = 2.4 32 + 12 = 88.8 ma v dd5 : i dd1 = 30 ma chapter 18 electrical specifications 761 user?s manual u14492ej4v1ud data retention characteristics (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1)) parameter symbol conditions min. typ. max. unit v dddr stop mode, v dd3 = v dddr 1.5 3.6 v data retention voltage hv dddr stop mode, v dd5 = hv dddr 3.6 5.5 v ?40 c t a +85 c 20 1200 a i dddr v dd3 = v dddr ?40 c t a +110 c 20 3500 a data retention current hi dddr v dd5 = hv dddr note 1 10 120 a power supply voltage rise time t rvd 200 s power supply voltage fall time t fvd 200 s power supply voltage retention time (from stop mode setting) t hvd 0 ms stop release signal input time t drel 0 ns note 2 0.8hv dddr hv dddr v data retention input voltage, high v ihdr note 3 0.8v dddr v dddr v note 2 0 0.2hv dddr v data retention input voltage, low v ildr note 3 0 0.2v dddr v notes 1. the current of the to000 to to005 and to010 to to015 pins is not included. 2. p00/nmi, p01/eso0/intp0, p02/eso1/intp1, p03/ad trg0/intp2, p04/adtrg1 /intp3, p05/intp4 to p07/intp6, p10/tiud10/to10, p11/tcud10/in tp100, p12/tclr10/intp101, p13/tiud11/to11, p14/tcud11/intp110, p15/tclr11/intp111, p20/ti2/intp20, p21/to21/intp21 to p24/to24/intp24, p25/tclr2/intp25, p26/ti 3/tclr3/intp30, p27/to3/intp31, p30/rxd0, p32/rxd1, p34/asck1, p35/rxd2, p37/asck2, p40/ si0, p42/sck0, p43/si1, p45/sck1, p46/crxd, mode0 to mode2, cksel, reset pins 3. clk_dbg, sync, ad0_dbg to ad3_dbg pins ( pd70f3116 only) remark the typ. value is a reference value for when t a = 25 c. t hvd v dddr , hv dddr t drel v ihdr v ihdr t fvd t rvd v dd3 , v dd5 reset (input) stop mode release interrupt (nmi, etc.) (released by falling edge) stop mode release interrupt (nmi, etc.) (released by rising edge) v ildr stop mode setting chapter 18 electrical specifications 762 user?s manual u14492ej4v1ud ac characteristics (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 50 pf) ac test input test points (a) other than (b) to (d) below (b) ad0/pdl0 to ad15/pdl15, a16/pd h0 to a23/pdh7, lwr/pct0, uwr/ pct1, pct2, pct3, rd/pct4, pct5, astb/pct6, pct7, wait/pcm0, clkout/pcm1, hldak/pcm2, hldrq/pcm3, pcm4, cs0/pcs0 to cs7/pcs7 pins (c) clk_dbg note , sync note , ad0_dbg to ad3_dbg note , reset pins note pd70f3116 only (d) x1 pin v dd5 0 v 0.8v dd5 0.2v dd5 0.8v dd5 0.2v dd5 test points v dd3 0 v 0.8v dd3 0.2v dd3 0.8v dd3 0.2v dd3 test points v dd3 0 v 0.8v dd3 0.15v dd3 0.8v dd3 0.15v dd3 test points v dd5 0 v 2.2 v 0.8 v 2.2 v 0.8 v test points chapter 18 electrical specifications 763 user?s manual u14492ej4v1ud ac test output test points (a) pins other than (b) below (b) ad0_dbg to ad3_dbg, trig_dbg pins ( pd70f3116 only) load conditions caution in cases where the load ca pacitance is greater than 50 pf due to the circuit configuration, insert a buffer or other elemen t to reduce the devi ce?s load capacitance to 50 pf or lower. v dd5 0 v 0.8v dd5 0.2v dd5 0.8v dd5 0.2v dd5 test points v dd3 0 v 0.8v dd3 0.2v dd3 0.8v dd3 0.2v dd3 test points dut (device under test) c l = 50 pf chapter 18 electrical specifications 764 user?s manual u14492ej4v1ud (1) clock timing (1/2) (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit direct mode 31.25 125 ns pll mode note 1 156 250 ns direct mode 20 125 ns x1 input cycle <1> t cyx pll mode note 2 156 250 ns direct mode 6 ns x1 input high-level width <2> t wxh pll mode 50 ns direct mode 6 ns x1 input low-level width <3> t wxl pll mode 50 ns direct mode 4 ns x1 input rise time <4> t xr pll mode 10 ns direct mode 4 ns x1 input fall time <5> t xf pll mode 10 ns note 2 4 50 mhz note 1 4 32 mhz cpu operation frequency ? f xx clkout signal used note 3 4 32 mhz note 2 20 250 ns note 1 31.25 250 ns clkout output cycle <6> t cyk clkout signal used note 3 31.25 250 ns clkout high-level width <7> t wkh 0.5t ? 9 ns clkout low-level width <8> t wkl 0.5t ? 11 ns clkout rise time <9> t kr 11 ns clkout fall time <10> t kf 9 ns delay time from x1 to clkout <11> t dxk direct mode 40 ns notes 1. ?40c t a +110c 2. ?40c t a +85c 3. when interfacing to the external devices using the clkout signal, make the internal system clock frequency (f xx ) 32 mhz or lower. remark t = t cyk chapter 18 electrical specifications 765 user?s manual u14492ej4v1ud (1) clock timing (2/2) (2) output waveform (exc ept for clkout) (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit output rise time <12> t or 15 ns output fall time <13> t of 15 ns x1 <3> <1> <2> <4> <5> x1 (direct mode) (pll mode) <5> <1> <2> <3> <4> <11> <11> clkout (output) <8> <9> <7> <10> <6> <13> <12> signals other than clkout chapter 18 electrical specifications 766 user?s manual u14492ej4v1ud (3) reset timing (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit reset pin high-level width <14> t wrsh 500 ns at power-on and at stop mode release 500 + t ost ns reset pin low-level width <15> t wrsl other than at power-on and at stop mode release 500 ns caution thoroughly evaluate the oscillation stabilization time. remark t ost : oscillation stabilization time reset (input) <14> <15> chapter 18 electrical specifications 767 user?s manual u14492ej4v1ud (4) multiplex bus timing (a) clkout asynchronous (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb ) <16> t sast (0.5 + w as )t ? 16 ns address hold time (from astb ) <17> t hsta (0.5 + w ah )t ? 15 ns address float delay time from rd <18> t frda 11 ns data input setup time from address <19> t said (2 + w + w as + w ah )t ? 40 ns data input setup time from rd <20> t srdid (1 + w)t ? 40 ns delay time from astb to rd, lwr, uwr <21> t dstrdwr (0.5 + w ah )t ? 15 ns data input hold time (from rd ) <22> t hrdid 0 ns address output time from rd <23> t drda (1 + i)t ? 15 ns delay time from rd, lwr, uwr to astb <24> t drdwrst 0.5t ? 15 ns delay time from rd to astb <25> t drdst (1.5 + i + w as )t ? 15 ns rd, lwr, uwr low-level width <26> t wrdwrl (1 + w)t ? 22 ns astb high-level width <27> t wsth (1 + w as )t ? 15 ns data output time from lwr, uwr <28> t dwrod 10 ns data output setup time (to lwr, uwr ) <29> t sodwr (1 + w)t ? 25 ns data output hold time (from lwr, uwr ) <30> t hwrod t ? 20 ns <31> t sawt1 w 1 (1.5 + w as + w ah )t ? 40 ns wait setup time (to address) <32> t sawt2 (1.5 + w + w as + w ah )t ? 40 ns <33> t hawt1 w 1 (0.5 + w + w as + w ah )t ns wait hold time (from address) <34> t hawt2 (1.5 + w + w as + w ah )t ns <35> t sstwt1 w 1 (1 + w ah )t ? 32 ns wait setup time (to astb ) <36> t sstwt2 (1 + w + w ah )t ? 32 ns <37> t hstwt1 w 1 (w + w ah )t ns wait hold time (from astb ) <38> t hstwt2 (1 + w + w ah )t ns hldrq high-level width <39> t whqh t + 10 ns hldak low-level width <40> t whal t ? 15 ns delay time from address float to hldak <41> t dfha ?12 ns delay time from hldak to bus output <42> t dhac ?7 ns delay time from hldrq to hldak <43> t dhqha1 2t ns delay time from hldrq to hldak <44> t dhqha2 0.5t 1.5t + 30 ns chapter 18 electrical specifications 768 user?s manual u14492ej4v1ud remarks 1. t = t cyk 2. w: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 3. i: number of idle states insert ed after the read cycle (0 or 1) 4. w as : number of address setup wait states (0 or 1) 5. w ah : number of address hold wait states (0 or 1) 6. observe at least either of the data input hold time t hkid or t hrdid . 7. for the number of wait clo cks to be inserted, refer to 4.6.3 relationship be tween programmable wait and external wait . (b) clkout synchronous (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address <45> t dka ?7 19 ns delay time from clkout to address float <46> t fka ?12 15 ns delay time from clkout to astb <47> t dkst ?3 + w ah t 19 + w ah t ns delay time from clkout to rd, lwr, uwr <48> t dkrdwr ?5 19 ns data input setup time (to clkout ) <49> t sidk 21 ns data input hold time (from clkout ) <50> t hkid 5 ns delay time from clkout to data output <51> t dkod 19 ns wait setup time (to clkout ) <52> t swtk 21 ns wait hold time (from clkout ) <53> t hkwt 5 ns hldrq setup time (to clkout ) <54> t shqk 21 ns hldrq hold time (from clkout ) <55> t hkhq 5 ns delay time from clkout to hldak <56> t dkha 19 ns delay time from clkout to address float <57> t dkf 19 ns remarks 1. t = t cyk 2. w ah : number of address hold wait states (0 or 1) 3. observe at least either of the data input hold time t hkid or t hrdid . chapter 18 electrical specifications 769 user?s manual u14492ej4v1ud (c) read cycle (clkout syn chronous/asynchr onous, 1 wait) <21> clkout (output) a16 to a23 (output) cs0 to cs7 (output) rd (output) ad0 to ad15 (i/o) astb (output) wait (input) t1 t2 tw t3 data address hi-z <45> <19> <46> <47> <16> <27> <48> <35> <37> <36> <38> <31> <33> <32> <34> <52> <52> <53> <20> <26> <18> <17> <49> <50> <47> <22> <48> <23> <25> <24> <53> caution when interfacing with the external device using the clkout signal, set the internal system clock frequency (f xx ) to 32 mhz or lower. remark lwr and uwr are high level. chapter 18 electrical specifications 770 user?s manual u14492ej4v1ud (d) write cycle (clkout syn chronous/asynchr onous, 1 wait) clkout (output) ad0 to ad15 (i/o) astb (output) lwr (output) uwr (output) a16 to a23 (output) cs0 to cs7 (output) wait (input) t1 t2 tw t3 data address <45> <51> <47> <16> <17> <27> <47> <48> <21> <35> <52> <37> <36> <38> <31> <33> <32> <34> <53> <52> <53> <28> <29> <26> <48> <24> <30> caution when interfacing with the external device using the clkout signal, set the internal system clock frequency (f xx ) to 32 mhz or lower. remark rd is high level. chapter 18 electrical specifications 771 user?s manual u14492ej4v1ud (e) bus hold clkout (output) hldrq (input) hldak (output) a16 to a23 (output) cs0 to cs7 (output) ad0 to ad15 (i/o) astb (output) rd (output) lwr (output), uwr (output) th th th ti hi-z hi-z hi-z data hi-z <54> <55> <43> <56> <41> <57> <56> <44> <40> <42> <54> <39> caution when interfacing with the external device using the clkout signal, set the internal system clock frequency (f xx ) to 32 mhz or lower. chapter 18 electrical specifications 772 user?s manual u14492ej4v1ud (5) interrupt timing (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit nmi high-level width <58> t wnih 500 ns nmi low-level width <59> t wnil 500 ns n = 0 to 6 500 ns n = 100, 101, 110, 111, 30, 31 5t + 10 ns n = 20 to 25 (when analog filter specified) 500 ns intpn high-level width <60> t with n = 20 to 25 (when digital filt er specified) 5t + 10 ns n = 0 to 6 500 ns n = 100, 101, 110, 111, 30, 31 5t + 10 ns n = 20 to 25 (when analog filter specified) 500 ns intpn low-level width <61> t witl n = 20 to 25 (when digital filt er specified) 5t + 10 ns remark t: digital filter sampling clock t can be selected by setting the following registers. ? intp100, intp101: can be selected from f xx tm10 , f xx tm10 /2, f xx tm10 /4, and f xx tm10 /8 by setting the nrc101 and nrc100 bits of the timer 10 noise elimination time selection register (nrc10) (f xx tm10 : clock selected with the timer 1/timer 2 clock sele ction register (prm02)). ? intp110, intp111: can be selected from f xx tm11 , f xx tm11 /2, f xx tm11 /4, and f xx tm11 /8 by setting the nrc111 and nrc110 bits of the timer 11 noise elimination time selection register (nrc11) (f xx tm11 : clock selected with the prm02 register). ? intp30: can be selected from f xx tm3 /2, f xx tm3 /4, f xx tm3 /8, and f xx tm3 /16 by setting the nrc31 and nrc30 bits of the timer 3 noise elimination time selection register (nrc3) (f xx tm3 : clock selected with the timer 3 clock selection register (prm03)). ? intp31: can be selected from f xx tm3 /32, f xx tm3 /64, f xx tm3 /128, and f xx tm3 /256 by setting the nrc33 and nrc32 bits of the timer 3 noise eliminat ion time selection register (nrc3) (f xx tm3 : clock selected with the prm03 register). remark n = 0 to 6, 100, 101, 110, 111, 20 to 25, 30, 31 nmi (input) intpn (input) <58> <59> <60> <61> chapter 18 electrical specifications 773 user?s manual u14492ej4v1ud (6) timer input timing (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit tiudn, tcudn high-/low-level width <62> t wudh, t wudl n = 10, 11 5t + 10 ns tiudn, tcudn input time difference <63> t phud n = 10, 11 2t + 10 ns n = 10, 11, 2 (other than for through input), 3 5t + 10 ns tclrn high-/low-level width <64> t wtch, t wtcl n = 2 (for through input note ) 2t + 10 ns n = 2 (other than for through input), 3 5t + 10 ns tin high-/low-level width <65> t wtih, t wtil n = 2 (for through input note ) 2t + 10 ns note when setting the timer 2 count clock/control edge select ion register 0 (cse0)?s cese1 bit to 1 and cese0 bit to 0. remarks 1. t: digital filter sampling clock t can be selected by setting the following registers. ? when using tiudn, tcudn, and tclrn (n = 10, 11), the following cycles can be selected by setting the nrcn1 and nrcn0 bits of timer n noise elimination time selection register (nrcn). when f xx /2 is selected for the timer n base clock: f xx /2, f xx /4, f xx /8, f xx /16 when f xx /4 is selected for the timer n base clock: f xx /4, f xx /8, f xx /16, f xx /32 ? when using tclr2 and ti2, the following cycles can be selected by setting the prm2 bit of the timer 1/timer 2 clock sele ction register (prm02). when f xx /2 is selected for the timer 2 base clock: f xx /2 when f xx /4 is selected for the timer 2 base clock: f xx /4 ? when using tclr3 and ti3, the following cycl es can be selected by setting the nrc31 and nrc30 bits of timer 3 noise elimination time selection register (nrc3). when f xx is selected for the timer 3 base clock: f xx /2, f xx /4, f xx /8, f xx /16 when f xx /2 is selected for the timer 3 base clock: f xx /4, f xx /8, f xx /16, f xx /32 2. f xx : internal system clock frequency remark m = 10, 11 n = 10, 11, 2, 3 x = 2, 3 <62> tiudm (input) tcudm (input) tclrn (input) tix (input) <62> <62> <62> <63> <63> <63> <63> <64> <64> <65> <65> chapter 18 electrical specifications 774 user?s manual u14492ej4v1ud (7) timer operating frequency (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit ?40 c t a +85 c 40 mhz timer 00, 01 operating frequency t 0 ?40 c t a +110 c 32 mhz timer 10, 11 operating frequency t 1 16 mhz timer 20, 21 operating frequency note t 2 16 mhz timer 3 operating frequency t 3 32 mhz notes 1. setting the tesne1 and tesne0 bits of timer 2 count clock/control edge select register 0 (cse0) to 11b (both rising/falling edges) is prohibited when the prm2 bit of the timer 1/timer 2 clock selection register (prm02) is 1b (f clk = f xx /2) 2. set the vswc register to 15h when the prm2 bit of the timer 1/timer 2 clock selection register (prm02) = 0b (f clk = f xx /4). (8) csi timing (1/2) (a) master mode (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle <66> t cysk1 output 200 ns sckn high-level width <67> t wsk1h output 0.5t cysk1 ? 25 ns sckn low-level width <68> t wsk1l output 0.5t cysk1 ? 25 ns sin setup time (to sckn ) <69> t ssisk 35 ns sin hold time (from sckn ) <70> t hsksi 30 ns son output delay time (from sckn ) <71> t dskso 30 ns son output hold time (from sckn ) <72> t hskso 0.5t cysk1 ? 20 ns remark n = 0, 1 chapter 18 electrical specifications 775 user?s manual u14492ej4v1ud (8) csi timing (2/2) (b) slave mode (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle <66> t cysk1 input 200 ns sckn high-level width <67> t wsk1h input 90 ns sckn low-level width <68> t wsk1l input 90 ns sin setup time (to sckn ) <69> t ssisk 50 ns sin hold time (from sckn ) <70> t hsksi 50 ns son output delay time (from sckn ) <71> t dskso 55 ns son output hold time (from sckn ) <72> t hskso t wsk1h ns remark n = 0, 1 remarks 1. the broken lines indicate high impedance. 2. n = 0, 1 <66> <68> <67> <69> <70> <71> <72> sin (input) son (output) sckn (i/o) output data input data chapter 18 electrical specifications 776 user?s manual u14492ej4v1ud (9) uart0 timing (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit uart0 baud rate generator input frequency f brg 25 mhz remark f brg (uart0 baud rate generator input frequency) can be selected from f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512, f xx /1024, and f xx /2048 by setting the tps3 to tps0 bits of clock selection register 0 (cksr0) (f xx : internal system clock frequency). (10) uart1, uart2 timing (1/2) (a) clocked master mode (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit asckn cycle <73> t cysk0 output 1000 ns asckn high-level width <74> t wsk0h output k t ? 20 ns asckn low-level width <75> t wsk0l output k t ? 20 ns rxdn setup time (to asckn ) <76> t srxsk 1.5 t + 35 ns rxdn hold time (from asckn ) <77> t hskrx 0 ns txdn output delay time (from asckn ) <78> t dsktx t + 10 ns txdn output hold time (from asckn ) <79> t hsktx (k + 1)t ? 20 ns remarks 1. t = 2t cyk 2. k: setting value of prescaler compare register n (prscmn) of uartn 3. n = 1, 2 chapter 18 electrical specifications 777 user?s manual u14492ej4v1ud (10) uart1, uart2 timing (2/2) (b) clocked slave mode (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ?40 to + 110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit asckn cycle <73> t cysk0 input 1000 ns asckn high-level width <74> t wsk0h input 4 t + 80 ns asckn low-level width <75> t wsk0l input 4 t + 80 ns rxdn setup time (to asckn ) <76> t srxsk t + 10 ns rxdn hold time (from asckn ) <77> t hskrx t + 10 ns txdn output delay time (from asckn ) <78> t dsktx 2.5 t + 45 ns txdn output hold time (from asckn ) <79> t hsktx k t + 1.5 t ns remarks 1. t = 2t cyk 2. k: setting value of prscmn register of uartn 3. n = 1, 2 <73> <75> <74> <76> <77> <78> <79> rxdn (input) txdn (output) asckn (i/o) output data input data remark n = 1, 2 chapter 18 electrical specifications 778 user?s manual u14492ej4v1ud (11) nbd timing ( pd70f3116 only) (t a = 0 to +40c, v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v, output pin load capacitance: c l = 100 pf) parameter symbol conditions min. max. unit nbd cycle <80> t ndcyc 80 ns nbd cycle low-level width <81> t ndl 35 ns nbd data output delay time <82> t ndd 5 t ndcyc ? 20 ns nbd data output hold time <83> t ndhd 2 ns nbd data input setup time <84> t nds 20 ns nbd data input hold time <85> t ndh 5 ns sync input setup time <86> t ndsys 20 ns sync input hold time <87> t ndsyh 5 ns clk_dbg (input) ad0_dbg to ad3_dbg (output) ad0_dbg to ad3_dbg (input) sync (input) <80> <81> <84> <82> <83> <85> <86> <87> chapter 18 electrical specifications 779 user?s manual u14492ej4v1ud a/d converter characteristics (t a = ?40 to + 85 c: pd703116, 703116(a), 70f3116, 70f3116(a), t a = ? 40 to +110 c: pd703116(a1), 70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, av dd = v dd5 = 5 v 0.5 v, av ss = v ss3 = v ss5 = cv ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution ? 10 bit overall error note 1 ? 5 lsb quantization error ? 1/2 lsb conversion time t conv 5 10 s sampling time t samp 833 ns zero-scale error note 1 ? 3 lsb full-scale error note 1 ? 3 lsb differential linearity error note 1 ? 3 lsb integral linearity error note 1 ? 5 lsb analog input voltage v ian ? 0.3 av refn + 0.3 v analog reference voltage av ref av refn = av dd 4.5 5.5 v av refn input current note 2 ai ref 1 2 ma av dd power supply current note 2 ai dd 3 6 ma notes 1. the quantization error ( 0.5 lsb) is not included. 2. the v850e/ia1 incorporates two a/d converters. this is the rated value for one converter. remarks 1. lsb: least significant bit 2. n = 0, 1 chapter 18 electrical specifications 780 user?s manual u14492ej4v1ud 18.2 flash memory programming mode ( pd70f3116 only) basic characteristics (t a = 0 to 70 c (during rewrite), t a = ? 40 to +85 c (except during rewrite): pd70f3116, 70f3116(a), t a = ? 40 to +110 c (except during rewrite): pd70f3116(a1), v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v) parameter symbol conditions min. typ. max. unit operating frequency f x 4 50 mhz v pp1 during flash memory programming 7.5 7.8 8.1 v v ppl v pp low-level detection ? 0.3 0.2v dd3 v v ppm v pp , v dd3 level detection 0.65v dd3 v dd3 + 0.3 v v pp supply voltage v pph v pp high-voltage level detection 7.5 7.8 8.1 v v dd3 supply current i dd1 v pp = v pp1 4.5fx ma v pp supply current i pp v pp = 7.8 v 100 ma step erase time t er note 1 0.398 0.4 0.402 s overall erase time per area t era when the step erase time = 0.4 s, note 2 40 s/area write-back time t wb note 3 0.99 1 1.01 ms number of write-backs per write-back command c wb when the write-back time = 1 ms, note 4 300 c ount/write- back command number of erase/write-backs c erwb 16 count step writing time t wt note 5 18 20 22 s overall writing time per word t wtw when the step writing time = 20 s (1 word = 4 bytes), note 6 20 200 s/word number of rewrites per area c erwr 1 erase + 1 write after erase = 1 rewrite, note 7 100 c ount/area notes 1. the recommended setting value of the step erase time is 0.4 s. 2. the prewrite time prior to erasure and the erase verify time (write-back time) are not included. 3. the recommended setting value of the write-back time is 1 ms. 4. write-back is executed once by the issuance of th e write-back command. therefore, the retry count must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step writing time is 20 s. 6. 20 s is added to the actual writing time per word. t he internal verify time during and after the writing is not included. 7. when writing initially to shipped products, it is coun ted as one rewrite for both ?erase to write? and ?write only?. example (p: write, e: erase) shipped product ?? p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remarks 1. when the pg-fp4 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. do not change the settings unless otherwise specified. 2. area 0 = 00000h to 1ffffh, area 1 = 20000h to 3ffffh chapter 18 electrical specifications 781 user?s manual u14492ej4v1ud serial write operation characteristics (t a = 0 to 70 c, v dd3 = cv dd = 3.0 to 3.6 v, v dd5 = 5 v 0.5 v, v ss3 = v ss5 = cv ss = 0 v) parameter symbol conditions min. typ. max. unit v dd3 , v dd5 to v pp set time <88> t drpsr 10 s v pp to reset set time <89> t psrrf 1 s reset to v pp count start time <90> t rfof v pp = 7.8 v 10t + 1500 ns count execution time <91> t count 15 ms v pp counter high-level width <92> t ch 1 s v pp counter low-level width <93> t cl 1 s v pp counter rise time <94> t r 1 s v pp counter fall time <95> t f 1 s v pp to v dd3 , v dd5 reset time <96> t pfdr 10 s remark t = t cyk <88> <90> <93> <92> <91> <95> <94> 0 v 0 v reset (input) <89> <96> 0 v 4.5 v v dd3 v dd5 v dd5 v pp v dd3 v dd5 v pp 0 v 3.0 v <96> <88> 782 user?s manual u14492ej4v1ud chapter 19 package drawing 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 + 4 ? 3 g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 ? 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b 783 user?s manual u14492ej4v1ud chapter 20 recommended soldering conditions v850e/ia1 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than thos e recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 20-1. surface mounting type solderi ng conditions pd703116gj-xxx-uen: 144-pin plast ic lqfp (fine pitch) (20 20) pd703116gj(a)-xxx-uen: 144-pin pl astic lqfp (fine pitch) (20 20) pd703116gj(a1)-xxx-uen: 144-pin plastic lqfp (fine pitch) (20 20) pd70f3116gj-uen: 144-pin plast ic lqfp (fine pitch) (20 20) pd70f3116gj(a)-uen: 144-pin plastic lqfp (fine pitch) (20 20) pd70f3116gj(a1)-uen: 144-pin plastic lqfp (fine pitch) (20 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 230c, time: 30 seconds max. (at 210c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125c for 10 to 72 hours) ir30-103-2 vps package peak temperature: 215c, time: 25 to 40 seconds (at 200c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125c for 10 to 72 hours) vp15-103-2 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or le ss and 65% rh or less for the allowable storage period. caution do not use different soldering methods together. 784 user?s manual u14492ej4v1ud appendix a notes a.1 restriction on conflict between sl d instruction and interrupt request a.1.1 description if a conflict occurs between the decode oper ation of an instruction in <2> imm ediately before the sld instruction following an instruction in <1> and an interr upt request before the instru ction in <1> is complete, the execution result of the instruction in <1> ma y not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 785 user?s manual u14492ej4v1ud appendix b notes on target system design the following shows a diagram of the connection condi tions between the in-circuit emulator option board and conversion connector. design your system making allowanc es for conditions such as the form of parts mounted on the target system based on this configuration. figure b-1. 144-pin plastic lqfp (fine pitch) (20 20) side view target system nqpack144sd yqpack144sd 206.26 mm note in-circuit emulator option board conversion connector ie-703116-mc-em1 in-circuit emulator ie-v850e-mc yqguide note yqsocket144sdn (sold separately) can be inserted here to adjust the height (height: 3.2 mm). top view target system yqpack144sd, nqpack144sd, yqguide ie-703116-mc-em1 ie-v850e-mc connection condition diagram 13.3 mm 27.205 mm 21.58 mm 17.99 mm 75 mm 31.84 mm target system nqpack144sd yqpack144sd ie-703116-mc-em1 connect to ie-v850e-mc yqguide 786 user?s manual u14492ej4v1ud appendix c register index (1/11) symbol register name unit page adcr00 a/d conversion result register 00 adc 644 adcr01 a/d conversion result register 01 adc 644 adcr02 a/d conversion result register 02 adc 644 adcr03 a/d conversion result register 03 adc 644 adcr04 a/d conversion result register 04 adc 644 adcr05 a/d conversion result register 05 adc 644 adcr06 a/d conversion result register 06 adc 644 adcr07 a/d conversion result register 07 adc 644 adcr10 a/d conversion result register 10 adc 644 adcr11 a/d conversion result register 11 adc 644 adcr12 a/d conversion result register 12 adc 644 adcr13 a/d conversion result register 13 adc 644 adcr14 a/d conversion result register 14 adc 644 adcr15 a/d conversion result register 15 adc 644 adcr16 a/d conversion result register 16 adc 644 adcr17 a/d conversion result register 17 adc 644 adetm0 a/d voltage detection mode register 0 adc 643 adetm0h a/d voltage detection mode register 0h adc 643 adetm0l a/d voltage detection mode register 0l adc 643 adetm1 a/d voltage detection mode register 1 adc 643 adetm1h a/d voltage detection mode register 1h adc 643 adetm1l a/d voltage detection mode register 1l adc 643 adic0 interrupt control register intc 165 adic1 interrupt control register intc 165 adscm00 a/d scan mode register 00 adc 639 adscm00h a/d scan mode register 00h adc 639 adscm00l a/d scan mode register 00l adc 639 adscm01 a/d scan mode register 01 adc 642 adscm01h a/d scan mode register 01h adc 642 adscm01l a/d scan mode register 01l adc 642 adscm10 a/d scan mode register 10 adc 639 adscm10h a/d scan mode register 10h adc 639 adscm10l a/d scan mode register 10l adc 639 adscm11 a/d scan mode register 11 adc 642 adscm11h a/d scan mode register 11h adc 642 adscm11l a/d scan mode register 11l adc 642 asif0 asynchronous serial interface tr ansmission status register 0 uart0 411 asim0 asynchronous serial interface mode register 0 uart0 407 appendix c register index 787 user?s manual u14492ej4v1ud (2/11) symbol register name unit page asim10 asynchronous serial interface mode register 10 uart1 438 asim11 asynchronous serial interface mode register 11 uart1 440 asim20 asynchronous serial interface mode register 20 uart2 438 asim21 asynchronous serial interface mode register 21 uart2 440 asis0 asynchronous serial interface status register 0 uart0 410 asis1 asynchronous serial interface status register 1 uart1 441 asis2 asynchronous serial interface status register 2 uart2 441 awc address wait control register bcu 110 bcc bus cycle control register bcu 112 bct0 bus cycle type configuration register 0 bcu 100 bct1 bus cycle type configuration register 1 bcu 100 bfcm00 buffer register cm00 rpu 217 bfcm01 buffer register cm01 rpu 217 bfcm02 buffer register cm02 rpu 217 bfcm03 buffer register cm03 rpu 217 bfcm10 buffer register cm10 rpu 217 bfcm11 buffer register cm11 rpu 217 bfcm12 buffer register cm12 rpu 217 bfcm13 buffer register cm13 rpu 218 bpc peripheral area selection control register cpu 78 brgc0 baud rate generator control register 0 uart0 429 bsc bus size configuration register bcu 102 c1ba can1 bus active register fcan 582 c1brp can1 bit rate prescaler register fcan 583 c1ctrl can1 control register fcan 569 c1def can1 definition register fcan 573 c1dinf can1 bus diagnostic information register fcan 586 c1erc can1 error count register fcan 578 c1ie can1 interrupt enable register fcan 579 c1intp can1 interrupt pending register fcan 556 c1last can1 information register fcan 577 c1maskh0 can1 address mask 0 register h fcan 567 c1maskh1 can1 address mask 1 register h fcan 567 c1maskh2 can1 address mask 2 register h fcan 567 c1maskh3 can1 address mask 3 register h fcan 567 c1maskl0 can1 address mask 0 register l fcan 567 c1maskl1 can1 address mask 1 register l fcan 567 c1maskl2 can1 address mask 2 register l fcan 567 c1maskl3 can1 address mask 3 register l fcan 567 c1sync can1 synchronization control register fcan 587 canic0 interrupt control register intc 165 appendix c register index 788 user?s manual u14492ej4v1ud (3/11) symbol register name unit page canic1 interrupt control register intc 165 canic2 interrupt control register intc 165 canic3 interrupt control register intc 165 cc100 capture/compare register 100 rpu 290 cc101 capture/compare register 101 rpu 291 cc10ic0 interrupt control register intc 165 cc10ic1 interrupt control register intc 165 cc110 capture/compare register 110 rpu 290 cc111 capture/compare register 111 rpu 291 cc11ic0 interrupt control register intc 165 cc11ic1 interrupt control register intc 165 cc2ic0 interrupt control register intc 165 cc2ic1 interrupt control register intc 165 cc2ic2 interrupt control register intc 165 cc2ic3 interrupt control register intc 165 cc2ic4 interrupt control register intc 165 cc2ic5 interrupt control register intc 165 cc30 capture/compare register 30 rpu 370 cc31 capture/compare register 31 rpu 370 cc3ic0 interrupt control register intc 165 cc3ic1 interrupt control register intc 165 ccintp can interrupt pending register fcan 554 ccr0 capture/compare control register 0 rpu 296 ccr1 capture/compare control register 1 rpu 296 ccstate0 timer 2 capture/compare 1 to 4 status register 0 rpu 342 ccstate0h timer 2 capture/compare 1 to 4 status register 0h rpu 342 ccstate0l timer 2 capture/compare 1 to 4 status register 0l rpu 342 cgcs can main clock selection register fcan 562 cgie can global interrupt enable register fcan 561 cgintp can global interrupt pending register fcan 555 cgmsr can message search result register fcan 565 cgmss can message search start register fcan 565 cgst can global status register fcan 558 cgtsc can time stamp count register fcan 564 ckc clock control register cg 193 cksr0 clock selection register 0 uart0 428 cm000 compare register 000 rpu 216 cm001 compare register 001 rpu 216 cm002 compare register 002 rpu 216 cm003 compare register 003 rpu 217 cm010 compare register 010 rpu 216 appendix c register index 789 user?s manual u14492ej4v1ud (4/11) symbol register name unit page cm011 compare register 011 rpu 216 cm012 compare register 012 rpu 216 cm013 compare register 013 rpu 217 cm03ic0 interrupt control register intc 165 cm03ic1 interrupt control register intc 165 cm100 compare register 100 rpu 289 cm101 compare register 101 rpu 289 cm10ic0 interrupt control register intc 165 cm10ic1 interrupt control register intc 165 cm110 compare register 110 rpu 289 cm111 compare register 111 rpu 289 cm11ic0 interrupt control register intc 165 cm11ic1 interrupt control register intc 165 cm4 compare register 4 rpu 395 cm4ic0 interrupt control register intc 165 cmse050 timer 2 sub-channel 0, 5 capt ure/compare control register rpu 336 cmse120 timer 2 sub-channel 1, 2 capt ure/compare control register rpu 337 cmse340 timer 2 sub-channel 3, 4 capt ure/compare control register rpu 339 csc0 chip area selection control register 0 bcu 97 csc1 chip area selection control register 1 bcu 97 csce0 timer 2 software event capture register rpu 344 cse0 timer 2 count clock/control edge selection register 0 rpu 330 cse0h timer 2 count clock/control edge selection register 0h rpu 330 cse0l timer 2 count clock/contro l edge selection register 0l rpu 330 csic0 clocked serial interface cl ock selection register 0 csi0 474 csic1 clocked serial interface cl ock selection register 1 csi1 474 csiic0 interrupt control register intc 165 csiic1 interrupt control register intc 165 csim0 clocked serial interf ace mode register 0 csi0 472 csim1 clocked serial interf ace mode register 1 csi1 472 csl10 cc101 capture input selection register rpu 302 csl11 cc111 capture input selection register rpu 302 cstop can stop register fcan 557 cvpe10 timer 2 sub-channel 1 main capture/compare register rpu 326 cvpe20 timer 2 sub-channel 2 main capture/compare register rpu 326 cvpe30 timer 2 sub-channel 3 main capture/compare register rpu 326 cvpe40 timer 2 sub-channel 4 main capture/compare register rpu 326 cvse00 timer 2 sub-channel 0 c apture/compare register rpu 325 cvse10 timer 2 sub-channel 1 sub capture/compare register rpu 327 cvse20 timer 2 sub-channel 2 sub capture/compare register rpu 327 cvse30 timer 2 sub-channel 3 sub capture/compare register rpu 327 appendix c register index 790 user?s manual u14492ej4v1ud (5/11) symbol register name unit page cvse40 timer 2 sub-channel 4 sub capture/compare register rpu 327 cvse50 timer 2 sub-channel 5 c apture/compare register rpu 327 dadc0 dma addressing control register 0 dmac 129 dadc1 dma addressing control register 1 dmac 129 dadc2 dma addressing control register 2 dmac 129 dadc3 dma addressing control register 3 dmac 129 dbc0 dma transfer count register 0 dmac 128 dbc1 dma transfer count register 1 dmac 128 dbc2 dma transfer count register 2 dmac 128 dbc3 dma transfer count register 3 dmac 128 dchc0 dma channel control register 0 dmac 131 dchc1 dma channel control register 1 dmac 131 dchc2 dma channel control register 2 dmac 131 dchc3 dma channel control register 3 dmac 131 dda0h dma destination address register 0h dmac 126 dda0l dma destination address register 0l dmac 127 dda1h dma destination address register 1h dmac 126 dda1l dma destination address register 1l dmac 127 dda2h dma destination address register 2h dmac 126 dda2l dma destination address register 2l dmac 127 dda3h dma destination address register 3h dmac 126 dda3l dma destination address register 3l dmac 127 ddis dma disable status register dmac 133 detic0 interrupt control register intc 165 detic1 interrupt control register intc 165 dmaic0 interrupt control register intc 165 dmaic1 interrupt control register intc 165 dmaic2 interrupt control register intc 165 dmaic3 interrupt control register intc 165 drst dma restart register dmac 133 dsa0h dma source address register 0h dmac 124 dsa0l dma source address register 0l dmac 125 dsa1h dma source address register 1h dmac 124 dsa1l dma source address register 1l dmac 125 dsa2h dma source address register 2h dmac 124 dsa2l dma source address register 2l dmac 125 dsa3h dma source address register 3h dmac 124 dsa3l dma source address register 3l dmac 125 dtfr0 dma trigger factor register 0 dmac 134 dtfr1 dma trigger factor register 1 dmac 134 dtfr2 dma trigger factor register 2 dmac 134 appendix c register index 791 user?s manual u14492ej4v1ud (6/11) symbol register name unit page dtfr3 dma trigger factor register 3 dmac 134 dtm00 dead-time timer 00 rpu 216 dtm01 dead-time timer 01 rpu 216 dtm02 dead-time timer 02 rpu 216 dtm10 dead-time timer 10 rpu 216 dtm11 dead-time timer 11 rpu 216 dtm12 dead-time timer 12 rpu 216 dtrr0 dead-time timer reload register 0 rpu 216 dtrr1 dead-time timer reload register 1 rpu 216 dwc0 data wait control register 0 bcu 109 dwc1 data wait control register 1 bcu 109 fem0 timer 2 input filter mode register 0 rpu 176, 710 fem1 timer 2 input filter mode register 1 rpu 176, 710 fem2 timer 2 input filter mode register 2 rpu 176, 710 fem3 timer 2 input filter mode register 3 rpu 176, 710 fem4 timer 2 input filter mode register 4 rpu 176, 710 fem5 timer 2 input filter mode register 5 rpu 176, 710 flpmc flash programming mode control register cpu 740 imr0 interrupt mask register 0 intc 168 imr0h interrupt mask register 0h intc 168 imr0l interrupt mask register 0l intc 168 imr1 interrupt mask register 1 intc 168 imr1h interrupt mask register 1h intc 168 imr1l interrupt mask register 1l intc 168 imr2 interrupt mask register 2 intc 168 imr2h interrupt mask register 2h intc 168 imr2l interrupt mask register 2l intc 168 imr3 interrupt mask register 3 intc 168 imr3h interrupt mask register 3h intc 168 imr3l interrupt mask register 3l intc 168 intm0 external interrupt mode register 0 intc 157 intm1 external interrupt mode register 1 intc 171 intm2 external interrupt mode register 2 intc 171 ispr in-service priority register intc 169 itrg0 a/d internal trigger selection register adc 647 lockr lock register cpu 196 m_conf00 to m_conf31 can message configuration registers 00 to 31 fcan 548 m_ctrl00 to m_ctrl31 can message control registers 00 to 31 fcan 540 appendix c register index 792 user?s manual u14492ej4v1ud (7/11) symbol register name unit page m_datan0 to m_datan7 can message data registers n0 to n7 (n = 00 to 31) fcan 544 m_dlc00 to m_dlc31 can message data length registers 00 to 31 fcan 538 m_idh00 to m_idh31 can message id registers h00 to h31 fcan 546 m_idl00 to m_idl31 can message id registers l00 to l31 fcan 546 m_stat00 to m_stat31 can message status registers 00 to 31 fcan 550 m_time00 to m_time31 can message time stamp registers 00 to 31 fcan 543 nbdh ram access data buffer register h nbd 627 nbdhl ram access data buffer register hl nbd 627 nbdhu ram access data buffer register hu nbd 627 nbdl ram access data buffer register l nbd 627 nbdll ram access data buffer register ll nbd 627 nbdlu ram access data buffer register lu nbd 627 nbdmdh dma destination address setting register dh nbd 629 nbdmdl dma destination address setting register dl nbd 629 nbdmsh dma source address setting register sh nbd 628 nbdmsl dma source address setting register sl nbd 628 nrc10 timer 10 noise elimination ti me selection register rpu 707 nrc11 timer 11 noise elimination ti me selection register rpu 707 nrc3 timer 3 noise elimination ti me selection register rpu 708 octle0 timer 2 output control register 0 rpu 335 octle0h timer 2 output control register 0h rpu 335 octle0l timer 2 output control register 0l rpu 335 odele0 timer 2 output delay register 0 rpu 343 odele0h timer 2 output delay register 0h rpu 343 odele0l timer 2 output delay register 0l rpu 343 p0 port 0 port 682 p0ic0 interrupt control register intc 165 p0ic1 interrupt control register intc 165 p0ic2 interrupt control register intc 165 p0ic3 interrupt control register intc 165 p0ic4 interrupt control register intc 165 p0ic5 interrupt control register intc 165 p0ic6 interrupt control register intc 165 p1 port 1 port 683 p2 port 2 port 686 p3 port 3 port 689 appendix c register index 793 user?s manual u14492ej4v1ud (8/11) symbol register name unit page p4 port 4 port 691 pcm port cm port 701 pcs port cs port 697 pct port ct port 699 pdh port dh port 693 pdl port dl port 695 pdlh port dlh port 695 pdll port dll port 695 pfc1 port 1 function control register port 685 pfc2 port 2 function control register port 688 phcmd peripheral command register cpu 192 phs peripheral status register cpu 195 pm1 port 1 mode register port 683 pm2 port 2 mode register port 686 pm3 port 3 mode register port 689 pm4 port 4 mode register port 691 pmc1 port 1 mode control register port 684 pmc2 port 2 mode control register port 687 pmc3 port 3 mode control register port 690 pmc4 port 4 mode control register port 692 pmccm port cm mode control register port 702 pmccs port cs mode control register port 698 pmcct port ct mode control register port 700 pmcdh port dh mode control register port 694 pmcdl port dl mode control register port 696 pmcdlh port dl mode control register h port 696 pmcdll port dl mode control register l port 696 pmcm port cm mode register port 701 pmcs port cs mode register port 698 pmct port ct mode register port 699 pmdh port dh mode register port 693 pmdl port dl mode register port 696 pmdlh port dl mode register h port 696 pmdll port dl mode register l port 696 poer0 pwm output enable register 0 rpu 232 poer1 pwm output enable register 1 rpu 232 prcmd command register cpu 200 prm01 timer 0 clock sele ction register rpu 219 prm02 timer 1/timer 2 clock se lection register rpu 292, 328 prm03 timer 3 clock sele ction register rpu 372 prm04 fcan clock selection register fcan 537 appendix c register index 794 user?s manual u14492ej4v1ud (9/11) symbol register name unit page prm10 prescaler mode register 10 rpu 299 prm11 prescaler mode register 11 rpu 299 prscm1 prescaler compare register 1 uart1 464 prscm2 prescaler compare register 2 uart2 464 prscm3 prescaler compare register 3 csi0, csi1 504 prsm1 prescaler mode register 1 uart1 463 prsm2 prescaler mode register 2 uart2 463 prsm3 prescaler mode register 3 csi0, csi1 503 psc power save control register cpu 201 psmr power save mode register cpu 200 psto0 pwm software timing output register 0 rpu 233 psto1 pwm software timing output register 1 rpu 233 rxb0 reception buffer register 0 uart0 412 rxb1 2-frame continuous recept ion buffer register 1 uart1 443 rxb2 2-frame continuous recept ion buffer register 2 uart2 443 rxbl1 reception buffer register l1 uart1 443 rxbl2 reception buffer register l2 uart2 443 sc_stat00 to sc_stat31 can status set/clear registers 00 to 31 fcan 552 seic0 interrupt control register intc 165 sesa10 signal edge selection register 10 intc, rpu 172, 297 sesa11 signal edge selection register 11 intc, rpu 172, 297 sesc valid edge selection register intc, rpu 175, 377 sese0 timer 2 sub-channel input event edge selection register 0 rpu 331 sese0h timer 2 sub-channel input event edge selection register 0h rpu 331 sese0l timer 2 sub-channel input event edge selection register 0l rpu 331 sio0 serial i/o shift register 0 csi0 484 sio1 serial i/o shift register 1 csi1 484 siol0 serial i/o shift register l0 csi0 485 siol1 serial i/o shift register l1 csi1 485 sirb0 clocked serial interface re ception buffer register 0 csi0 476 sirb1 clocked serial interface re ception buffer register 1 csi1 476 sirbe0 clocked serial interface read- only reception buffer register 0 csi0 478 sirbe1 clocked serial interface read- only reception buffer register 1 csi1 478 sirbel0 clocked serial interface read- only reception buffer register l0 csi0 479 sirbel1 clocked serial interface read- only reception buffer register l1 csi1 479 sirbl0 clocked serial interface rec eption buffer register l0 csi0 477 sirbl1 clocked serial interface rec eption buffer register l1 csi1 477 sotb0 clocked serial interface tran smission buffer register 0 csi0 480 sotb1 clocked serial interface tran smission buffer register 1 csi1 480 sotbf0 clocked serial interface initia l transmission buffer register 0 csi0 482 appendix c register index 795 user?s manual u14492ej4v1ud (10/11) symbol register name unit page sotbf1 clocked serial interface initia l transmission buffer register 1 csi1 482 sotbfl0 clocked serial interface initia l transmission buffer register l0 csi0 483 sotbfl1 clocked serial interface initia l transmission buffer register l1 csi1 483 sotbl0 clocked serial interface tran smission buffer register l0 csi0 481 sotbl1 clocked serial interface tran smission buffer register l1 csi1 481 spec0 tomr write enable register 0 rpu 242 spec1 tomr write enable register 1 rpu 242 sric0 interrupt control register intc 165 sric1 interrupt control register intc 165 sric2 interrupt control register intc 165 status0 status register 0 rpu 301 status1 status register 1 rpu 301 stic0 interrupt control register intc 165 stic1 interrupt control register intc 165 stic2 interrupt control register intc 165 stopte0 timer 2 clock st op register 0 rpu 329 stopte0h timer 2 clock st op register 0h rpu 329 stopte0l timer 2 clock st op register 0l rpu 329 tbstate0 timer 2 time base status register 0 rpu 341 tbstate0h timer 2 time base status register 0h rpu 341 tbstate0l timer 2 time base status register 0l rpu 341 tcre0 timer 2 time base control register 0 rpu 332 tcre0h timer 2 time base control register 0h rpu 332 tcre0l timer 2 time base control register 0l rpu 332 tm00 timer 00 rpu 215 tm01 timer 01 rpu 215 tm0ic0 interrupt control register intc 165 tm0ic1 interrupt control register intc 165 tm10 timer 10 rpu 287 tm11 timer 11 rpu 287 tm20 timer 20 rpu 325 tm21 timer 21 rpu 325 tm2ic0 interrupt control register intc 165 tm2ic1 interrupt control register intc 165 tm3 timer 3 rpu 368 tm3ic0 interrupt control register intc 165 tm4 timer 4 rpu 394 tmc00 timer control register 00 rpu 220 tmc00h timer control register 00h rpu 220 tmc00l timer control register 00l rpu 220 tmc01 timer control register 01 rpu 220 appendix c register index 796 user?s manual u14492ej4v1ud (11/11) symbol register name unit page tmc01h timer control register 01h rpu 220 tmc01l timer control register 01l rpu 220 tmc10 timer control register 10 rpu 294 tmc11 timer control register 11 rpu 294 tmc30 timer control register 30 rpu 373 tmc31 timer control register 31 rpu 375 tmc4 timer control register 4 rpu 397 tmic0 timer connection sele ction register 0 rpu 402 tomr0 timer output mode register 0 rpu 227 tomr1 timer output mode register 1 rpu 227 tuc00 timer unit control register 00 rpu 226 tuc01 timer unit control register 01 rpu 226 tum0 timer unit mode register 0 rpu 293 tum1 timer unit mode register 1 rpu 293 txb0 transmission buffer register 0 uart0 413 txs1 2-frame continuous transm ission shift register 1 uart1 446 txs2 2-frame continuous transm ission shift register 2 uart2 446 txsl1 transmission shift register l1 uart1 446 txsl2 transmission shift register l2 uart2 446 vswc system wait control register bcu 94 797 user?s manual u14492ej4v1ud appendix d instruction set list d.1 functions (1) symbols used in operand descriptions symbol explanation reg1 general-purpose register (used as source register) reg2 general-purpose register (usually used as destinat ion register. used as source register in some instructions.) reg3 general-purpose register (usually stores rema inder of division result or higher 32 bits of multiplication result.) bit#3 3-bit data for bit number specification immx x-bit immediate data dispx x-bit displacement data regid system register number vector 5-bit data that specifies a trap vector (00h to 1fh) cccc 4-bit data that shows a condition code sp stack pointer (r3) ep element pointer (r30) list x-item register list (2) symbols used in operands symbol explanation r 1 bit of data of code that specifies reg1 or regid r 1 bit of data of code that specifies reg2 w 1 bit of data of code that specifies reg3 d 1 bit of data of a displacement i 1 bit of immediate data (shows higher bit of immediate data) i 1 bit of immediate data cccc 4-bit data that shows a condition code cccc 4-bit data that shows condition code of bcond instruction bbb 3-bit data for bit number specification l 1 bit of data that specifies a pr ogram register in a register list s 1 bit of data that specifies a system register in a register list appendix d instruction set list 798 user?s manual u14492ej4v1ud (3) symbols used in operations symbol explanation assignment gr [ ] general-purpose register sr [ ] system register zero-extend (n) zero-extend n to word length. sign-extend (n) sign-extend n to word length. load-memory (a, b) read data of size ?b? from address ?a?. store-memory (a, b, c) write data ?b? of size ?c? to address ?a?. load-memory-bit (a, b) read bit ?b? of address ?a?. store-memory-bit (a, b, c) write ?c? in bit ?b? of address ?a?. saturated (n) perform saturation proces sing of n (n is 2?s complement). if n is a computation result and n 7fffffffh, make n = 7fffffffh. if n is a computation result and n 80000000h, make n = 80000000h. result reflect result in flag. byte byte (8 bits) half-word halfword (16 bits) word word (32 bits) + addition ? subtraction || bit concatenation multiplication division % remainder of division result and logical product or logical sum xor exclusive logical sum not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) symbols used in execution clock symbol explanation i when executing another instruction immediat ely after instruction execution (issue) r when repeating same instruction immediat ely after instruction execution (repeat) | when using instruction execution result in inst ruction immediately afte r instruction execution (latency) appendix d instruction set list 799 user?s manual u14492ej4v1ud (5) symbols used in flag operations symbol explanation (blank) no change 0 clear to 0. set or cleared according to result. r previously saved value is restored. (6) condition codes condition name (cond) condition code (cccc) condition expression explanation v 0000 ov = 1 overflow nv 1000 ov = 0 no overflow c/l 0001 cy = 1 carry lower (less than) nc/nl 1001 cy = 0 no carry no lower (greater than or equal) z/e 0010 z = 1 zero equal nz/ne 1010 z = 0 not zero not equal nh 0011 (cy or z) = 1 not higher (less than or equal) h 1011 (cy or z) = 0 higher (greater than) n 0100 s = 1 negative p 1100 s = 0 positive t 0101 ? always (unconditional) sa 1101 sat = 1 saturated lt 0110 (s xor ov) = 1 less than signed ge 1110 (s xor ov) = 0 greater than or equal signed le 0111 ((s xor ov) or z) = 1 less than or equal signed gt 1111 ((s xor ov) or z) = 0 greater than signed appendix d instruction set list 800 user?s manual u14492ej4v1ud d.2 instruction set (alphabetical order) (1/5) execution clock flags mnemonic operands opcode operation i r i cy ov s z sat reg1, reg2 r r r r r 0 0 1 1 1 0 r r r r r gr[reg2] gr[reg2] + gr[reg1] 1 1 1 add imm5, reg2 r r r r r 0 1 0 0 1 0 i i i i i gr[reg2] gr[reg2] + sign-extend (imm5) 1 1 1 addi imm16, r r r r r 1 1 0 0 0 0 r r r r r gr[reg2] gr[reg1] + sign-extend (imm16) 1 1 1 reg1, reg2 i i i i i i i i i i i i i i i i and reg1, reg2 r r r r r 0 0 1 0 1 0 r r r r r gr[reg2] gr[reg2] and gr[reg1] 1 1 1 0 r r r r r 1 1 0 1 1 0 r r r r r 1 1 1 0 0 andi imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] and zero-extend (imm16) d d d d d 1 0 1 1 d d d c c c c conditions satisfied 3 note 2 3 note 2 3 note 2 bcond disp9 if conditions are satisfied then pc pc + sign-extend (disp9) conditions not satisfied 1 1 1 r r r r r 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 bsh reg2, reg3 w w w w w 0 1 1 0 1 0 0 0 0 1 0 gr[reg3] gr[reg2] (23:16) || gr[reg2] (31:24) || gr[reg2] (7:0) || gr[reg2] (15:8) r r r r r 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 bsw reg2, reg3 w w w w w 0 1 1 0 1 0 0 0 0 0 0 gr[reg3] gr[reg2] (7:0) || gr[reg2] (15:8) || gr [reg2] (23:16) || gr[reg2] (31:24) callt imm6 0 0 0 0 0 0 1 0 0 0 i i i i i i ctpc pc + 2 (return pc) ctpsw psw adr ctbp + zero-extend (imm6 logically shift left by 1) pc ctbp + zero-extend (load-memory (adr, halfword) 5 5 5 1 0 b b b 1 1 1 1 1 0 r r r r r bit#3, disp16[reg1] d d d d d d d d d d d d d d d d adr gr[reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 0) 3 note 3 3 note 3 3 note 3 1 0 b b b 1 1 1 1 1 0 r r r r r clr1 reg2, [reg1] d d d d d d d d d d d d d d d d adr gr[reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, 0) 3 note 3 3 note 3 3 note 3 r r r r r 1 1 1 1 1 1 i i i i i cccc, imm5, reg2, reg3 w w w w w 0 1 1 0 0 0 c c c c 0 if conditions are satisfied then gr[reg3] sign-extend (imm5) else gr[reg3] gr[reg2] 1 1 1 r r r r r 1 1 1 1 1 1 r r r r r cmov cccc, reg1, reg2, reg3 w w w w w 0 1 1 0 0 1 c c c c 0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1, reg2 r r r r r 0 0 1 1 1 1 r r r r r result gr[reg2] ? gr[reg1] 1 1 1 cmp imm5, reg2 r r r r r 0 1 0 0 1 1 i i i i i result gr[reg2] ? sign-extend (imm5) 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 ctret 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 pc ctpc psw ctpsw 4 4 4 r r r r r 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 dbret 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 pc dbpc psw dbpsw 4 4 4 r r r r r dbtrap 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 dbpc pc + 2 (return pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 4 4 4 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 di 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 psw.id 1 1 1 1 note 1 appendix d instruction set list 801 user?s manual u14492ej4v1ud (2/5) execution clock flags mnemonic operands opcode operation i r i cy ov s z sat 0 0 0 0 0 1 1 0 0 1 i i i i il imm5, list12 l l l l l l l l l l l 0 0 0 00 sp sp + zero-extend (imm5 l ogically shift left by 2) gr[reg in list12] load-memory (sp, word) sp sp + 4 repeat 2 steps above until regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 0 0 0 0 0 1 1 0 0 1 i i i i il dispose imm5, list12[reg1] l l l l l l l l l l l r r r rr sp sp + zero-extend (imm5 l ogically shift left by 2) gr[reg in list12] load-memory (sp, word) sp sp + 4 repeat 2 steps above until regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 r r r r r 1 1 1 1 1 1 r r r rr div reg1, reg2, reg3 w w w w w 0 1 0 1 1 0 0 0 0 00 gr[reg2] gr[reg2] gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1, reg2 r r r r r 0 0 0 0 1 0 r r r rr gr[reg2] gr[reg2] gr[reg1 ] note 6 35 35 35 r r r r r 1 1 1 1 1 1 r r r rr divh reg1, reg2, reg3 w w w w w 0 1 0 1 0 0 0 0 0 00 gr[reg2] gr[reg2] gr[reg1 ] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 r r r r r 1 1 1 1 1 1 r r r rr divhu reg1, reg2, reg3 w w w w w 0 1 0 1 0 0 0 0 0 10 gr[reg2] gr[reg2] gr[reg1 ] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 r r r r r 1 1 1 1 1 1 r r r rr divu reg1, reg2, reg3 w w w w w 0 1 0 1 1 0 0 0 0 10 gr[reg2] gr[reg2] gr[reg1 ] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 1 0 0 0 0 1 1 1 1 1 1 0 0 0 00 ei 0 0 0 0 0 0 0 1 0 1 1 0 0 0 00 psw.id 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 00 halt 0 0 0 0 0 0 0 1 0 0 1 0 0 0 00 stop 1 1 1 r r r r r 1 1 1 1 1 1 0 0 0 00 hsw reg2, reg3 w w w w w 0 1 1 0 1 0 0 0 1 00 gr[reg3] gr[reg2] (15:0) || gr[reg2] (31:16) 1 1 1 0 r r r r r 1 1 1 1 0 d d d d dd jarl disp22, reg2 d d d d d d d d d d d d d d d0 gr[reg2] pc + 4 pc pc + sign-extend (disp22) 3 3 3 jmp [reg1] 0 0 0 0 0 0 0 0 0 1 1 r r r rr pc gr[reg1] 4 4 4 0 0 0 0 0 1 1 1 1 0 d d d d dd jr disp22 d d d d d d d d d d d d d d d 0 pc pc + sign-extend (disp22) 3 3 3 r r r r r 1 1 1 0 0 0 r r r rr ld.b disp16[reg1], reg2 d d d d d d d d d d d d d d dd adr gr[reg1] + sign-extend (disp16) gr[reg2] sign-extend (load-memory (adr, byte)) 1 1 note 11 r r r r r 1 1 1 1 0 b r r r rr ld.bu disp16[reg1], reg2 d d d d d d d d d d d d d d d 1 adr gr[reg1] + sign-extend (disp16) gr[reg2] zero-extend (load-memory (adr, byte)) 1 1 note 11 r r r r r 1 1 1 0 0 1 r r r rr ld.h disp16[reg1], reg2 d d d d d d d d d d d d d d d 0 adr gr[reg1] + sign-extend (disp16) gr[reg2] sign-extend (load-memory (adr, halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2, regid r 0 r 0 r 0 r 0 r 0 1 0 1 0 1 0 1 0 1 0 1 1 r 0 r 0 r 0 r 0 r 0 sr[regid] gr[reg2] regid = psw 1 1 1 r r r r r 1 1 1 0 0 1 r r r rr ld.hu disp16[reg1], reg2 d d d d d d d d d d d d d d d 1 adr gr[reg1] + sign-extend (disp16) gr[reg2] zero-extend (load-memory (adr, halfword)) 1 1 note 11 note 7 notes 8, 10 note 8 note 12 note 8 note 5 note 7 appendix d instruction set list 802 user?s manual u14492ej4v1ud (3/5) execution clock flags mnemonic operands opcode operation i r i cy ov s z sat r r r r r 1 1 1 0 0 1 r r r r r ld.w disp16[reg1], reg2 d d d d d d d d d d d d d d d 1 adr gr[reg1] + sign-extend (disp16) gr[reg2] load-memory (adr, word) 1 1 note 11 reg1, reg2 r r r r r 0 0 0 0 0 0 r r r r r gr[reg2] gr[reg1] 1 1 1 imm5, reg2 r r r r r 0 1 0 0 0 0 i i i i i gr[reg2] sign-extend (imm5) 1 1 1 0 0 0 0 0 1 1 0 0 0 1 r r r r r gr[reg1] imm32 2 2 2 i i i i i i i i i i i i i i i i mov imm32, reg1 i i i i i i i i i i i i i i i i r r r r r 1 1 0 0 0 1 r r r r r movea imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] + sign-extend (imm16) 1 1 1 r r r r r 1 1 0 0 1 0 r r r r r movhi imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] + (imm16 || 0 16 ) 1 1 1 r r r r r 1 1 1 1 1 1 r r r r r reg1, reg2, reg3 w w w w w 0 1 0 0 0 1 0 0 0 0 0 gr[reg3] || gr[reg2] gr[reg2] gr[reg1] reg1 reg2 reg3, reg3 r0 1 2 note 14 2 r r r r r 1 1 1 1 1 1 i i i i i mul note 22 imm9, reg2, reg3 w w w w w 0 1 0 0 1 i i i i 0 0 gr[reg3] || gr[reg2] gr[reg2] sign-extend (imm9) 1 2 note 14 2 reg1, reg2 r r r r r 0 0 0 1 1 1 r r r r r gr[reg2] gr[reg2] note 6 gr[reg1] note 6 1 1 2 mulh imm5, reg2 r r r r r 0 1 0 1 1 1 i i i i i gr[reg2] gr[reg2] note 6 sign-extend (imm5) 1 1 2 r r r r r 1 1 0 1 1 1 r r r r r mulhi imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] note 6 imm16 1 1 2 r r r r r 1 1 1 1 1 1 r r r r r reg1, reg2, reg3 w w w w w 0 1 0 0 0 1 0 0 0 1 0 gr[reg3] || gr[reg2] gr[reg2] gr[reg1] reg1 reg2 reg3, reg3 r0 1 2 note 14 2 r r r r r 1 1 1 1 1 1 i i i i i mulu note 22 imm9, reg2, reg3 w w w w w 0 1 0 0 1 i i i i 1 0 gr[reg3] || gr[reg2] gr[reg2] zero-extend (imm9) 1 2 note 14 2 nop 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 passes at least 1 cycle doing nothing. 1 1 1 not reg1, reg2 r r r r r 0 0 0 0 0 1 r r r r r gr[reg2] not (gr[reg1]) 1 1 1 0 0 1 b b b 1 1 1 1 1 0 r r r r r bit#3, disp16[reg1] d d d d d d d d d d d d d d d d adr gr[reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, z flag) 3 note 3 3 note 3 3 note 3 r r r r r 1 1 1 1 1 1 r r r r r not1 reg2, [reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 adr gr[reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, z flag) 3 note 3 3 note 3 3 note 3 or reg1, reg2 r r r r r 0 0 1 0 0 0 r r r r r gr[reg2] gr[reg2] or gr [reg1] 1 1 1 0 r r r r r 1 1 0 1 0 0 r r r r r ori imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] or zero-extend (imm16) 1 1 1 0 0 0 0 0 0 1 1 1 1 0 i i i i i l list12, imm5 l l l l l l l l l l l 0 0 0 0 1 store-memory (sp ? 4, gr[reg in list12], word) sp sp ? 4 repeat 1 steps above until regs in list12 is stored sp sp-zero-extend (imm5) n+1 note 4 n+1 note 4 n+1 note 4 0 0 0 0 0 1 1 1 1 0 i i i i i l prepare list12, imm5, sp/imm note 15 l l l l l l l l l l l f f 0 1 1 store-memory (sp ? 4, gr[reg in list12], word) gr[reg in list12] load-memory (sp, word) sp sp + 4 repeat 2 steps above until regs in list12 is loaded pc gr[reg1] n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 note 8 note 13 note 13 note 16 imm16/imm32 appendix d instruction set list 803 user?s manual u14492ej4v1ud (4/5) execution clock flags mnemonic operands opcode operation i r i cy ov s z sat 0 0 0 0 0 1 1 1 1 1 1 0 0 0 00 reti 0 0 0 0 0 0 0 1 0 1 0 0 0 0 00 if psw.ep = 1 then pc eipc psw eipsw else if psw.np = 1 then pc fepc psw fepsw else pc eipc psw eipsw 4 4 4 r r r r r r r r r r 1 1 1 1 1 1 r r r rr reg1, reg2 0 0 0 0 0 0 0 0 1 0 1 0 0 0 00 gr[reg2] gr[reg2] arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5, reg2 r r r r r 0 1 0 1 0 1 i i i ii gr[reg2] gr[reg2] arithmetically shift right by zero- extend (imm5) 1 1 1 0 r r r r r 1 1 1 1 1 1 0 c c cc sasf cccc, reg2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 00 if conditions are satisfied then gr[reg2] (gr[reg2] logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2] logically shift left by 1) or 00000000h 1 1 1 reg1, reg2 r r r r r 0 0 0 1 1 0 r r r rr gr[reg2] saturated (gr[reg2] + gr[reg1]) 1 1 1 satadd imm5, reg2 r r r r r 0 1 0 0 0 1 i i i ii gr[reg2] saturated (gr[reg2] + sign-extend (imm5)) 1 1 1 satsub reg1, reg2 r r r r r 0 0 0 1 0 1 r r r rr gr[reg2] saturated (gr[reg2] ? gr[reg1]) 1 1 1 r r r r r 1 1 0 0 1 1 r r r rr satsubi imm16, reg1, reg2 i i i i i i i i i i i i i i ii gr[reg2] saturated (gr[reg1] ? sign-extend (imm16)) 1 1 1 satsubr reg1, reg2 r r r r r 0 0 0 1 0 0 r r r rr gr[reg2] saturated (gr[reg1] ? gr[reg2]) 1 1 1 r r r r r 1 1 1 1 1 1 0 c c cc setf cccc, reg2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1 0 0 b b b 1 1 1 1 1 0 r r r rr bit#3, disp16 [reg1] d d d d d d d d d d d d d d dd adr gr[reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 1) 3 note 3 3 note 3 3 note 3 r r r r r 1 1 1 1 1 1 r r r rr set1 reg2, [reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 0 00 adr gr[reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, 1) 3 note 3 3 note 3 3 note 3 r r r r r 1 1 1 1 1 1 r r r rr reg1, reg2 0 0 0 0 0 0 0 0 1 1 0 0 0 0 00 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 r r r r r 0 1 0 1 1 0 i i i ii shl imm5, reg2 gr[reg2] gr[reg2] logically shift left by zero-extend (imm5) 1 1 1 0 r r r r r 1 1 1 1 1 1 r r r rr reg1, reg2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 00 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5, reg2 r r r r r 0 1 0 1 0 0 i i i ii gr[reg2] gr[reg2] logically shift right by zero-extend (imm5) 1 1 1 0 sld.b disp7[ep], reg2 r r r r r 0 1 1 0 d d d d d dd adr ep + zero-extend (disp7) gr[reg2] sign-extend (load-memory (adr, byte)) 1 1 note 9 sld.bu disp4[ep], reg2 r r r r r 0 0 0 0 1 1 0 d d dd adr ep + zero-extend (disp4) gr[reg2] zero-extend (load-memory (adr, byte)) 1 1 note 9 sld.h disp8[ep], reg2 r r r r r 1 0 0 0 d d d d d dd adr ep + zero-extend (disp8) gr[reg2] sign-extend (load-memory (adr, halfword)) 1 1 note 9 note 18 note 19 appendix d instruction set list 804 user?s manual u14492ej4v1ud (5/5) execution clock flags mnemonic operands opcode operation i r i cy ov s z sat sld.hu disp5[ep], reg2 r r r r r 0 0 0 0 1 1 1 d d d d adr ep + zero-extend (disp5) gr[reg2] zero-extend (load-memory (adr, halfword)) 1 1 note 9 sld.w disp8[ep], reg2 r r r r r 1 0 1 0 d d d d d d 0 adr ep + zero-extend (disp8) gr[reg2] load-memory (adr, word) 1 1 note 9 sst.b reg2, disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep + zero-extend (disp7) store-memory (adr, gr[reg2], byte) 1 1 1 sst.h reg2, disp8[ep] r r r r r 1 0 0 1 d d d d d d d adr ep + zero-extend (disp8) store-memory (adr, gr[reg2], halfword) 1 1 1 sst.w reg2, disp8[ep] r r r r r 1 0 1 0 d d d d d d 1 adr ep + zero-extend (disp8) store-memory (adr, gr[reg2], word) 1 1 1 r r r r r 1 1 1 0 1 0 r r r r r st.b reg2, disp16 [reg1] d d d d d d d d d d d d d d d d adr gr[reg1] + sign-extend (disp16) store-memory (adr, gr[reg2], byte) 1 1 1 r r r r r 1 1 1 0 1 1 r r r r r st.h reg2, disp16 [reg1] d d d d d d d d d d d d d d d 0 adr gr[reg1] + sign-extend (disp16) store-memory (adr, gr[reg2], halfword) 1 1 1 r r r r r 1 1 1 0 1 1 r r r r r st.w reg2, disp16 [reg1] d d d d d d d d d d d d d d d 1 adr gr[reg1] + sign-extend (disp16) store-memory (adr, gr[reg2], word) 1 1 1 r r r r r 1 1 1 1 1 1 r r r r r stsr regid, reg2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 gr[reg2] sr[regid] 1 1 1 sub reg1, reg2 r r r r r 0 0 1 1 0 1 r r r r r gr[reg2] gr[reg2] ? gr[reg1] 1 1 1 subr reg1, reg2 r r r r r 0 0 1 1 0 0 r r r r r gr[reg2] gr[reg1] ? gr[reg2] 1 1 1 switch reg1 0 0 0 0 0 0 0 0 0 1 0 r r r r r adr (pc + 2) + (gr[reg1] logically shift left by 1) pc (pc + 2) + (sign-extend (load-memory (adr, halfword))) logically shift left by 1 5 5 5 sxb reg1 0 0 0 0 0 0 0 0 1 0 1 r r r r r gr[reg1] sign-extend (gr[reg1] (7:0)) 1 1 1 sxh reg1 0 0 0 0 0 0 0 0 1 1 1 r r r r r gr[reg1] sign-extend (gr[reg1] (15:0)) 1 1 1 0 0 0 0 0 1 1 1 1 1 1 i i i i i trap vector 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 eipc pc + 4 (return pc) eipsw psw ecr.eicc exception code (40h to 4fh, 50h to 5fh) psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh (exception code: 40h to 4fh)) 00000050h (when vector is 10h to 1fh (exception code: 50h to 5fh)) 4 4 4 tst reg1, reg2 r r r r r 0 0 1 0 1 1 r r r r r result gr[reg2] and gr[reg1] 1 1 1 0 1 1 b b b 1 1 1 1 1 0 r r r r r bit#3, disp16 [reg1] d d d d d d d d d d d d d d d d adr gr[reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) 3 note 3 3 note 3 3 note 3 r r r r r 1 1 1 1 1 1 r r r r r tst1 reg2, [reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 adr gr[reg1] z flag not (load-memory-bit (adr, reg2)) 3 note 3 3 note 3 3 note 3 xor reg1, reg2 r r r r r 0 0 1 0 0 1 r r r r r gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 r r r r r 1 1 0 1 0 1 r r r r r xori imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 0 0 0 0 0 0 0 0 1 0 0 r r r r r gr[reg1] zero-extend (gr[reg1] (7:0)) 1 1 1 zxh reg1 0 0 0 0 0 0 0 0 1 1 0 r r r r r gr[reg1] zero-extend (gr[reg1] (15:0)) 1 1 1 notes 18, 20 note 21 note 19 note 21 note 8 note 8 appendix d instruction set list 805 user?s manual u14492ej4v1ud notes 1. dddddddd is the higher 8 bits of disp9. 2. 4 if there is an instruction to overwrite the contents of the psw immediately before 3. if there is no wait state (3 + num ber of read access wait states) 4. n is the total number of load registers in list12. (acco rding to the number of wait states. if there are no wait states, n is the number of r egisters in list12. when n = 0, t he operation is the same as n = 1.) 5. rrrrr : other than 00000 6. only the lower halfword of data is valid. 7. ddddddddddddddddddddd is the higher 21 bits of disp22. 8. ddddddddddddddd is the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states) 10. b : bit 0 of disp16 11. according to the number of wait stat es (2 if there are no wait states) 12. in this instruction, although the source register is regarded as reg2 for convenience of the mnemonic description, the reg1 field is used in the opcode. t herefore, the meanings of register specifications assigned in the mnemonic description and in the opc ode differ from those in other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii : lower 5 bits of imm9 iiii : higher 4 bits of imm9 14. shortened by 1 clock if reg2 = reg3 (lower 32 bits of result are not written to register) or reg3 = r0 (higher 32 bits of result are not written to register). 15. sp/imm: specify in bits 19 and 20 of sub-opcode. 16. ff = 00: load sp in ep. 01: load sign-extended 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit immediate data (bits 47 to 32) l ogically shifted 16 bits to the left in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. n + 3 clocks when imm = imm32 18. rrrrr : other than 00000 19. ddddddd is the higher 7 bits of disp8. 20. dddd is the higher 4 bits of disp5. 21. dddddd is the higher 6 bits of disp8. 22. do not make a combination that satisfies all the following conditions when using the ?mul reg1, reg2, reg3? instruction and ?mulu reg1, reg2, reg3? in struction. operation is not guaranteed when an instruction that satisfies the fo llowing conditions is executed. ? reg1 = reg3 ? reg1 reg2 ? reg1 r0 ? reg3 r0 user?s manual u14492ej4v1ud 806 appendix e revision history e.1 major revisions in this edition (1/3) page description p. 19 addition of note to table 1-1 differences between v850e/ia1 and v850e/ia2 p. 20 addition of notes 1 and 2 to table 1-2 differences between v850e/ia1 and v850e/ia2 register setting values p. 23 addition of note to 1.4 ordering information p. 24 addition of note 3 to 1.5 pin configuration (top view) p. 62 addition of caution to 3.4.5 (3) on-chip peripheral i/o area pp. 77, 93 addition of caution to 3.4.9 programmable peripheral i/o registers and modification of bit units for manipulation and initial values p. 94 modification of description in 3.4.11 system wait control register (vswc) p. 100 addition of note to 4.4 (1) bus cycle type configuration registers 0, 1 (bct0, bct1) p. 124 addition of caution 2 to 6.3.1 (1) dma source address registers 0h to 3h (dsa0h to dsa3h) p. 126 addition of caution 2 to 6.3.2 (1) dma destination address registers 0h to 3h (dda0h to dda3h) p. 128 addition of cautions 1 and 2 to 6.3.3 dma transfer count registers 0 to 3 (dbc0 to dbc3) pp. 131, 132 modification and addition of description to caution in 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) p. 143 deletion of note from table 6-2 external bus cycles during dma transfer (two-cycle transfer) pp. 143, 144 modification of description in 6.9 next address setting function and addition of note p. 145 addition of cautions 1 and 2 to 6.10 dma transfer start factors p. 146 addition of 6.13.1 restrictions related to dma transfer forcible termination p. 148 modification of description in 6.14 times related to dma transfer pp. 148, 149 addition of 6.15 (5) restrictions related to automatic clearing of tcn bit of dchcn register and (6) read values of dsan and ddan registers p. 150 modification of description in chapter 7 interrupt/exception processing function p. 244 addition of caution 2 to 9.1.5 (2) pwm mode 0: triangular w ave modulation (right-left symmetric waveform control) p. 292 addition of notes 1 and 2 to 9.2.4 (1) timer 1/timer 2 clock selection register (prm02) p. 328 addition of notes 1 and 2 to 9.3.4 (1) timer 1/timer 2 clock selection register (prm02) p. 331 addition of notes 1 and 2 to 9.3.4 (3) timer 2 count clock/control edge selection register 0 (cse0) p. 363 addition of 9.3.6 pwm output operation when timer 2 operates in compare mode p. 384 modification of description in figure 9-92 tm3 compare operation example (set/reset output mode) p. 407 addition of caution 2 to 10.2.3 (1) asynchronous serial interface mode register (asim0) p. 418 addition of caution to 10.2.5 (3) continuous transmission operation appendix e revision history user?s manual u14492ej4v1ud 807 (2/3) page description p. 435 addition of description of transfer rate to 10.3.1 features p. 438 modification of description in cautions 1 and 2 in 10.3.3 (1) asynchronous serial interface mode registers 10, 20 (asim10, asim20) p. 464 addition of caution 3 to 10.3.7 (2) (c) prescaler compare registers 1, 2 (prscm1, prscm2) pp. 466, 467 modification of description in table 10-8 baud rate generator setting data (brg = f xx /2) p. 509 addition of caution to table 11-2 configuration of messages and buffers p. 513 addition of description to 11.5 message processing p. 532 addition of description to note in figure 11-21 nominal bit time p. 538 modification of description in 11.10 (2) can message data length registers 00 to 31 (m_dlc00 to m_dlc31) and addition of note p. 540 modification of description in 11.10 (3) can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) and addition of note p. 550 modification of description in 11.10 (8) can message status registers 00 to 31 (m_stat00 to m_stat31) p. 555 modification of description in 11.10 (11) can global interrupt pending register (cgintp) p. 556 modification of description in 11.10 (12) can1 interrupt pending register (c1intp) p. 557 addition of caution to 11.10 (13) can stop register (cstop) pp. 558, 559 modification of description in 11.10 (14) can global status register (cgst) and addition of description to note and caution pp. 562, 563 modification of description in 11.10 (16) can main clock selection register (cgcs) and addition of description to note and caution p. 565 addition of caution to 11.10 (18) can message search start/result register (cgmss (during write)/cgmsr (during read)) p. 567 addition of description to 11.10 (19) can1 address mask a registers l and h (c1maskla and c1maskha) p. 571 addition of description to caution in 11.10 (20) can1 control register (c1ctrl) pp. 574, 575 addition of description to caution in 11.10 (21) can1 definition register (c1def) p. 580 addition of description to 11.10 (24) can1 interrupt enable register (c1ie) p. 588 addition of description to 11.10 (28) can1 synchronization control register (c1sync) and addition of note p. 590 addition of description to figure 11-27 initialization processing p. 593 addition of note to figure 11-32 can1 synchronization c ontrol register (c1sync) settings p. 598 addition of description to figure 11-37 message buffer settings p. 601 addition of figure 11-40 can message status registers 00 to 31 (m_stat00 to m_stat31) settings p. 603 modification of description in figure 11-42 setting of receive completion interrupt and reception operation using reception polling p. 604 addition of figure 11-43 can message search start/result register (cgmss/cgmsr) settings p. 606 addition of description to figure 11-47 can stop mode settings p. 607 addition of description to figure 11-48 clearing of can stop mode p. 608 modification of description in 11.12 rules for correct setting of baud rate p. 612 modification of description in figure 11-50 sequential data read p. 613 addition of description to caution in 11.13.2 burst read mode appendix e revision history user?s manual u14492ej4v1ud 808 (3/3) page description p. 616 addition of description to 11.16 cautions on use p. 703 addition of 14.4 operation of port function p. 769 addition of caution to 18.1 (4) (c) read cycle (clkout synchronous/asynchronous, 1 wait) p. 770 addition of caution to 18.1 (4) (d) write cycle (clkout synchronous/asynchronous, 1 wait) p. 771 addition of caution to 18.1 (4) (e) bus hold p. 774 addition of notes 1 and 2 to 18.1 (7) timer operating frequency p. 780 modification of description of v pp supply voltage (v ppl ) in basic characteristics in 18.2 flash memory programming mode ( pd70f3116 only) p. 784 addition of appendix a notes pp. 802, 805 addition of note 22 to mul, mulu in appendix d d.2 instruction set (alphabetical order) p. 806 modification of description in appendix e revision history appendix e revision history user?s manual u14492ej4v1ud 809 e.2 revision history up to previous edition the following table shows the revision hi story up to the previous editions. t he ?applied to:? column indicates the chapters of each edition in wh ich the revision was applied. (1/10) edition major revision from pr evious edition applied to: ? deletion of the following product pd703117gj-xxx-uen ? addition of the following products pd703116gj-xxx-uen, 703116gj(a)-xxx-uen, 703116gj(a1)-xxx-uen, 70f3116gj(a)-uen, 70f3116gj(a1)-uen ? change of status of the following produc t from ?under development? to ?developed? pd70f3116gj-uen ? clarification of bits defined as reserved word s in the device file ( names of bits whose numbers are in angle brackets) throughout addition of table 1-1 differ ences between v850e/ia1 and v850e/ia2 addition of table 1-2 differences be tween v850e/ia1 and v850e/ia2 register setting values modification of description in 1.3 applications modification of description in 1.4 ordering information modification of caution in 1.5 pin configuration addition of 1.7 diffe rences between products chapter 1 introduction modification of pin status of astb (pct6) and hldrq (pcm3) pins in 2.2 pin status modification of description in 2.4 types of pin i/o circuit and c onnection of unused pins modification of i/o circuit type from 5- k to 5-ac in 2.5 pin i/o circuits chapter 2 pin functions modification of description in 3.4.5 (1) (a) memory map modification of description in 3.4.5 (2) internal ram area addition of note and modification of caution in 3.4.5 (3) on-chip peripheral i/o area deletion of part of description in 3.4.7 (1) program space modification of part of description in example of wrap-around application in 3.4.7 (2) data space modification of figure 3-6 recommended memory map modification of description in 3. 4.8 peripheral i/o registers modification of description in 3.4.9 programmable peripheral i/o registers modification of bit name in 3.4.9 (1) peri pheral area selection control register (bpc) modification of description of programmable peripheral i/o register area in 3.4.9 programmable peripheral i/o registers modification of description on bits that can be manipulated, modification of description in table, and addition of remark in 3.4.11 system wait control register (vswc) chapter 3 cpu function modification and addition of description in 4.2.1 pin status during internal rom, internal ram, and peripheral i/o access addition of note in 4.3 memory block function 2nd edition addition of caution in 4.3.1 (1) chip area se lection control registers 0, 1 (csc0, csc1) chapter 4 bus control function appendix e revision history user?s manual u14492ej4v1ud 810 (2/10) edition major revision from pr evious edition applied to: modification of description in table in 4.5.1 number of access clocks addition of caution in 4.6.1 (2) a ddress wait control register (awc) modification of timing chart in figur e 4-2 example of wait insertion addition of description in 4.8.1 function outline modification of description in 4.9 bus priority order modification of description (1) in 4.10.1 program space chapter 4 bus control function modification of timing chart in figur e 5-1 sram, external rom, exter nal i/o access timing chapter 5 memory access control function addition of description in 6.3.3 dma transfe r count registers 0 to 3 (dbc0 to dbc3) addition of caution and modifi cation of bit settings in 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) modification of description and caution in 6. 3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) modification of description on bits that can be manipulated in 6.3.6 dma disable status register (ddis) modification of description on bits that can be manipulated in 6.3.7 dma restart register (drst) modification of description and addi tion of bit names and bit description in 6.3.8 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) addition of description in 6.5.1 single transfer mode addition of description in 6. 5.2 single-step transfer mode addition of caution in 6.6.1 two-cycle transfer modification of description in 6.7. 1 transfer type and transfer object modification of description in table 6-1 relationship between transfer type and transfer object addition and deletion of description in table 6- 2 external bus cycles during dma transfer (two-cycle transfer) addition of caution in 6.8 dma channel priorities addition of part of description in remark in 6.13 forcible termination modification of description in 6.14 (3 ) times related to dma transfer addition of 6.14 (5) dma start factor chapter 6 dma functions (dma controller) modification of description in chapter 7 interrupt/exception processing function modification of description in table 7- 1 interrupt/exception source list modification of description in figure 7-2 acknowledging non-maskable interrupt request addition of caution in 7.3.5 interrupt mask registers 0 to 3 (imr0 to imr3) addition of caution and modifica tion of bit description in 7.3.8 (2) signal edge selection registers 10, 11 (sesa10, sesa11) 2nd edition addition of caution in 7.3.8 (3) valid edge selection register (sesc) chapter 7 interrupt/ exception processing function appendix e revision history user?s manual u14492ej4v1ud 811 (3/10) edition major revision from pr evious edition applied to: addition of caution and addition of caution in bit description in 7.3.8 (4) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) modification of description in figure 7-14 pipeline operation at interrupt request acknowledgement (outline) addition and modification of description in 7. 8 periods in which interrupts are not acknowledged chapter 7 interrupt/ exception processing function modification of description in 8.3.1 direct mode addition of description on caution in 8.3.2 pll mode modification of description on bit that can be manipulated and data setting sequence to ckc, and modification of caution in 8. 3.4 clock control register (ckc) modification of register symbol and initial value in 8.4 pll lockup modification of note in figure 8-1 po wer save mode state transition diagram modification of data setting sequence to psc and c aution in 8.5.2 (3) power save control register (psc) modification of description in table 8- 4 operation status in idle mode addition of note and addition and m odification of description in 8.5.4 (2) release of idle mode modification of description in table 8-6 operation status in software stop mode addition of note and addition and modification of description in 8.5.5 (2) release of software stop mode addition and modification of de scription and modification of ti ming chart in 8.6.1 (1) securing the time using an on-chip time base counter modification of timing chart in 8.6.1 (2) se curing the time according to the signal level width (reset pin input) modification of description in tabl e 8-8 counting time examples (f xx = 10 f x ) chapter 8 clock generation function modification of figure 9-1 bl ock diagram of timer 0 (mode 0: symmetric triangular wave, mode 1: asymmetric triangular wave) modification of figure 9-2 block diagram of timer 0 (mode 2: sawtooth wave) addition of caution in table 9-1 timer 0 operation modes addition of caution in 9.1.3 (3) dead-time timer reload registers 0, 1 (dtrr0, dtrr1) modification of bit names in 9.1.4 (2) ti mer control registers 00, 01 (tmc00, tmc01) addition of description, modifi cation of bit names, and addition of caution in bit description in 9.1.4 (3) timer unit control registers 00, 01 (tuc00, tuc01) addition of bit names and bit descriptions in 9.1.4 (4) timer output mode registers 0, 1 (tomr0, tomr1) addition of figure 9-7 output waveforms of to000 and to001 in pwm mode 0 (symmetric triangular waves) (wit hout dead time (tm0ced0 bit = 1)) addition of figure 9-8 output waveforms of to000 and to001 in pwm mode 0 (symmetric triangular waves) (wit h dead time (tm0ced0 bit = 0)) modification of bit names in 9.1.4 (5) pw m output enable registers 0, 1 (poer0, poer1) 2nd edition addition of caution, modifica tion of bit names and bit descr iptions, and addition of figures 9-9 to 9-14 in 9.1.4 (6) pwm software timing output registers 0, 1 (psto0, psto1) chapter 9 timer/counter function (real- time pulse unit) appendix e revision history user?s manual u14492ej4v1ud 812 (4/10) edition major revision from pr evious edition applied to: addition of remark in 9.1.5 operation addition of remark in figure 9-30 operat ion timing in pwm mode 2 (sawtooth wave) modification of figure 9-45 block diagram of timer 1 modification of bit names and addition of cauti on in bit description in 9.2.4 (3) timer control registers 10, 11 (tmc10, tmc11) modification of bit description in 9.2.4 (5) signal edge selection registers 10, 11 (sesa10, sesa11) modification of bit names in 9.2.4 (7) st atus registers 0, 1 (status0, status1) modification of description in table 9-8 timer 2 configuration list addition of table 9-9 captur e/compare operation sources addition of table 9-10 output lev el sources during timer output modification of figure 9-62 block diagram of timer 2 addition of caution in 9.3.3 (3) timer 2 sub-channel n main capt ure/compare register (cvpen0) (n = 1 to 4) addition of caution in 9.3.3 (4) timer 2 sub-channel n sub captur e/compare register (cvsen0) (n = 1 to 4) modification of description on bits that can be manipulated in 9.3.4 (2) timer 2 clock stop register 0 (stopte0) modification of description on bits that can be manipulated in 9.3.4 (3) timer 2 count clock/control edge selection register 0 (cse0) modification of description on bits that c an be manipulated in 9.3.4 (4) timer 2 sub- channel input event edge selection register 0 (sese0) modification of description on bits that can be manipulated, addition of caution, and addition of caution in bit description in 9.3.4 (5) timer 2 time base control register 0 (tcre0) modification of description on bits that can be manipulated in 9.3.4 (6) timer 2 output control register 0 (octle0) addition of caution in bit description in 9.3.4 (8) timer 2 sub-channel 1, 2 capture/compare control register (cmse120) addition of caution in bit description in 9.3.4 (9) timer 2 sub-channel 3, 4 capture/compare control register (cmse340) modification of description on bits that can be manipulated and modification of initial value in 9.3.4 (10) timer 2 time bas e status register 0 (tbstate0) modification of description on bits that c an be manipulated in 9.3.4 (11) timer 2 capture/compare 1 to 4 status register 0 (ccstate0) modification of description on bits that can be manipulated in 9.3.4 (12) timer 2 output delay register 0 (odele0) modification of caution in 9.4.3 (1) (a) selection of the external count clock addition of caution and modifica tion of bit names in 9.4.4 (2) timer control register 30 (tmc30) addition of caution in 9.4.5 (1) count operation 2nd edition modification of figure 9-88 compare operation example chapter 9 timer/counter function (real- time pulse unit) appendix e revision history user?s manual u14492ej4v1ud 813 (5/10) edition major revision from pr evious edition applied to: addition of note and deletion of caution in figure 9-95 cycle measurement operation timing example modification of figure 9-97 exampl e of timing during tm4 operation modification of bit names in 9.5.4 (1 ) timer control register 4 (tmc4) modification of figure 9-98 tm 4 compare operation example chapter 9 timer/counter function (real- time pulse unit) addition of caution and modifi cation of bit names and bit descriptions in 10.2.3 (1) asynchronous serial interfac e mode register 0 (asim0) modification of description on bits that c an be manipulated in 10.2.3 (2) asynchronous serial interface status register 0 (asis0) modification of bit names and addition of c aution in bit description in 10.2.3 (3) asynchronous serial interface trans mission status register 0 (asif0) modification of description on bits that can be manipulated in 10.2.3 (4) reception buffer register 0 (rxb0) modification of description on bits that c an be manipulated in 10.2.3 (5) transmission buffer register 0 (txb0) addition and modification of description in 10.2.5 (3) continuous transmission operation addition of figure 10-4 conti nuous transmission processing flow addition of note and modification of descrip tion in table in figure 10-5 continuous transmission starting procedure modification of description in table in fi gure 10-6 continuous tr ansmission end procedure addition of caution in figure 10-7 asynchr onous serial interface reception completion interrupt timing modification of description on bits that can be manipulated and addition of caution in 10.2.6 (2) (a) clock selection register 0 (cksr0) modification of description on bits that can be manipulated in 10.2.6 (2) (b) baud rate generator control register 0 (brgc0) addition of baud rate item in table 10-3 baud rate generator setting data addition of (2) in 10.2.7 precautions modification of bit names in 10.3.3 (1) asyn chronous serial interface mode registers 10, 20 (asim10, asim20) modification of bit names in 10. 3.3 (3) asynchronous serial in terface status registers 1, 2 (asis1, asis2) modification of description on bits that can be manipulated in 10.3.3 (4) 2-frame continuous reception buffer registers 1, 2 (r xb1, rxb2)/reception buffer registers l1, l2 (rxbl1, rxbl2) addition of caution in 10.3.4 (1) reception completion interrupt (intsrn) addition of 10.3.5 (3) continuous transmission of 3 or more frames modification of bit names in 10.3.7 (2) (b) prescaler mode registers 1, 2 (prsm1, prsm2) modification of description on bits that can be manipulated in 10.3.7 (2) (c) prescaler compare registers 1, 2 (prscm1, prscm2) 2nd edition addition of 10.3.7 (3) allowable baud rate range during reception chapter 10 serial interface function appendix e revision history user?s manual u14492ej4v1ud 814 (6/10) edition major revision from pr evious edition applied to: addition of 10.3.7 (4) transfer rate in 2-frame continuous reception modification of bit names in 10.4.3 (1) cl ocked serial interface mode registers 0, 1 (csim0, csim1) modification of description on bits that can be manipulated in 10.4.3 (4) clocked serial interface reception buffer registers l0, l1 (sirbl0, sirbl1) modification of description on bits that can be manipulated in 10.4.3 (6) clocked serial interface read-only reception buffer r egisters l0, l1 (sirbel0, sirbel1) modification of description on bits that can be manipulated in 10.4.3 (8) clocked serial interface transmission buffer regi sters l0, l1 (sotbl0, sotbl1) modification of description on bits that can be manipulated in 10.4.3 (10) clocked serial interface initial transmission buffer r egisters l0, l1 (sotbfl0, sotbfl1) modification of description on bits that can be manipulated in 10.4.3 (12) serial i/o shift registers l0, l1 (siol0, siol1) modification of description on bits that can be manipulated in 10.4.6 (2) (c) prescaler compare register 3 (prscm3) chapter 10 serial interface function modification of figure 11-1 block diagram of fcan addition of description in 11.5 message processing modification of description in t able 11-6 data length code settings modification of description in 11.8.7 (1) prescaler modification of description in 11.8.7 (2) nominal bit time (8 to 25 time quantum) addition of caution and modification of bi t description in 11.10 (2) can message data length registers 00 to 31 (m_dlc00 to m_dlc31) deletion of one of notes for bits, addition of caution and modification of bit description in 11.10 (3) can message control registers 00 to 31 (m_ctrl00 to m_ctrl31) addition of caution in bit description in 11.10 (4) can message time stamp registers 00 to 31 (m_time00 to m_time31) modification of description in 11.10 (6) ca n message id registers l00 to l31 and h00 to h31 (m_idl00 to m_idl31 and m_idh00 to m_idh31) deletion of part of bit description in 11.10 (7 ) can message configuration registers 00 to 31 (m_conf00 to m_conf31) addition of bit description in 11.10 (8) can message status registers 00 to 31 (m_stat00 to m_stat31) modification of description on bits that can be manipulated, modificati on of caution in bit description, and addition of note in 11.10 (14) can global status register (cgst) modification of description on bits that c an be manipulated in 11.10 (15) can global interrupt enable register (cgie) modification of figure 11-25 fcan clocks modification of bit description in 11.10 (18) can message search start/result register (cgmss (during write)/cgmsr (during read)) addition of caution and deletion of part of bit description in 11.10 (19) can1 address mask a registers l and h (c1maskla and c1maskha) 2nd edition addition of caution and addition of bit descripti on in 11.10 (20) can1 control register (c1ctrl) chapter 11 fcan controller appendix e revision history user?s manual u14492ej4v1ud 815 (7/10) edition major revision from pr evious edition applied to: modification of description on bits that c an be manipulated, addition and deletion of bit description, and deletion of caut ion and modification of bit descr iption in 11.10 (21) can1 definition register (c1def) modification of description on bits that can be manipulated in 11.10 (24) can1 interrupt enable register (c1ie) modification of bit settings in 11.10 (25) can1 bus active register (c1ba) modification of caution and bit settings in 11.10 (28) can1 synchronization control register (c1sync) modification of figure 11-28 can global interrupt enable register (cgie) settings modification of figure 11-35 can1 addr ess mask a registers l and h (c1maskla and c1maskha) (a = 0 to 3) settings modification of 11.11.3 receive setting modification of figure 11-44 can stop mode settings modification of figure 11-45 clearing of can stop mode modification of description in 11.12 ru les for correct setting of baud rate modification of description in 11.14.2 burst read mode addition of description in 11.15.1 interrupts that are generated for fcan controller modification of description in 11.15.2 in terrupts that are generated for global can interface addition of <2> and <3> in 11.17 cautions on use chapter 11 fcan controller addition of description in 12.1 (2) event detection function modification of figure 12-1 image of nbd space addition of description in 12.4.1 (1) (b) read command addition of caution in 12.4.2 (2) (b) nbd event address register (evtu_a) addition of description for nbdll, modifi cation of description on bits that can be manipulated, and deletion of part of remark in 12.5 (1) ram access data buffer register l (nbdl) addition of description for nbdhl, modification of descr iption on bits that can be manipulated, and deletion of part of remark in 12.5 (2) ram access data buffer register h (nbdh) addition of description to (1) in 12.6.1 general restrictions addition of description and caution to (4) in 12.6.3 restrictions related to nbd event trigger function chapter 12 nbd function ( pd70f3116) modification of description on bits that can be manipulated, modifica tion of bit names, and addition of bit descriptions in 13.3 (1) a/d scan mode registers 00 and 10 (adscm00, adscm10) modification of description on bits that can be manipulated and modification of bit description in 13.3 (2) a/d scan mode registers 01 and 11 (adscm01, adscm11) modification of description on bits that can be manipulated and modifica tion of bit names in 13.3 (3) a/d voltage detection mode registers 0 and 1 (adetm0, adetm1) addition of description in 13.10.4 (1) halt mode 2nd edition modification of description in 13.10.4 (2) idle mode, software stop mode chapter 13 a/d converter appendix e revision history user?s manual u14492ej4v1ud 816 (8/10) edition major revision from pr evious edition applied to: addition of 13.10.6 timing that make s the a/d conversion result undefined addition of 13.11 how to read a/d converter characteristics table chapter 13 a/d converter modification of block type and addition of caution in 14.2 (1) functions of each port modification of figure 14- 2 type b block diagram modification of figure 14- 3 type c block diagram modification of figure 14- 4 type d block diagram addition of figure 14-5 type e block diagram modification of figure 14- 8 type h block diagram modification of figure 14- 9 type j block diagram modification of figure 14- 10 type m block diagram modification of figure 14- 11 type n block diagram modification of figure 14- 12 type o block diagram addition of figure 14-13 type p block diagram modification of block type in 14.3. 2 (1) operation in control mode modification of block type in 14.3. 6 (1) operation in control mode modification of block type in 14.3. 9 (1) operation in control mode modification of block type in 14.3. 10 (1) operation in control mode addition of caution and addition of caution in bit description in 14.4.3 (1) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) chapter 14 port functions addition and modification of descrip tion in table 15-2 initial values of cpu, internal ram, and on-chip peripheral i/o after reset chapter 15 reset function addition of caution in 16.2 writing by flash programmer addition of note in table 16-1 connection of v850e/ia1 flash programming adapter (fa- 144gj-8eu) addition of batch erase command in erase item in table 16-4 commands for controlling flash memory addition of 16.7.3 outline of self-programming interface addition of 16.7.5 software environment addition of 16.7.6 self-programming function number addition of 16.7.7 calling parameters addition of 16.7.8 contents of ram parameters addition of 16.7.9 errors during self-programming addition of 16.7.10 flash information addition of 16.7.11 area number addition of initial value 00h and modificati on of caution in 16.7.12 flash programming mode control register (flpmc) addition of 16.7.13 calling device internal processing addition of 16.7.14 erasing flash memory flow 2nd edition addition of 16.7.15 continuous writing flow chapter 16 flash memory ( pd70f3116) appendix e revision history user?s manual u14492ej4v1ud 817 (9/10) edition major revision from pr evious edition applied to: addition of 16.7.16 internal verify flow addition of 16.7.17 acquiri ng flash information flow addition of 16.7.18 self-programming library modification of caution in 16.8 how to di stinguish flash memory and mask rom versions chapter 16 flash memory ( pd70f3116) addition of chapter 17 turning on/off power chapter 17 turning on/off power 2nd edition modification of description in b.2 instru ction set (alphabetical order) appendix b instruction set list modification of description in 4.2.1 pin stat us during internal rom, internal ram, and on- chip peripheral i/o access chapter 4 bus control function addition of description to 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) addition of description to 6.3.1 (1) dma s ource address registers 0h to 3h (dsa0h to dsa3h) addition of description to 6.3.2 dma destinat ion address registers 0 to 3 (dda0 to dda3) addition of description to 6.3.2 (1) dma desti nation address registers 0h to 3h (dda0h to dda3h) addition of description to 6 . 3.3 dma transfer count registers 0 to 3 (dbc0 to dbc3) addition of description to 6.3.4 dma addre ssing control registers 0 to 3 (dadc0 to dadc3) addition of description to 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) addition and modification of descr iption in 6.3.6 dma disable status register (ddis) addition of description to 6.3.7 dma restart register (drst) addition of description to 6.3.8 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) modification of description in table 6-1 relationship between transfer type and transfer object modification of description in remark in 6.7.1 transfer type and transfer object modification and addition of description in 6.9 next address setting function modification of description in 6.11 forcible interruption modification of description in 6. 14 (4) bus arbitration for cpu addition of 6.14 (6) execution of pr ogram and dma transfer in internal ram chapter 6 dma functions (dma controller) addition of caution to 7.3.4 interrupt control register (xxicn) 3rd edition addition of caution to 7.3.6 in-s ervice priority register (ispr) chapter 7 interrupt/ exception processing function appendix e revision history user?s manual u14492ej4v1ud 818 (10/10) edition major revision from pr evious edition applied to: modification of description in remark in 9.1.5 (2) pwm mode 0: triangular wave modulation (right-left symmetr ic waveform control) chapter 9 timer/counter function (real- time pulse unit) addition of caution to 14.2 (1) functions of each port modification of description in figure 14-14 example of noise elimination timing chapter 14 port functions addition of chapter 18 electrical specifications chapter 18 electrical specifications addition of chapter 19 package drawing chapter 19 package drawing addition of chapter 20 recommended soldering conditions chapter 20 recommended soldering conditions addition of appendix a notes on target system design appendix a notes on target system design 3rd edition addition of appendix e revision history appendix e revision history |
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